sirfsoc_uart.c 21 KB

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  1. /*
  2. * Driver for CSR SiRFprimaII onboard UARTs.
  3. *
  4. * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
  5. *
  6. * Licensed under GPLv2 or later.
  7. */
  8. #include <linux/module.h>
  9. #include <linux/ioport.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/init.h>
  12. #include <linux/sysrq.h>
  13. #include <linux/console.h>
  14. #include <linux/tty.h>
  15. #include <linux/tty_flip.h>
  16. #include <linux/serial_core.h>
  17. #include <linux/serial.h>
  18. #include <linux/clk.h>
  19. #include <linux/of.h>
  20. #include <linux/slab.h>
  21. #include <linux/io.h>
  22. #include <asm/irq.h>
  23. #include <asm/mach/irq.h>
  24. #include <linux/pinctrl/consumer.h>
  25. #include "sirfsoc_uart.h"
  26. static unsigned int
  27. sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count);
  28. static unsigned int
  29. sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count);
  30. static struct uart_driver sirfsoc_uart_drv;
  31. static const struct sirfsoc_baudrate_to_regv baudrate_to_regv[] = {
  32. {4000000, 2359296},
  33. {3500000, 1310721},
  34. {3000000, 1572865},
  35. {2500000, 1245186},
  36. {2000000, 1572866},
  37. {1500000, 1245188},
  38. {1152000, 1638404},
  39. {1000000, 1572869},
  40. {921600, 1114120},
  41. {576000, 1245196},
  42. {500000, 1245198},
  43. {460800, 1572876},
  44. {230400, 1310750},
  45. {115200, 1310781},
  46. {57600, 1310843},
  47. {38400, 1114328},
  48. {19200, 1114545},
  49. {9600, 1114979},
  50. };
  51. static struct sirfsoc_uart_port sirfsoc_uart_ports[SIRFSOC_UART_NR] = {
  52. [0] = {
  53. .port = {
  54. .iotype = UPIO_MEM,
  55. .flags = UPF_BOOT_AUTOCONF,
  56. .line = 0,
  57. },
  58. },
  59. [1] = {
  60. .port = {
  61. .iotype = UPIO_MEM,
  62. .flags = UPF_BOOT_AUTOCONF,
  63. .line = 1,
  64. },
  65. },
  66. [2] = {
  67. .port = {
  68. .iotype = UPIO_MEM,
  69. .flags = UPF_BOOT_AUTOCONF,
  70. .line = 2,
  71. },
  72. },
  73. };
  74. static inline struct sirfsoc_uart_port *to_sirfport(struct uart_port *port)
  75. {
  76. return container_of(port, struct sirfsoc_uart_port, port);
  77. }
  78. static inline unsigned int sirfsoc_uart_tx_empty(struct uart_port *port)
  79. {
  80. unsigned long reg;
  81. reg = rd_regl(port, SIRFUART_TX_FIFO_STATUS);
  82. if (reg & SIRFUART_FIFOEMPTY_MASK(port))
  83. return TIOCSER_TEMT;
  84. else
  85. return 0;
  86. }
  87. static unsigned int sirfsoc_uart_get_mctrl(struct uart_port *port)
  88. {
  89. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  90. if (!(sirfport->ms_enabled)) {
  91. goto cts_asserted;
  92. } else if (sirfport->hw_flow_ctrl) {
  93. if (!(rd_regl(port, SIRFUART_AFC_CTRL) &
  94. SIRFUART_CTS_IN_STATUS))
  95. goto cts_asserted;
  96. else
  97. goto cts_deasserted;
  98. }
  99. cts_deasserted:
  100. return TIOCM_CAR | TIOCM_DSR;
  101. cts_asserted:
  102. return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
  103. }
  104. static void sirfsoc_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
  105. {
  106. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  107. unsigned int assert = mctrl & TIOCM_RTS;
  108. unsigned int val = assert ? SIRFUART_AFC_CTRL_RX_THD : 0x0;
  109. unsigned int current_val;
  110. if (sirfport->hw_flow_ctrl) {
  111. current_val = rd_regl(port, SIRFUART_AFC_CTRL) & ~0xFF;
  112. val |= current_val;
  113. wr_regl(port, SIRFUART_AFC_CTRL, val);
  114. }
  115. }
  116. static void sirfsoc_uart_stop_tx(struct uart_port *port)
  117. {
  118. unsigned int regv;
  119. regv = rd_regl(port, SIRFUART_INT_EN);
  120. wr_regl(port, SIRFUART_INT_EN, regv & ~SIRFUART_TX_INT_EN);
  121. }
  122. void sirfsoc_uart_start_tx(struct uart_port *port)
  123. {
  124. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  125. unsigned long regv;
  126. sirfsoc_uart_pio_tx_chars(sirfport, 1);
  127. wr_regl(port, SIRFUART_TX_FIFO_OP, SIRFUART_TX_FIFO_START);
  128. regv = rd_regl(port, SIRFUART_INT_EN);
  129. wr_regl(port, SIRFUART_INT_EN, regv | SIRFUART_TX_INT_EN);
  130. }
  131. static void sirfsoc_uart_stop_rx(struct uart_port *port)
  132. {
  133. unsigned long regv;
  134. wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
  135. regv = rd_regl(port, SIRFUART_INT_EN);
  136. wr_regl(port, SIRFUART_INT_EN, regv & ~SIRFUART_RX_IO_INT_EN);
  137. }
  138. static void sirfsoc_uart_disable_ms(struct uart_port *port)
  139. {
  140. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  141. unsigned long reg;
  142. sirfport->ms_enabled = 0;
  143. if (!sirfport->hw_flow_ctrl)
  144. return;
  145. reg = rd_regl(port, SIRFUART_AFC_CTRL);
  146. wr_regl(port, SIRFUART_AFC_CTRL, reg & ~0x3FF);
  147. reg = rd_regl(port, SIRFUART_INT_EN);
  148. wr_regl(port, SIRFUART_INT_EN, reg & ~SIRFUART_CTS_INT_EN);
  149. }
  150. static void sirfsoc_uart_enable_ms(struct uart_port *port)
  151. {
  152. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  153. unsigned long reg;
  154. unsigned long flg;
  155. if (!sirfport->hw_flow_ctrl)
  156. return;
  157. flg = SIRFUART_AFC_RX_EN | SIRFUART_AFC_TX_EN;
  158. reg = rd_regl(port, SIRFUART_AFC_CTRL);
  159. wr_regl(port, SIRFUART_AFC_CTRL, reg | flg);
  160. reg = rd_regl(port, SIRFUART_INT_EN);
  161. wr_regl(port, SIRFUART_INT_EN, reg | SIRFUART_CTS_INT_EN);
  162. uart_handle_cts_change(port,
  163. !(rd_regl(port, SIRFUART_AFC_CTRL) & SIRFUART_CTS_IN_STATUS));
  164. sirfport->ms_enabled = 1;
  165. }
  166. static void sirfsoc_uart_break_ctl(struct uart_port *port, int break_state)
  167. {
  168. unsigned long ulcon = rd_regl(port, SIRFUART_LINE_CTRL);
  169. if (break_state)
  170. ulcon |= SIRFUART_SET_BREAK;
  171. else
  172. ulcon &= ~SIRFUART_SET_BREAK;
  173. wr_regl(port, SIRFUART_LINE_CTRL, ulcon);
  174. }
  175. static unsigned int
  176. sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count)
  177. {
  178. unsigned int ch, rx_count = 0;
  179. struct tty_struct *tty;
  180. tty = tty_port_tty_get(&port->state->port);
  181. if (!tty)
  182. return -ENODEV;
  183. while (!(rd_regl(port, SIRFUART_RX_FIFO_STATUS) &
  184. SIRFUART_FIFOEMPTY_MASK(port))) {
  185. ch = rd_regl(port, SIRFUART_RX_FIFO_DATA) | SIRFUART_DUMMY_READ;
  186. if (unlikely(uart_handle_sysrq_char(port, ch)))
  187. continue;
  188. uart_insert_char(port, 0, 0, ch, TTY_NORMAL);
  189. rx_count++;
  190. if (rx_count >= max_rx_count)
  191. break;
  192. }
  193. port->icount.rx += rx_count;
  194. tty_flip_buffer_push(tty);
  195. tty_kref_put(tty);
  196. return rx_count;
  197. }
  198. static unsigned int
  199. sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count)
  200. {
  201. struct uart_port *port = &sirfport->port;
  202. struct circ_buf *xmit = &port->state->xmit;
  203. unsigned int num_tx = 0;
  204. while (!uart_circ_empty(xmit) &&
  205. !(rd_regl(port, SIRFUART_TX_FIFO_STATUS) &
  206. SIRFUART_FIFOFULL_MASK(port)) &&
  207. count--) {
  208. wr_regl(port, SIRFUART_TX_FIFO_DATA, xmit->buf[xmit->tail]);
  209. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  210. port->icount.tx++;
  211. num_tx++;
  212. }
  213. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  214. uart_write_wakeup(port);
  215. return num_tx;
  216. }
  217. static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id)
  218. {
  219. unsigned long intr_status;
  220. unsigned long cts_status;
  221. unsigned long flag = TTY_NORMAL;
  222. struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
  223. struct uart_port *port = &sirfport->port;
  224. struct uart_state *state = port->state;
  225. struct circ_buf *xmit = &port->state->xmit;
  226. intr_status = rd_regl(port, SIRFUART_INT_STATUS);
  227. wr_regl(port, SIRFUART_INT_STATUS, intr_status);
  228. intr_status &= rd_regl(port, SIRFUART_INT_EN);
  229. if (unlikely(intr_status & (SIRFUART_ERR_INT_STAT))) {
  230. if (intr_status & SIRFUART_RXD_BREAK) {
  231. if (uart_handle_break(port))
  232. goto recv_char;
  233. uart_insert_char(port, intr_status,
  234. SIRFUART_RX_OFLOW, 0, TTY_BREAK);
  235. return IRQ_HANDLED;
  236. }
  237. if (intr_status & SIRFUART_RX_OFLOW)
  238. port->icount.overrun++;
  239. if (intr_status & SIRFUART_FRM_ERR) {
  240. port->icount.frame++;
  241. flag = TTY_FRAME;
  242. }
  243. if (intr_status & SIRFUART_PARITY_ERR)
  244. flag = TTY_PARITY;
  245. wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_RESET);
  246. wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
  247. wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_START);
  248. intr_status &= port->read_status_mask;
  249. uart_insert_char(port, intr_status,
  250. SIRFUART_RX_OFLOW_INT, 0, flag);
  251. }
  252. recv_char:
  253. if (intr_status & SIRFUART_CTS_INT_EN) {
  254. cts_status = !(rd_regl(port, SIRFUART_AFC_CTRL) &
  255. SIRFUART_CTS_IN_STATUS);
  256. if (cts_status != 0) {
  257. uart_handle_cts_change(port, 1);
  258. } else {
  259. uart_handle_cts_change(port, 0);
  260. wake_up_interruptible(&state->port.delta_msr_wait);
  261. }
  262. }
  263. if (intr_status & SIRFUART_RX_IO_INT_EN)
  264. sirfsoc_uart_pio_rx_chars(port, SIRFSOC_UART_IO_RX_MAX_CNT);
  265. if (intr_status & SIRFUART_TX_INT_EN) {
  266. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  267. return IRQ_HANDLED;
  268. } else {
  269. sirfsoc_uart_pio_tx_chars(sirfport,
  270. SIRFSOC_UART_IO_TX_REASONABLE_CNT);
  271. if ((uart_circ_empty(xmit)) &&
  272. (rd_regl(port, SIRFUART_TX_FIFO_STATUS) &
  273. SIRFUART_FIFOEMPTY_MASK(port)))
  274. sirfsoc_uart_stop_tx(port);
  275. }
  276. }
  277. return IRQ_HANDLED;
  278. }
  279. static void sirfsoc_uart_start_rx(struct uart_port *port)
  280. {
  281. unsigned long regv;
  282. regv = rd_regl(port, SIRFUART_INT_EN);
  283. wr_regl(port, SIRFUART_INT_EN, regv | SIRFUART_RX_IO_INT_EN);
  284. wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_RESET);
  285. wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
  286. wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_START);
  287. }
  288. static unsigned int
  289. sirfsoc_calc_sample_div(unsigned long baud_rate,
  290. unsigned long ioclk_rate, unsigned long *setted_baud)
  291. {
  292. unsigned long min_delta = ~0UL;
  293. unsigned short sample_div;
  294. unsigned int regv = 0;
  295. unsigned long ioclk_div;
  296. unsigned long baud_tmp;
  297. int temp_delta;
  298. for (sample_div = SIRF_MIN_SAMPLE_DIV;
  299. sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
  300. ioclk_div = (ioclk_rate / (baud_rate * (sample_div + 1))) - 1;
  301. if (ioclk_div > SIRF_IOCLK_DIV_MAX)
  302. continue;
  303. baud_tmp = ioclk_rate / ((ioclk_div + 1) * (sample_div + 1));
  304. temp_delta = baud_tmp - baud_rate;
  305. temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
  306. if (temp_delta < min_delta) {
  307. regv = regv & (~SIRF_IOCLK_DIV_MASK);
  308. regv = regv | ioclk_div;
  309. regv = regv & (~SIRF_SAMPLE_DIV_MASK);
  310. regv = regv | (sample_div << SIRF_SAMPLE_DIV_SHIFT);
  311. min_delta = temp_delta;
  312. *setted_baud = baud_tmp;
  313. }
  314. }
  315. return regv;
  316. }
  317. static void sirfsoc_uart_set_termios(struct uart_port *port,
  318. struct ktermios *termios,
  319. struct ktermios *old)
  320. {
  321. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  322. unsigned long ioclk_rate;
  323. unsigned long config_reg = 0;
  324. unsigned long baud_rate;
  325. unsigned long setted_baud;
  326. unsigned long flags;
  327. unsigned long ic;
  328. unsigned int clk_div_reg = 0;
  329. unsigned long temp_reg_val;
  330. unsigned long rx_time_out;
  331. int threshold_div;
  332. int temp;
  333. ioclk_rate = 150000000;
  334. switch (termios->c_cflag & CSIZE) {
  335. default:
  336. case CS8:
  337. config_reg |= SIRFUART_DATA_BIT_LEN_8;
  338. break;
  339. case CS7:
  340. config_reg |= SIRFUART_DATA_BIT_LEN_7;
  341. break;
  342. case CS6:
  343. config_reg |= SIRFUART_DATA_BIT_LEN_6;
  344. break;
  345. case CS5:
  346. config_reg |= SIRFUART_DATA_BIT_LEN_5;
  347. break;
  348. }
  349. if (termios->c_cflag & CSTOPB)
  350. config_reg |= SIRFUART_STOP_BIT_LEN_2;
  351. baud_rate = uart_get_baud_rate(port, termios, old, 0, 4000000);
  352. spin_lock_irqsave(&port->lock, flags);
  353. port->read_status_mask = SIRFUART_RX_OFLOW_INT;
  354. port->ignore_status_mask = 0;
  355. /* read flags */
  356. if (termios->c_iflag & INPCK)
  357. port->read_status_mask |=
  358. SIRFUART_FRM_ERR_INT | SIRFUART_PARITY_ERR_INT;
  359. if (termios->c_iflag & (BRKINT | PARMRK))
  360. port->read_status_mask |= SIRFUART_RXD_BREAK_INT;
  361. /* ignore flags */
  362. if (termios->c_iflag & IGNPAR)
  363. port->ignore_status_mask |=
  364. SIRFUART_FRM_ERR_INT | SIRFUART_PARITY_ERR_INT;
  365. if ((termios->c_cflag & CREAD) == 0)
  366. port->ignore_status_mask |= SIRFUART_DUMMY_READ;
  367. /* enable parity if PARENB is set*/
  368. if (termios->c_cflag & PARENB) {
  369. if (termios->c_cflag & CMSPAR) {
  370. if (termios->c_cflag & PARODD)
  371. config_reg |= SIRFUART_STICK_BIT_MARK;
  372. else
  373. config_reg |= SIRFUART_STICK_BIT_SPACE;
  374. } else if (termios->c_cflag & PARODD) {
  375. config_reg |= SIRFUART_STICK_BIT_ODD;
  376. } else {
  377. config_reg |= SIRFUART_STICK_BIT_EVEN;
  378. }
  379. }
  380. /* Hardware Flow Control Settings */
  381. if (UART_ENABLE_MS(port, termios->c_cflag)) {
  382. if (!sirfport->ms_enabled)
  383. sirfsoc_uart_enable_ms(port);
  384. } else {
  385. if (sirfport->ms_enabled)
  386. sirfsoc_uart_disable_ms(port);
  387. }
  388. /* common rate: fast calculation */
  389. for (ic = 0; ic < SIRF_BAUD_RATE_SUPPORT_NR; ic++)
  390. if (baud_rate == baudrate_to_regv[ic].baud_rate)
  391. clk_div_reg = baudrate_to_regv[ic].reg_val;
  392. setted_baud = baud_rate;
  393. /* arbitary rate setting */
  394. if (unlikely(clk_div_reg == 0))
  395. clk_div_reg = sirfsoc_calc_sample_div(baud_rate, ioclk_rate,
  396. &setted_baud);
  397. wr_regl(port, SIRFUART_DIVISOR, clk_div_reg);
  398. if (tty_termios_baud_rate(termios))
  399. tty_termios_encode_baud_rate(termios, setted_baud, setted_baud);
  400. /* set receive timeout */
  401. rx_time_out = SIRFSOC_UART_RX_TIMEOUT(baud_rate, 20000);
  402. rx_time_out = (rx_time_out > 0xFFFF) ? 0xFFFF : rx_time_out;
  403. config_reg |= SIRFUART_RECV_TIMEOUT(rx_time_out);
  404. temp_reg_val = rd_regl(port, SIRFUART_TX_FIFO_OP);
  405. wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
  406. wr_regl(port, SIRFUART_TX_FIFO_OP,
  407. temp_reg_val & ~SIRFUART_TX_FIFO_START);
  408. wr_regl(port, SIRFUART_TX_DMA_IO_CTRL, SIRFUART_TX_MODE_IO);
  409. wr_regl(port, SIRFUART_RX_DMA_IO_CTRL, SIRFUART_RX_MODE_IO);
  410. wr_regl(port, SIRFUART_LINE_CTRL, config_reg);
  411. /* Reset Rx/Tx FIFO Threshold level for proper baudrate */
  412. if (baud_rate < 1000000)
  413. threshold_div = 1;
  414. else
  415. threshold_div = 2;
  416. temp = port->line == 1 ? 16 : 64;
  417. wr_regl(port, SIRFUART_TX_FIFO_CTRL, temp / threshold_div);
  418. wr_regl(port, SIRFUART_RX_FIFO_CTRL, temp / threshold_div);
  419. temp_reg_val |= SIRFUART_TX_FIFO_START;
  420. wr_regl(port, SIRFUART_TX_FIFO_OP, temp_reg_val);
  421. uart_update_timeout(port, termios->c_cflag, baud_rate);
  422. sirfsoc_uart_start_rx(port);
  423. wr_regl(port, SIRFUART_TX_RX_EN, SIRFUART_TX_EN | SIRFUART_RX_EN);
  424. spin_unlock_irqrestore(&port->lock, flags);
  425. }
  426. static void startup_uart_controller(struct uart_port *port)
  427. {
  428. unsigned long temp_regv;
  429. int temp;
  430. temp_regv = rd_regl(port, SIRFUART_TX_DMA_IO_CTRL);
  431. wr_regl(port, SIRFUART_TX_DMA_IO_CTRL, temp_regv | SIRFUART_TX_MODE_IO);
  432. temp_regv = rd_regl(port, SIRFUART_RX_DMA_IO_CTRL);
  433. wr_regl(port, SIRFUART_RX_DMA_IO_CTRL, temp_regv | SIRFUART_RX_MODE_IO);
  434. wr_regl(port, SIRFUART_TX_DMA_IO_LEN, 0);
  435. wr_regl(port, SIRFUART_RX_DMA_IO_LEN, 0);
  436. wr_regl(port, SIRFUART_TX_RX_EN, SIRFUART_RX_EN | SIRFUART_TX_EN);
  437. wr_regl(port, SIRFUART_TX_FIFO_OP, SIRFUART_TX_FIFO_RESET);
  438. wr_regl(port, SIRFUART_TX_FIFO_OP, 0);
  439. wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_RESET);
  440. wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
  441. temp = port->line == 1 ? 16 : 64;
  442. wr_regl(port, SIRFUART_TX_FIFO_CTRL, temp);
  443. wr_regl(port, SIRFUART_RX_FIFO_CTRL, temp);
  444. }
  445. static int sirfsoc_uart_startup(struct uart_port *port)
  446. {
  447. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  448. unsigned int index = port->line;
  449. int ret;
  450. set_irq_flags(port->irq, IRQF_VALID | IRQF_NOAUTOEN);
  451. ret = request_irq(port->irq,
  452. sirfsoc_uart_isr,
  453. 0,
  454. SIRFUART_PORT_NAME,
  455. sirfport);
  456. if (ret != 0) {
  457. dev_err(port->dev, "UART%d request IRQ line (%d) failed.\n",
  458. index, port->irq);
  459. goto irq_err;
  460. }
  461. startup_uart_controller(port);
  462. enable_irq(port->irq);
  463. irq_err:
  464. return ret;
  465. }
  466. static void sirfsoc_uart_shutdown(struct uart_port *port)
  467. {
  468. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  469. wr_regl(port, SIRFUART_INT_EN, 0);
  470. free_irq(port->irq, sirfport);
  471. if (sirfport->ms_enabled) {
  472. sirfsoc_uart_disable_ms(port);
  473. sirfport->ms_enabled = 0;
  474. }
  475. }
  476. static const char *sirfsoc_uart_type(struct uart_port *port)
  477. {
  478. return port->type == SIRFSOC_PORT_TYPE ? SIRFUART_PORT_NAME : NULL;
  479. }
  480. static int sirfsoc_uart_request_port(struct uart_port *port)
  481. {
  482. void *ret;
  483. ret = request_mem_region(port->mapbase,
  484. SIRFUART_MAP_SIZE, SIRFUART_PORT_NAME);
  485. return ret ? 0 : -EBUSY;
  486. }
  487. static void sirfsoc_uart_release_port(struct uart_port *port)
  488. {
  489. release_mem_region(port->mapbase, SIRFUART_MAP_SIZE);
  490. }
  491. static void sirfsoc_uart_config_port(struct uart_port *port, int flags)
  492. {
  493. if (flags & UART_CONFIG_TYPE) {
  494. port->type = SIRFSOC_PORT_TYPE;
  495. sirfsoc_uart_request_port(port);
  496. }
  497. }
  498. static struct uart_ops sirfsoc_uart_ops = {
  499. .tx_empty = sirfsoc_uart_tx_empty,
  500. .get_mctrl = sirfsoc_uart_get_mctrl,
  501. .set_mctrl = sirfsoc_uart_set_mctrl,
  502. .stop_tx = sirfsoc_uart_stop_tx,
  503. .start_tx = sirfsoc_uart_start_tx,
  504. .stop_rx = sirfsoc_uart_stop_rx,
  505. .enable_ms = sirfsoc_uart_enable_ms,
  506. .break_ctl = sirfsoc_uart_break_ctl,
  507. .startup = sirfsoc_uart_startup,
  508. .shutdown = sirfsoc_uart_shutdown,
  509. .set_termios = sirfsoc_uart_set_termios,
  510. .type = sirfsoc_uart_type,
  511. .release_port = sirfsoc_uart_release_port,
  512. .request_port = sirfsoc_uart_request_port,
  513. .config_port = sirfsoc_uart_config_port,
  514. };
  515. #ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
  516. static int __init sirfsoc_uart_console_setup(struct console *co, char *options)
  517. {
  518. unsigned int baud = 115200;
  519. unsigned int bits = 8;
  520. unsigned int parity = 'n';
  521. unsigned int flow = 'n';
  522. struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
  523. if (co->index < 0 || co->index >= SIRFSOC_UART_NR)
  524. return -EINVAL;
  525. if (!port->mapbase)
  526. return -ENODEV;
  527. if (options)
  528. uart_parse_options(options, &baud, &parity, &bits, &flow);
  529. port->cons = co;
  530. return uart_set_options(port, co, baud, parity, bits, flow);
  531. }
  532. static void sirfsoc_uart_console_putchar(struct uart_port *port, int ch)
  533. {
  534. while (rd_regl(port,
  535. SIRFUART_TX_FIFO_STATUS) & SIRFUART_FIFOFULL_MASK(port))
  536. cpu_relax();
  537. wr_regb(port, SIRFUART_TX_FIFO_DATA, ch);
  538. }
  539. static void sirfsoc_uart_console_write(struct console *co, const char *s,
  540. unsigned int count)
  541. {
  542. struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
  543. uart_console_write(port, s, count, sirfsoc_uart_console_putchar);
  544. }
  545. static struct console sirfsoc_uart_console = {
  546. .name = SIRFSOC_UART_NAME,
  547. .device = uart_console_device,
  548. .flags = CON_PRINTBUFFER,
  549. .index = -1,
  550. .write = sirfsoc_uart_console_write,
  551. .setup = sirfsoc_uart_console_setup,
  552. .data = &sirfsoc_uart_drv,
  553. };
  554. static int __init sirfsoc_uart_console_init(void)
  555. {
  556. register_console(&sirfsoc_uart_console);
  557. return 0;
  558. }
  559. console_initcall(sirfsoc_uart_console_init);
  560. #endif
  561. static struct uart_driver sirfsoc_uart_drv = {
  562. .owner = THIS_MODULE,
  563. .driver_name = SIRFUART_PORT_NAME,
  564. .nr = SIRFSOC_UART_NR,
  565. .dev_name = SIRFSOC_UART_NAME,
  566. .major = SIRFSOC_UART_MAJOR,
  567. .minor = SIRFSOC_UART_MINOR,
  568. #ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
  569. .cons = &sirfsoc_uart_console,
  570. #else
  571. .cons = NULL,
  572. #endif
  573. };
  574. int sirfsoc_uart_probe(struct platform_device *pdev)
  575. {
  576. struct sirfsoc_uart_port *sirfport;
  577. struct uart_port *port;
  578. struct resource *res;
  579. int ret;
  580. if (of_property_read_u32(pdev->dev.of_node, "cell-index", &pdev->id)) {
  581. dev_err(&pdev->dev,
  582. "Unable to find cell-index in uart node.\n");
  583. ret = -EFAULT;
  584. goto err;
  585. }
  586. sirfport = &sirfsoc_uart_ports[pdev->id];
  587. port = &sirfport->port;
  588. port->dev = &pdev->dev;
  589. port->private_data = sirfport;
  590. if (of_find_property(pdev->dev.of_node, "hw_flow_ctrl", NULL))
  591. sirfport->hw_flow_ctrl = 1;
  592. if (of_property_read_u32(pdev->dev.of_node,
  593. "fifosize",
  594. &port->fifosize)) {
  595. dev_err(&pdev->dev,
  596. "Unable to find fifosize in uart node.\n");
  597. ret = -EFAULT;
  598. goto err;
  599. }
  600. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  601. if (res == NULL) {
  602. dev_err(&pdev->dev, "Insufficient resources.\n");
  603. ret = -EFAULT;
  604. goto err;
  605. }
  606. port->mapbase = res->start;
  607. port->membase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
  608. if (!port->membase) {
  609. dev_err(&pdev->dev, "Cannot remap resource.\n");
  610. ret = -ENOMEM;
  611. goto err;
  612. }
  613. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  614. if (res == NULL) {
  615. dev_err(&pdev->dev, "Insufficient resources.\n");
  616. ret = -EFAULT;
  617. goto irq_err;
  618. }
  619. port->irq = res->start;
  620. if (sirfport->hw_flow_ctrl) {
  621. sirfport->p = pinctrl_get_select_default(&pdev->dev);
  622. ret = IS_ERR(sirfport->p);
  623. if (ret)
  624. goto pin_err;
  625. }
  626. port->ops = &sirfsoc_uart_ops;
  627. spin_lock_init(&port->lock);
  628. platform_set_drvdata(pdev, sirfport);
  629. ret = uart_add_one_port(&sirfsoc_uart_drv, port);
  630. if (ret != 0) {
  631. dev_err(&pdev->dev, "Cannot add UART port(%d).\n", pdev->id);
  632. goto port_err;
  633. }
  634. return 0;
  635. port_err:
  636. platform_set_drvdata(pdev, NULL);
  637. if (sirfport->hw_flow_ctrl)
  638. pinctrl_put(sirfport->p);
  639. pin_err:
  640. irq_err:
  641. devm_iounmap(&pdev->dev, port->membase);
  642. err:
  643. return ret;
  644. }
  645. static int sirfsoc_uart_remove(struct platform_device *pdev)
  646. {
  647. struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
  648. struct uart_port *port = &sirfport->port;
  649. platform_set_drvdata(pdev, NULL);
  650. if (sirfport->hw_flow_ctrl)
  651. pinctrl_put(sirfport->p);
  652. devm_iounmap(&pdev->dev, port->membase);
  653. uart_remove_one_port(&sirfsoc_uart_drv, port);
  654. return 0;
  655. }
  656. static int
  657. sirfsoc_uart_suspend(struct platform_device *pdev, pm_message_t state)
  658. {
  659. struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
  660. struct uart_port *port = &sirfport->port;
  661. uart_suspend_port(&sirfsoc_uart_drv, port);
  662. return 0;
  663. }
  664. static int sirfsoc_uart_resume(struct platform_device *pdev)
  665. {
  666. struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
  667. struct uart_port *port = &sirfport->port;
  668. uart_resume_port(&sirfsoc_uart_drv, port);
  669. return 0;
  670. }
  671. static struct of_device_id sirfsoc_uart_ids[] __devinitdata = {
  672. { .compatible = "sirf,prima2-uart", },
  673. {}
  674. };
  675. MODULE_DEVICE_TABLE(of, sirfsoc_serial_of_match);
  676. static struct platform_driver sirfsoc_uart_driver = {
  677. .probe = sirfsoc_uart_probe,
  678. .remove = __devexit_p(sirfsoc_uart_remove),
  679. .suspend = sirfsoc_uart_suspend,
  680. .resume = sirfsoc_uart_resume,
  681. .driver = {
  682. .name = SIRFUART_PORT_NAME,
  683. .owner = THIS_MODULE,
  684. .of_match_table = sirfsoc_uart_ids,
  685. },
  686. };
  687. static int __init sirfsoc_uart_init(void)
  688. {
  689. int ret = 0;
  690. ret = uart_register_driver(&sirfsoc_uart_drv);
  691. if (ret)
  692. goto out;
  693. ret = platform_driver_register(&sirfsoc_uart_driver);
  694. if (ret)
  695. uart_unregister_driver(&sirfsoc_uart_drv);
  696. out:
  697. return ret;
  698. }
  699. module_init(sirfsoc_uart_init);
  700. static void __exit sirfsoc_uart_exit(void)
  701. {
  702. platform_driver_unregister(&sirfsoc_uart_driver);
  703. uart_unregister_driver(&sirfsoc_uart_drv);
  704. }
  705. module_exit(sirfsoc_uart_exit);
  706. MODULE_LICENSE("GPL v2");
  707. MODULE_AUTHOR("Bin Shi <Bin.Shi@csr.com>, Rong Wang<Rong.Wang@csr.com>");
  708. MODULE_DESCRIPTION("CSR SiRFprimaII Uart Driver");