p2020ds.dtsi 6.9 KB

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  1. /*
  2. * P2020DS Device Tree Source stub (no addresses or top-level ranges)
  3. *
  4. * Copyright 2011-2012 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &board_lbc {
  35. nor@0,0 {
  36. #address-cells = <1>;
  37. #size-cells = <1>;
  38. compatible = "cfi-flash";
  39. reg = <0x0 0x0 0x8000000>;
  40. bank-width = <2>;
  41. device-width = <1>;
  42. ramdisk@0 {
  43. reg = <0x0 0x03000000>;
  44. read-only;
  45. };
  46. diagnostic@3000000 {
  47. reg = <0x03000000 0x00e00000>;
  48. read-only;
  49. };
  50. dink@3e00000 {
  51. reg = <0x03e00000 0x00200000>;
  52. read-only;
  53. };
  54. kernel@4000000 {
  55. reg = <0x04000000 0x00400000>;
  56. read-only;
  57. };
  58. jffs2@4400000 {
  59. reg = <0x04400000 0x03b00000>;
  60. };
  61. dtb@7f00000 {
  62. reg = <0x07f00000 0x00080000>;
  63. read-only;
  64. };
  65. u-boot@7f80000 {
  66. reg = <0x07f80000 0x00080000>;
  67. read-only;
  68. };
  69. };
  70. nand@2,0 {
  71. #address-cells = <1>;
  72. #size-cells = <1>;
  73. compatible = "fsl,elbc-fcm-nand";
  74. reg = <0x2 0x0 0x40000>;
  75. u-boot@0 {
  76. reg = <0x0 0x02000000>;
  77. read-only;
  78. };
  79. jffs2@2000000 {
  80. reg = <0x02000000 0x10000000>;
  81. };
  82. ramdisk@12000000 {
  83. reg = <0x12000000 0x08000000>;
  84. read-only;
  85. };
  86. kernel@1a000000 {
  87. reg = <0x1a000000 0x04000000>;
  88. };
  89. dtb@1e000000 {
  90. reg = <0x1e000000 0x01000000>;
  91. read-only;
  92. };
  93. empty@1f000000 {
  94. reg = <0x1f000000 0x21000000>;
  95. };
  96. };
  97. board-control@3,0 {
  98. compatible = "fsl,p2020ds-fpga", "fsl,fpga-ngpixis";
  99. reg = <0x3 0x0 0x30>;
  100. };
  101. nand@4,0 {
  102. compatible = "fsl,elbc-fcm-nand";
  103. reg = <0x4 0x0 0x40000>;
  104. };
  105. nand@5,0 {
  106. compatible = "fsl,elbc-fcm-nand";
  107. reg = <0x5 0x0 0x40000>;
  108. };
  109. nand@6,0 {
  110. compatible = "fsl,elbc-fcm-nand";
  111. reg = <0x6 0x0 0x40000>;
  112. };
  113. };
  114. &board_soc {
  115. usb@22000 {
  116. phy_type = "ulpi";
  117. dr_mode = "host";
  118. };
  119. mdio@24520 {
  120. phy0: ethernet-phy@0 {
  121. interrupts = <3 1 0 0>;
  122. reg = <0x0>;
  123. };
  124. phy1: ethernet-phy@1 {
  125. interrupts = <3 1 0 0>;
  126. reg = <0x1>;
  127. };
  128. phy2: ethernet-phy@2 {
  129. interrupts = <3 1 0 0>;
  130. reg = <0x2>;
  131. };
  132. tbi0: tbi-phy@11 {
  133. reg = <0x11>;
  134. device_type = "tbi-phy";
  135. };
  136. };
  137. mdio@25520 {
  138. tbi1: tbi-phy@11 {
  139. reg = <0x11>;
  140. device_type = "tbi-phy";
  141. };
  142. };
  143. mdio@26520 {
  144. tbi2: tbi-phy@11 {
  145. reg = <0x11>;
  146. device_type = "tbi-phy";
  147. };
  148. };
  149. ptp_clock@24e00 {
  150. fsl,tclk-period = <5>;
  151. fsl,tmr-prsc = <200>;
  152. fsl,tmr-add = <0xCCCCCCCD>;
  153. fsl,tmr-fiper1 = <0x3B9AC9FB>;
  154. fsl,tmr-fiper2 = <0x0001869B>;
  155. fsl,max-adj = <249999999>;
  156. };
  157. enet0: ethernet@24000 {
  158. tbi-handle = <&tbi0>;
  159. phy-handle = <&phy0>;
  160. phy-connection-type = "rgmii-id";
  161. };
  162. enet1: ethernet@25000 {
  163. tbi-handle = <&tbi1>;
  164. phy-handle = <&phy1>;
  165. phy-connection-type = "rgmii-id";
  166. };
  167. enet2: ethernet@26000 {
  168. tbi-handle = <&tbi2>;
  169. phy-handle = <&phy2>;
  170. phy-connection-type = "rgmii-id";
  171. };
  172. };
  173. &board_pci1 {
  174. pcie@0 {
  175. interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
  176. interrupt-map = <
  177. // IDSEL 0x11 func 0 - PCI slot 1
  178. 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
  179. 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
  180. // IDSEL 0x11 func 1 - PCI slot 1
  181. 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
  182. 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
  183. // IDSEL 0x11 func 2 - PCI slot 1
  184. 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
  185. 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
  186. // IDSEL 0x11 func 3 - PCI slot 1
  187. 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
  188. 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
  189. // IDSEL 0x11 func 4 - PCI slot 1
  190. 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
  191. 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
  192. // IDSEL 0x11 func 5 - PCI slot 1
  193. 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
  194. 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
  195. // IDSEL 0x11 func 6 - PCI slot 1
  196. 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
  197. 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
  198. // IDSEL 0x11 func 7 - PCI slot 1
  199. 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
  200. 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
  201. // IDSEL 0x1d Audio
  202. 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
  203. // IDSEL 0x1e Legacy
  204. 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
  205. 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
  206. // IDSEL 0x1f IDE/SATA
  207. 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
  208. 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
  209. >;
  210. uli1575@0 {
  211. reg = <0x0 0x0 0x0 0x0 0x0>;
  212. #size-cells = <2>;
  213. #address-cells = <3>;
  214. ranges = <0x2000000 0x0 0xa0000000
  215. 0x2000000 0x0 0xa0000000
  216. 0x0 0x20000000
  217. 0x1000000 0x0 0x0
  218. 0x1000000 0x0 0x0
  219. 0x0 0x10000>;
  220. isa@1e {
  221. device_type = "isa";
  222. #interrupt-cells = <2>;
  223. #size-cells = <1>;
  224. #address-cells = <2>;
  225. reg = <0xf000 0x0 0x0 0x0 0x0>;
  226. ranges = <0x1 0x0 0x1000000 0x0 0x0
  227. 0x1000>;
  228. interrupt-parent = <&i8259>;
  229. i8259: interrupt-controller@20 {
  230. reg = <0x1 0x20 0x2
  231. 0x1 0xa0 0x2
  232. 0x1 0x4d0 0x2>;
  233. interrupt-controller;
  234. device_type = "interrupt-controller";
  235. #address-cells = <0>;
  236. #interrupt-cells = <2>;
  237. compatible = "chrp,iic";
  238. interrupts = <4 1 0 0>;
  239. interrupt-parent = <&mpic>;
  240. };
  241. i8042@60 {
  242. #size-cells = <0>;
  243. #address-cells = <1>;
  244. reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
  245. interrupts = <1 3 12 3>;
  246. interrupt-parent =
  247. <&i8259>;
  248. keyboard@0 {
  249. reg = <0x0>;
  250. compatible = "pnpPNP,303";
  251. };
  252. mouse@1 {
  253. reg = <0x1>;
  254. compatible = "pnpPNP,f03";
  255. };
  256. };
  257. rtc@70 {
  258. compatible = "pnpPNP,b00";
  259. reg = <0x1 0x70 0x2>;
  260. };
  261. gpio@400 {
  262. reg = <0x1 0x400 0x80>;
  263. };
  264. };
  265. };
  266. };
  267. };