sysmmu.c 7.3 KB

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  1. /* linux/arch/arm/plat-s5p/sysmmu.c
  2. *
  3. * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/io.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/export.h>
  14. #include <asm/pgtable.h>
  15. #include <mach/map.h>
  16. #include <mach/regs-sysmmu.h>
  17. #include <plat/sysmmu.h>
  18. #define CTRL_ENABLE 0x5
  19. #define CTRL_BLOCK 0x7
  20. #define CTRL_DISABLE 0x0
  21. static struct device *dev;
  22. static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
  23. S5P_PAGE_FAULT_ADDR,
  24. S5P_AR_FAULT_ADDR,
  25. S5P_AW_FAULT_ADDR,
  26. S5P_DEFAULT_SLAVE_ADDR,
  27. S5P_AR_FAULT_ADDR,
  28. S5P_AR_FAULT_ADDR,
  29. S5P_AW_FAULT_ADDR,
  30. S5P_AW_FAULT_ADDR
  31. };
  32. static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
  33. "PAGE FAULT",
  34. "AR MULTI-HIT FAULT",
  35. "AW MULTI-HIT FAULT",
  36. "BUS ERROR",
  37. "AR SECURITY PROTECTION FAULT",
  38. "AR ACCESS PROTECTION FAULT",
  39. "AW SECURITY PROTECTION FAULT",
  40. "AW ACCESS PROTECTION FAULT"
  41. };
  42. static int (*fault_handlers[S5P_SYSMMU_TOTAL_IPNUM])(
  43. enum S5P_SYSMMU_INTERRUPT_TYPE itype,
  44. unsigned long pgtable_base,
  45. unsigned long fault_addr);
  46. /*
  47. * If adjacent 2 bits are true, the system MMU is enabled.
  48. * The system MMU is disabled, otherwise.
  49. */
  50. static unsigned long sysmmu_states;
  51. static inline void set_sysmmu_active(sysmmu_ips ips)
  52. {
  53. sysmmu_states |= 3 << (ips * 2);
  54. }
  55. static inline void set_sysmmu_inactive(sysmmu_ips ips)
  56. {
  57. sysmmu_states &= ~(3 << (ips * 2));
  58. }
  59. static inline int is_sysmmu_active(sysmmu_ips ips)
  60. {
  61. return sysmmu_states & (3 << (ips * 2));
  62. }
  63. static void __iomem *sysmmusfrs[S5P_SYSMMU_TOTAL_IPNUM];
  64. static inline void sysmmu_block(sysmmu_ips ips)
  65. {
  66. __raw_writel(CTRL_BLOCK, sysmmusfrs[ips] + S5P_MMU_CTRL);
  67. dev_dbg(dev, "%s is blocked.\n", sysmmu_ips_name[ips]);
  68. }
  69. static inline void sysmmu_unblock(sysmmu_ips ips)
  70. {
  71. __raw_writel(CTRL_ENABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
  72. dev_dbg(dev, "%s is unblocked.\n", sysmmu_ips_name[ips]);
  73. }
  74. static inline void __sysmmu_tlb_invalidate(sysmmu_ips ips)
  75. {
  76. __raw_writel(0x1, sysmmusfrs[ips] + S5P_MMU_FLUSH);
  77. dev_dbg(dev, "TLB of %s is invalidated.\n", sysmmu_ips_name[ips]);
  78. }
  79. static inline void __sysmmu_set_ptbase(sysmmu_ips ips, unsigned long pgd)
  80. {
  81. if (unlikely(pgd == 0)) {
  82. pgd = (unsigned long)ZERO_PAGE(0);
  83. __raw_writel(0x20, sysmmusfrs[ips] + S5P_MMU_CFG); /* 4KB LV1 */
  84. } else {
  85. __raw_writel(0x0, sysmmusfrs[ips] + S5P_MMU_CFG); /* 16KB LV1 */
  86. }
  87. __raw_writel(pgd, sysmmusfrs[ips] + S5P_PT_BASE_ADDR);
  88. dev_dbg(dev, "Page table base of %s is initialized with 0x%08lX.\n",
  89. sysmmu_ips_name[ips], pgd);
  90. __sysmmu_tlb_invalidate(ips);
  91. }
  92. void sysmmu_set_fault_handler(sysmmu_ips ips,
  93. int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
  94. unsigned long pgtable_base,
  95. unsigned long fault_addr))
  96. {
  97. BUG_ON(!((ips >= SYSMMU_MDMA) && (ips < S5P_SYSMMU_TOTAL_IPNUM)));
  98. fault_handlers[ips] = handler;
  99. }
  100. static irqreturn_t s5p_sysmmu_irq(int irq, void *dev_id)
  101. {
  102. /* SYSMMU is in blocked when interrupt occurred. */
  103. unsigned long base = 0;
  104. sysmmu_ips ips = (sysmmu_ips)dev_id;
  105. enum S5P_SYSMMU_INTERRUPT_TYPE itype;
  106. itype = (enum S5P_SYSMMU_INTERRUPT_TYPE)
  107. __ffs(__raw_readl(sysmmusfrs[ips] + S5P_INT_STATUS));
  108. BUG_ON(!((itype >= 0) && (itype < 8)));
  109. dev_alert(dev, "%s occurred by %s.\n", sysmmu_fault_name[itype],
  110. sysmmu_ips_name[ips]);
  111. if (fault_handlers[ips]) {
  112. unsigned long addr;
  113. base = __raw_readl(sysmmusfrs[ips] + S5P_PT_BASE_ADDR);
  114. addr = __raw_readl(sysmmusfrs[ips] + fault_reg_offset[itype]);
  115. if (fault_handlers[ips](itype, base, addr)) {
  116. __raw_writel(1 << itype,
  117. sysmmusfrs[ips] + S5P_INT_CLEAR);
  118. dev_notice(dev, "%s from %s is resolved."
  119. " Retrying translation.\n",
  120. sysmmu_fault_name[itype], sysmmu_ips_name[ips]);
  121. } else {
  122. base = 0;
  123. }
  124. }
  125. sysmmu_unblock(ips);
  126. if (!base)
  127. dev_notice(dev, "%s from %s is not handled.\n",
  128. sysmmu_fault_name[itype], sysmmu_ips_name[ips]);
  129. return IRQ_HANDLED;
  130. }
  131. void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd)
  132. {
  133. if (is_sysmmu_active(ips)) {
  134. sysmmu_block(ips);
  135. __sysmmu_set_ptbase(ips, pgd);
  136. sysmmu_unblock(ips);
  137. } else {
  138. dev_dbg(dev, "%s is disabled. "
  139. "Skipping initializing page table base.\n",
  140. sysmmu_ips_name[ips]);
  141. }
  142. }
  143. void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd)
  144. {
  145. if (!is_sysmmu_active(ips)) {
  146. sysmmu_clk_enable(ips);
  147. __sysmmu_set_ptbase(ips, pgd);
  148. __raw_writel(CTRL_ENABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
  149. set_sysmmu_active(ips);
  150. dev_dbg(dev, "%s is enabled.\n", sysmmu_ips_name[ips]);
  151. } else {
  152. dev_dbg(dev, "%s is already enabled.\n", sysmmu_ips_name[ips]);
  153. }
  154. }
  155. void s5p_sysmmu_disable(sysmmu_ips ips)
  156. {
  157. if (is_sysmmu_active(ips)) {
  158. __raw_writel(CTRL_DISABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
  159. set_sysmmu_inactive(ips);
  160. sysmmu_clk_disable(ips);
  161. dev_dbg(dev, "%s is disabled.\n", sysmmu_ips_name[ips]);
  162. } else {
  163. dev_dbg(dev, "%s is already disabled.\n", sysmmu_ips_name[ips]);
  164. }
  165. }
  166. void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips)
  167. {
  168. if (is_sysmmu_active(ips)) {
  169. sysmmu_block(ips);
  170. __sysmmu_tlb_invalidate(ips);
  171. sysmmu_unblock(ips);
  172. } else {
  173. dev_dbg(dev, "%s is disabled. "
  174. "Skipping invalidating TLB.\n", sysmmu_ips_name[ips]);
  175. }
  176. }
  177. static int s5p_sysmmu_probe(struct platform_device *pdev)
  178. {
  179. int i, ret;
  180. struct resource *res, *mem;
  181. dev = &pdev->dev;
  182. for (i = 0; i < S5P_SYSMMU_TOTAL_IPNUM; i++) {
  183. int irq;
  184. sysmmu_clk_init(dev, i);
  185. sysmmu_clk_disable(i);
  186. res = platform_get_resource(pdev, IORESOURCE_MEM, i);
  187. if (!res) {
  188. dev_err(dev, "Failed to get the resource of %s.\n",
  189. sysmmu_ips_name[i]);
  190. ret = -ENODEV;
  191. goto err_res;
  192. }
  193. mem = request_mem_region(res->start, resource_size(res),
  194. pdev->name);
  195. if (!mem) {
  196. dev_err(dev, "Failed to request the memory region of %s.\n",
  197. sysmmu_ips_name[i]);
  198. ret = -EBUSY;
  199. goto err_res;
  200. }
  201. sysmmusfrs[i] = ioremap(res->start, resource_size(res));
  202. if (!sysmmusfrs[i]) {
  203. dev_err(dev, "Failed to ioremap() for %s.\n",
  204. sysmmu_ips_name[i]);
  205. ret = -ENXIO;
  206. goto err_reg;
  207. }
  208. irq = platform_get_irq(pdev, i);
  209. if (irq <= 0) {
  210. dev_err(dev, "Failed to get the IRQ resource of %s.\n",
  211. sysmmu_ips_name[i]);
  212. ret = -ENOENT;
  213. goto err_map;
  214. }
  215. if (request_irq(irq, s5p_sysmmu_irq, IRQF_DISABLED,
  216. pdev->name, (void *)i)) {
  217. dev_err(dev, "Failed to request IRQ for %s.\n",
  218. sysmmu_ips_name[i]);
  219. ret = -ENOENT;
  220. goto err_map;
  221. }
  222. }
  223. return 0;
  224. err_map:
  225. iounmap(sysmmusfrs[i]);
  226. err_reg:
  227. release_mem_region(mem->start, resource_size(mem));
  228. err_res:
  229. return ret;
  230. }
  231. static int s5p_sysmmu_remove(struct platform_device *pdev)
  232. {
  233. return 0;
  234. }
  235. int s5p_sysmmu_runtime_suspend(struct device *dev)
  236. {
  237. return 0;
  238. }
  239. int s5p_sysmmu_runtime_resume(struct device *dev)
  240. {
  241. return 0;
  242. }
  243. const struct dev_pm_ops s5p_sysmmu_pm_ops = {
  244. .runtime_suspend = s5p_sysmmu_runtime_suspend,
  245. .runtime_resume = s5p_sysmmu_runtime_resume,
  246. };
  247. static struct platform_driver s5p_sysmmu_driver = {
  248. .probe = s5p_sysmmu_probe,
  249. .remove = s5p_sysmmu_remove,
  250. .driver = {
  251. .owner = THIS_MODULE,
  252. .name = "s5p-sysmmu",
  253. .pm = &s5p_sysmmu_pm_ops,
  254. }
  255. };
  256. static int __init s5p_sysmmu_init(void)
  257. {
  258. return platform_driver_register(&s5p_sysmmu_driver);
  259. }
  260. arch_initcall(s5p_sysmmu_init);