cpu.c 6.0 KB

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  1. /* linux/arch/arm/plat-s3c24xx/cpu.c
  2. *
  3. * Copyright (c) 2004-2005 Simtec Electronics
  4. * http://www.simtec.co.uk/products/SWLINUX/
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * S3C24XX CPU Support
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. */
  23. #include <linux/init.h>
  24. #include <linux/module.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/ioport.h>
  27. #include <linux/serial_core.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/delay.h>
  30. #include <linux/io.h>
  31. #include <mach/hardware.h>
  32. #include <mach/regs-clock.h>
  33. #include <asm/irq.h>
  34. #include <asm/cacheflush.h>
  35. #include <asm/system_info.h>
  36. #include <asm/system_misc.h>
  37. #include <asm/mach/arch.h>
  38. #include <asm/mach/map.h>
  39. #include <mach/regs-gpio.h>
  40. #include <plat/regs-serial.h>
  41. #include <plat/cpu.h>
  42. #include <plat/devs.h>
  43. #include <plat/clock.h>
  44. #include <plat/s3c2410.h>
  45. #include <plat/s3c2412.h>
  46. #include <plat/s3c2416.h>
  47. #include <plat/s3c244x.h>
  48. #include <plat/s3c2443.h>
  49. /* table of supported CPUs */
  50. static const char name_s3c2410[] = "S3C2410";
  51. static const char name_s3c2412[] = "S3C2412";
  52. static const char name_s3c2416[] = "S3C2416/S3C2450";
  53. static const char name_s3c2440[] = "S3C2440";
  54. static const char name_s3c2442[] = "S3C2442";
  55. static const char name_s3c2442b[] = "S3C2442B";
  56. static const char name_s3c2443[] = "S3C2443";
  57. static const char name_s3c2410a[] = "S3C2410A";
  58. static const char name_s3c2440a[] = "S3C2440A";
  59. static struct cpu_table cpu_ids[] __initdata = {
  60. {
  61. .idcode = 0x32410000,
  62. .idmask = 0xffffffff,
  63. .map_io = s3c2410_map_io,
  64. .init_clocks = s3c2410_init_clocks,
  65. .init_uarts = s3c2410_init_uarts,
  66. .init = s3c2410_init,
  67. .name = name_s3c2410
  68. },
  69. {
  70. .idcode = 0x32410002,
  71. .idmask = 0xffffffff,
  72. .map_io = s3c2410_map_io,
  73. .init_clocks = s3c2410_init_clocks,
  74. .init_uarts = s3c2410_init_uarts,
  75. .init = s3c2410a_init,
  76. .name = name_s3c2410a
  77. },
  78. {
  79. .idcode = 0x32440000,
  80. .idmask = 0xffffffff,
  81. .map_io = s3c2440_map_io,
  82. .init_clocks = s3c244x_init_clocks,
  83. .init_uarts = s3c244x_init_uarts,
  84. .init = s3c2440_init,
  85. .name = name_s3c2440
  86. },
  87. {
  88. .idcode = 0x32440001,
  89. .idmask = 0xffffffff,
  90. .map_io = s3c2440_map_io,
  91. .init_clocks = s3c244x_init_clocks,
  92. .init_uarts = s3c244x_init_uarts,
  93. .init = s3c2440_init,
  94. .name = name_s3c2440a
  95. },
  96. {
  97. .idcode = 0x32440aaa,
  98. .idmask = 0xffffffff,
  99. .map_io = s3c2442_map_io,
  100. .init_clocks = s3c244x_init_clocks,
  101. .init_uarts = s3c244x_init_uarts,
  102. .init = s3c2442_init,
  103. .name = name_s3c2442
  104. },
  105. {
  106. .idcode = 0x32440aab,
  107. .idmask = 0xffffffff,
  108. .map_io = s3c2442_map_io,
  109. .init_clocks = s3c244x_init_clocks,
  110. .init_uarts = s3c244x_init_uarts,
  111. .init = s3c2442_init,
  112. .name = name_s3c2442b
  113. },
  114. {
  115. .idcode = 0x32412001,
  116. .idmask = 0xffffffff,
  117. .map_io = s3c2412_map_io,
  118. .init_clocks = s3c2412_init_clocks,
  119. .init_uarts = s3c2412_init_uarts,
  120. .init = s3c2412_init,
  121. .name = name_s3c2412,
  122. },
  123. { /* a newer version of the s3c2412 */
  124. .idcode = 0x32412003,
  125. .idmask = 0xffffffff,
  126. .map_io = s3c2412_map_io,
  127. .init_clocks = s3c2412_init_clocks,
  128. .init_uarts = s3c2412_init_uarts,
  129. .init = s3c2412_init,
  130. .name = name_s3c2412,
  131. },
  132. { /* a strange version of the s3c2416 */
  133. .idcode = 0x32450003,
  134. .idmask = 0xffffffff,
  135. .map_io = s3c2416_map_io,
  136. .init_clocks = s3c2416_init_clocks,
  137. .init_uarts = s3c2416_init_uarts,
  138. .init = s3c2416_init,
  139. .name = name_s3c2416,
  140. },
  141. {
  142. .idcode = 0x32443001,
  143. .idmask = 0xffffffff,
  144. .map_io = s3c2443_map_io,
  145. .init_clocks = s3c2443_init_clocks,
  146. .init_uarts = s3c2443_init_uarts,
  147. .init = s3c2443_init,
  148. .name = name_s3c2443,
  149. },
  150. };
  151. /* minimal IO mapping */
  152. static struct map_desc s3c_iodesc[] __initdata = {
  153. IODESC_ENT(GPIO),
  154. IODESC_ENT(IRQ),
  155. IODESC_ENT(MEMCTRL),
  156. IODESC_ENT(UART)
  157. };
  158. /* read cpu identificaiton code */
  159. static unsigned long s3c24xx_read_idcode_v5(void)
  160. {
  161. #if defined(CONFIG_CPU_S3C2416)
  162. /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
  163. u32 gs = __raw_readl(S3C24XX_GSTATUS1);
  164. /* test for s3c2416 or similar device */
  165. if ((gs >> 16) == 0x3245)
  166. return gs;
  167. #endif
  168. #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
  169. return __raw_readl(S3C2412_GSTATUS1);
  170. #else
  171. return 1UL; /* don't look like an 2400 */
  172. #endif
  173. }
  174. static unsigned long s3c24xx_read_idcode_v4(void)
  175. {
  176. return __raw_readl(S3C2410_GSTATUS1);
  177. }
  178. static void s3c24xx_default_idle(void)
  179. {
  180. unsigned long tmp;
  181. int i;
  182. /* idle the system by using the idle mode which will wait for an
  183. * interrupt to happen before restarting the system.
  184. */
  185. /* Warning: going into idle state upsets jtag scanning */
  186. __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
  187. S3C2410_CLKCON);
  188. /* the samsung port seems to do a loop and then unset idle.. */
  189. for (i = 0; i < 50; i++)
  190. tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
  191. /* this bit is not cleared on re-start... */
  192. __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
  193. S3C2410_CLKCON);
  194. }
  195. void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
  196. {
  197. arm_pm_idle = s3c24xx_default_idle;
  198. /* initialise the io descriptors we need for initialisation */
  199. iotable_init(mach_desc, size);
  200. iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
  201. if (cpu_architecture() >= CPU_ARCH_ARMv5) {
  202. samsung_cpu_id = s3c24xx_read_idcode_v5();
  203. } else {
  204. samsung_cpu_id = s3c24xx_read_idcode_v4();
  205. }
  206. s3c24xx_init_cpu();
  207. s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
  208. }