pcie.c 7.2 KB

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  1. /*
  2. * arch/arm/plat-orion/pcie.c
  3. *
  4. * Marvell Orion SoC PCIe handling.
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without any
  8. * warranty of any kind, whether express or implied.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/pci.h>
  12. #include <linux/mbus.h>
  13. #include <asm/mach/pci.h>
  14. #include <plat/pcie.h>
  15. #include <plat/addr-map.h>
  16. #include <linux/delay.h>
  17. /*
  18. * PCIe unit register offsets.
  19. */
  20. #define PCIE_DEV_ID_OFF 0x0000
  21. #define PCIE_CMD_OFF 0x0004
  22. #define PCIE_DEV_REV_OFF 0x0008
  23. #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
  24. #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
  25. #define PCIE_HEADER_LOG_4_OFF 0x0128
  26. #define PCIE_BAR_CTRL_OFF(n) (0x1804 + ((n - 1) * 4))
  27. #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
  28. #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
  29. #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
  30. #define PCIE_WIN5_CTRL_OFF 0x1880
  31. #define PCIE_WIN5_BASE_OFF 0x1884
  32. #define PCIE_WIN5_REMAP_OFF 0x188c
  33. #define PCIE_CONF_ADDR_OFF 0x18f8
  34. #define PCIE_CONF_ADDR_EN 0x80000000
  35. #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
  36. #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
  37. #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
  38. #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
  39. #define PCIE_CONF_DATA_OFF 0x18fc
  40. #define PCIE_MASK_OFF 0x1910
  41. #define PCIE_CTRL_OFF 0x1a00
  42. #define PCIE_CTRL_X1_MODE 0x0001
  43. #define PCIE_STAT_OFF 0x1a04
  44. #define PCIE_STAT_DEV_OFFS 20
  45. #define PCIE_STAT_DEV_MASK 0x1f
  46. #define PCIE_STAT_BUS_OFFS 8
  47. #define PCIE_STAT_BUS_MASK 0xff
  48. #define PCIE_STAT_LINK_DOWN 1
  49. #define PCIE_DEBUG_CTRL 0x1a60
  50. #define PCIE_DEBUG_SOFT_RESET (1<<20)
  51. u32 __init orion_pcie_dev_id(void __iomem *base)
  52. {
  53. return readl(base + PCIE_DEV_ID_OFF) >> 16;
  54. }
  55. u32 __init orion_pcie_rev(void __iomem *base)
  56. {
  57. return readl(base + PCIE_DEV_REV_OFF) & 0xff;
  58. }
  59. int orion_pcie_link_up(void __iomem *base)
  60. {
  61. return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
  62. }
  63. int __init orion_pcie_x4_mode(void __iomem *base)
  64. {
  65. return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE);
  66. }
  67. int orion_pcie_get_local_bus_nr(void __iomem *base)
  68. {
  69. u32 stat = readl(base + PCIE_STAT_OFF);
  70. return (stat >> PCIE_STAT_BUS_OFFS) & PCIE_STAT_BUS_MASK;
  71. }
  72. void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr)
  73. {
  74. u32 stat;
  75. stat = readl(base + PCIE_STAT_OFF);
  76. stat &= ~(PCIE_STAT_BUS_MASK << PCIE_STAT_BUS_OFFS);
  77. stat |= nr << PCIE_STAT_BUS_OFFS;
  78. writel(stat, base + PCIE_STAT_OFF);
  79. }
  80. void __init orion_pcie_reset(void __iomem *base)
  81. {
  82. u32 reg;
  83. int i;
  84. /*
  85. * MV-S104860-U0, Rev. C:
  86. * PCI Express Unit Soft Reset
  87. * When set, generates an internal reset in the PCI Express unit.
  88. * This bit should be cleared after the link is re-established.
  89. */
  90. reg = readl(base + PCIE_DEBUG_CTRL);
  91. reg |= PCIE_DEBUG_SOFT_RESET;
  92. writel(reg, base + PCIE_DEBUG_CTRL);
  93. for (i = 0; i < 20; i++) {
  94. mdelay(10);
  95. if (orion_pcie_link_up(base))
  96. break;
  97. }
  98. reg &= ~(PCIE_DEBUG_SOFT_RESET);
  99. writel(reg, base + PCIE_DEBUG_CTRL);
  100. }
  101. /*
  102. * Setup PCIE BARs and Address Decode Wins:
  103. * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
  104. * WIN[0-3] -> DRAM bank[0-3]
  105. */
  106. static void __init orion_pcie_setup_wins(void __iomem *base,
  107. struct mbus_dram_target_info *dram)
  108. {
  109. u32 size;
  110. int i;
  111. /*
  112. * First, disable and clear BARs and windows.
  113. */
  114. for (i = 1; i <= 2; i++) {
  115. writel(0, base + PCIE_BAR_CTRL_OFF(i));
  116. writel(0, base + PCIE_BAR_LO_OFF(i));
  117. writel(0, base + PCIE_BAR_HI_OFF(i));
  118. }
  119. for (i = 0; i < 5; i++) {
  120. writel(0, base + PCIE_WIN04_CTRL_OFF(i));
  121. writel(0, base + PCIE_WIN04_BASE_OFF(i));
  122. writel(0, base + PCIE_WIN04_REMAP_OFF(i));
  123. }
  124. writel(0, base + PCIE_WIN5_CTRL_OFF);
  125. writel(0, base + PCIE_WIN5_BASE_OFF);
  126. writel(0, base + PCIE_WIN5_REMAP_OFF);
  127. /*
  128. * Setup windows for DDR banks. Count total DDR size on the fly.
  129. */
  130. size = 0;
  131. for (i = 0; i < dram->num_cs; i++) {
  132. struct mbus_dram_window *cs = dram->cs + i;
  133. writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));
  134. writel(0, base + PCIE_WIN04_REMAP_OFF(i));
  135. writel(((cs->size - 1) & 0xffff0000) |
  136. (cs->mbus_attr << 8) |
  137. (dram->mbus_dram_target_id << 4) | 1,
  138. base + PCIE_WIN04_CTRL_OFF(i));
  139. size += cs->size;
  140. }
  141. /*
  142. * Round up 'size' to the nearest power of two.
  143. */
  144. if ((size & (size - 1)) != 0)
  145. size = 1 << fls(size);
  146. /*
  147. * Setup BAR[1] to all DRAM banks.
  148. */
  149. writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1));
  150. writel(0, base + PCIE_BAR_HI_OFF(1));
  151. writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1));
  152. }
  153. void __init orion_pcie_setup(void __iomem *base)
  154. {
  155. u16 cmd;
  156. u32 mask;
  157. /*
  158. * Point PCIe unit MBUS decode windows to DRAM space.
  159. */
  160. orion_pcie_setup_wins(base, &orion_mbus_dram_info);
  161. /*
  162. * Master + slave enable.
  163. */
  164. cmd = readw(base + PCIE_CMD_OFF);
  165. cmd |= PCI_COMMAND_IO;
  166. cmd |= PCI_COMMAND_MEMORY;
  167. cmd |= PCI_COMMAND_MASTER;
  168. writew(cmd, base + PCIE_CMD_OFF);
  169. /*
  170. * Enable interrupt lines A-D.
  171. */
  172. mask = readl(base + PCIE_MASK_OFF);
  173. mask |= 0x0f000000;
  174. writel(mask, base + PCIE_MASK_OFF);
  175. }
  176. int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
  177. u32 devfn, int where, int size, u32 *val)
  178. {
  179. writel(PCIE_CONF_BUS(bus->number) |
  180. PCIE_CONF_DEV(PCI_SLOT(devfn)) |
  181. PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
  182. PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
  183. base + PCIE_CONF_ADDR_OFF);
  184. *val = readl(base + PCIE_CONF_DATA_OFF);
  185. if (size == 1)
  186. *val = (*val >> (8 * (where & 3))) & 0xff;
  187. else if (size == 2)
  188. *val = (*val >> (8 * (where & 3))) & 0xffff;
  189. return PCIBIOS_SUCCESSFUL;
  190. }
  191. int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
  192. u32 devfn, int where, int size, u32 *val)
  193. {
  194. writel(PCIE_CONF_BUS(bus->number) |
  195. PCIE_CONF_DEV(PCI_SLOT(devfn)) |
  196. PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
  197. PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
  198. base + PCIE_CONF_ADDR_OFF);
  199. *val = readl(base + PCIE_CONF_DATA_OFF);
  200. if (bus->number != orion_pcie_get_local_bus_nr(base) ||
  201. PCI_FUNC(devfn) != 0)
  202. *val = readl(base + PCIE_HEADER_LOG_4_OFF);
  203. if (size == 1)
  204. *val = (*val >> (8 * (where & 3))) & 0xff;
  205. else if (size == 2)
  206. *val = (*val >> (8 * (where & 3))) & 0xffff;
  207. return PCIBIOS_SUCCESSFUL;
  208. }
  209. int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
  210. u32 devfn, int where, int size, u32 *val)
  211. {
  212. *val = readl(wa_base + (PCIE_CONF_BUS(bus->number) |
  213. PCIE_CONF_DEV(PCI_SLOT(devfn)) |
  214. PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
  215. PCIE_CONF_REG(where)));
  216. if (size == 1)
  217. *val = (*val >> (8 * (where & 3))) & 0xff;
  218. else if (size == 2)
  219. *val = (*val >> (8 * (where & 3))) & 0xffff;
  220. return PCIBIOS_SUCCESSFUL;
  221. }
  222. int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
  223. u32 devfn, int where, int size, u32 val)
  224. {
  225. int ret = PCIBIOS_SUCCESSFUL;
  226. writel(PCIE_CONF_BUS(bus->number) |
  227. PCIE_CONF_DEV(PCI_SLOT(devfn)) |
  228. PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
  229. PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
  230. base + PCIE_CONF_ADDR_OFF);
  231. if (size == 4) {
  232. writel(val, base + PCIE_CONF_DATA_OFF);
  233. } else if (size == 2) {
  234. writew(val, base + PCIE_CONF_DATA_OFF + (where & 3));
  235. } else if (size == 1) {
  236. writeb(val, base + PCIE_CONF_DATA_OFF + (where & 3));
  237. } else {
  238. ret = PCIBIOS_BAD_REGISTER_NUMBER;
  239. }
  240. return ret;
  241. }