setup-sh7367.c 10 KB

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  1. /*
  2. * sh7367 processor support
  3. *
  4. * Copyright (C) 2010 Magnus Damm
  5. * Copyright (C) 2008 Yoshihiro Shimoda
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/init.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/irq.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/uio_driver.h>
  26. #include <linux/delay.h>
  27. #include <linux/input.h>
  28. #include <linux/io.h>
  29. #include <linux/serial_sci.h>
  30. #include <linux/sh_timer.h>
  31. #include <mach/hardware.h>
  32. #include <mach/common.h>
  33. #include <mach/irqs.h>
  34. #include <asm/mach-types.h>
  35. #include <asm/mach/arch.h>
  36. #include <asm/mach/map.h>
  37. #include <asm/mach/time.h>
  38. static struct map_desc sh7367_io_desc[] __initdata = {
  39. /* create a 1:1 entity map for 0xe6xxxxxx
  40. * used by CPGA, INTC and PFC.
  41. */
  42. {
  43. .virtual = 0xe6000000,
  44. .pfn = __phys_to_pfn(0xe6000000),
  45. .length = 256 << 20,
  46. .type = MT_DEVICE_NONSHARED
  47. },
  48. };
  49. void __init sh7367_map_io(void)
  50. {
  51. iotable_init(sh7367_io_desc, ARRAY_SIZE(sh7367_io_desc));
  52. }
  53. /* SCIFA0 */
  54. static struct plat_sci_port scif0_platform_data = {
  55. .mapbase = 0xe6c40000,
  56. .flags = UPF_BOOT_AUTOCONF,
  57. .scscr = SCSCR_RE | SCSCR_TE,
  58. .scbrr_algo_id = SCBRR_ALGO_4,
  59. .type = PORT_SCIFA,
  60. .irqs = { evt2irq(0xc00), evt2irq(0xc00),
  61. evt2irq(0xc00), evt2irq(0xc00) },
  62. };
  63. static struct platform_device scif0_device = {
  64. .name = "sh-sci",
  65. .id = 0,
  66. .dev = {
  67. .platform_data = &scif0_platform_data,
  68. },
  69. };
  70. /* SCIFA1 */
  71. static struct plat_sci_port scif1_platform_data = {
  72. .mapbase = 0xe6c50000,
  73. .flags = UPF_BOOT_AUTOCONF,
  74. .scscr = SCSCR_RE | SCSCR_TE,
  75. .scbrr_algo_id = SCBRR_ALGO_4,
  76. .type = PORT_SCIFA,
  77. .irqs = { evt2irq(0xc20), evt2irq(0xc20),
  78. evt2irq(0xc20), evt2irq(0xc20) },
  79. };
  80. static struct platform_device scif1_device = {
  81. .name = "sh-sci",
  82. .id = 1,
  83. .dev = {
  84. .platform_data = &scif1_platform_data,
  85. },
  86. };
  87. /* SCIFA2 */
  88. static struct plat_sci_port scif2_platform_data = {
  89. .mapbase = 0xe6c60000,
  90. .flags = UPF_BOOT_AUTOCONF,
  91. .scscr = SCSCR_RE | SCSCR_TE,
  92. .scbrr_algo_id = SCBRR_ALGO_4,
  93. .type = PORT_SCIFA,
  94. .irqs = { evt2irq(0xc40), evt2irq(0xc40),
  95. evt2irq(0xc40), evt2irq(0xc40) },
  96. };
  97. static struct platform_device scif2_device = {
  98. .name = "sh-sci",
  99. .id = 2,
  100. .dev = {
  101. .platform_data = &scif2_platform_data,
  102. },
  103. };
  104. /* SCIFA3 */
  105. static struct plat_sci_port scif3_platform_data = {
  106. .mapbase = 0xe6c70000,
  107. .flags = UPF_BOOT_AUTOCONF,
  108. .scscr = SCSCR_RE | SCSCR_TE,
  109. .scbrr_algo_id = SCBRR_ALGO_4,
  110. .type = PORT_SCIFA,
  111. .irqs = { evt2irq(0xc60), evt2irq(0xc60),
  112. evt2irq(0xc60), evt2irq(0xc60) },
  113. };
  114. static struct platform_device scif3_device = {
  115. .name = "sh-sci",
  116. .id = 3,
  117. .dev = {
  118. .platform_data = &scif3_platform_data,
  119. },
  120. };
  121. /* SCIFA4 */
  122. static struct plat_sci_port scif4_platform_data = {
  123. .mapbase = 0xe6c80000,
  124. .flags = UPF_BOOT_AUTOCONF,
  125. .scscr = SCSCR_RE | SCSCR_TE,
  126. .scbrr_algo_id = SCBRR_ALGO_4,
  127. .type = PORT_SCIFA,
  128. .irqs = { evt2irq(0xd20), evt2irq(0xd20),
  129. evt2irq(0xd20), evt2irq(0xd20) },
  130. };
  131. static struct platform_device scif4_device = {
  132. .name = "sh-sci",
  133. .id = 4,
  134. .dev = {
  135. .platform_data = &scif4_platform_data,
  136. },
  137. };
  138. /* SCIFA5 */
  139. static struct plat_sci_port scif5_platform_data = {
  140. .mapbase = 0xe6cb0000,
  141. .flags = UPF_BOOT_AUTOCONF,
  142. .scscr = SCSCR_RE | SCSCR_TE,
  143. .scbrr_algo_id = SCBRR_ALGO_4,
  144. .type = PORT_SCIFA,
  145. .irqs = { evt2irq(0xd40), evt2irq(0xd40),
  146. evt2irq(0xd40), evt2irq(0xd40) },
  147. };
  148. static struct platform_device scif5_device = {
  149. .name = "sh-sci",
  150. .id = 5,
  151. .dev = {
  152. .platform_data = &scif5_platform_data,
  153. },
  154. };
  155. /* SCIFB */
  156. static struct plat_sci_port scif6_platform_data = {
  157. .mapbase = 0xe6c30000,
  158. .flags = UPF_BOOT_AUTOCONF,
  159. .scscr = SCSCR_RE | SCSCR_TE,
  160. .scbrr_algo_id = SCBRR_ALGO_4,
  161. .type = PORT_SCIFB,
  162. .irqs = { evt2irq(0xd60), evt2irq(0xd60),
  163. evt2irq(0xd60), evt2irq(0xd60) },
  164. };
  165. static struct platform_device scif6_device = {
  166. .name = "sh-sci",
  167. .id = 6,
  168. .dev = {
  169. .platform_data = &scif6_platform_data,
  170. },
  171. };
  172. static struct sh_timer_config cmt10_platform_data = {
  173. .name = "CMT10",
  174. .channel_offset = 0x10,
  175. .timer_bit = 0,
  176. .clockevent_rating = 125,
  177. .clocksource_rating = 125,
  178. };
  179. static struct resource cmt10_resources[] = {
  180. [0] = {
  181. .name = "CMT10",
  182. .start = 0xe6138010,
  183. .end = 0xe613801b,
  184. .flags = IORESOURCE_MEM,
  185. },
  186. [1] = {
  187. .start = evt2irq(0xb00), /* CMT1_CMT10 */
  188. .flags = IORESOURCE_IRQ,
  189. },
  190. };
  191. static struct platform_device cmt10_device = {
  192. .name = "sh_cmt",
  193. .id = 10,
  194. .dev = {
  195. .platform_data = &cmt10_platform_data,
  196. },
  197. .resource = cmt10_resources,
  198. .num_resources = ARRAY_SIZE(cmt10_resources),
  199. };
  200. /* VPU */
  201. static struct uio_info vpu_platform_data = {
  202. .name = "VPU5",
  203. .version = "0",
  204. .irq = intcs_evt2irq(0x980),
  205. };
  206. static struct resource vpu_resources[] = {
  207. [0] = {
  208. .name = "VPU",
  209. .start = 0xfe900000,
  210. .end = 0xfe902807,
  211. .flags = IORESOURCE_MEM,
  212. },
  213. };
  214. static struct platform_device vpu_device = {
  215. .name = "uio_pdrv_genirq",
  216. .id = 0,
  217. .dev = {
  218. .platform_data = &vpu_platform_data,
  219. },
  220. .resource = vpu_resources,
  221. .num_resources = ARRAY_SIZE(vpu_resources),
  222. };
  223. /* VEU0 */
  224. static struct uio_info veu0_platform_data = {
  225. .name = "VEU0",
  226. .version = "0",
  227. .irq = intcs_evt2irq(0x700),
  228. };
  229. static struct resource veu0_resources[] = {
  230. [0] = {
  231. .name = "VEU0",
  232. .start = 0xfe920000,
  233. .end = 0xfe9200b7,
  234. .flags = IORESOURCE_MEM,
  235. },
  236. };
  237. static struct platform_device veu0_device = {
  238. .name = "uio_pdrv_genirq",
  239. .id = 1,
  240. .dev = {
  241. .platform_data = &veu0_platform_data,
  242. },
  243. .resource = veu0_resources,
  244. .num_resources = ARRAY_SIZE(veu0_resources),
  245. };
  246. /* VEU1 */
  247. static struct uio_info veu1_platform_data = {
  248. .name = "VEU1",
  249. .version = "0",
  250. .irq = intcs_evt2irq(0x720),
  251. };
  252. static struct resource veu1_resources[] = {
  253. [0] = {
  254. .name = "VEU1",
  255. .start = 0xfe924000,
  256. .end = 0xfe9240b7,
  257. .flags = IORESOURCE_MEM,
  258. },
  259. };
  260. static struct platform_device veu1_device = {
  261. .name = "uio_pdrv_genirq",
  262. .id = 2,
  263. .dev = {
  264. .platform_data = &veu1_platform_data,
  265. },
  266. .resource = veu1_resources,
  267. .num_resources = ARRAY_SIZE(veu1_resources),
  268. };
  269. /* VEU2 */
  270. static struct uio_info veu2_platform_data = {
  271. .name = "VEU2",
  272. .version = "0",
  273. .irq = intcs_evt2irq(0x740),
  274. };
  275. static struct resource veu2_resources[] = {
  276. [0] = {
  277. .name = "VEU2",
  278. .start = 0xfe928000,
  279. .end = 0xfe9280b7,
  280. .flags = IORESOURCE_MEM,
  281. },
  282. };
  283. static struct platform_device veu2_device = {
  284. .name = "uio_pdrv_genirq",
  285. .id = 3,
  286. .dev = {
  287. .platform_data = &veu2_platform_data,
  288. },
  289. .resource = veu2_resources,
  290. .num_resources = ARRAY_SIZE(veu2_resources),
  291. };
  292. /* VEU3 */
  293. static struct uio_info veu3_platform_data = {
  294. .name = "VEU3",
  295. .version = "0",
  296. .irq = intcs_evt2irq(0x760),
  297. };
  298. static struct resource veu3_resources[] = {
  299. [0] = {
  300. .name = "VEU3",
  301. .start = 0xfe92c000,
  302. .end = 0xfe92c0b7,
  303. .flags = IORESOURCE_MEM,
  304. },
  305. };
  306. static struct platform_device veu3_device = {
  307. .name = "uio_pdrv_genirq",
  308. .id = 4,
  309. .dev = {
  310. .platform_data = &veu3_platform_data,
  311. },
  312. .resource = veu3_resources,
  313. .num_resources = ARRAY_SIZE(veu3_resources),
  314. };
  315. /* VEU2H */
  316. static struct uio_info veu2h_platform_data = {
  317. .name = "VEU2H",
  318. .version = "0",
  319. .irq = intcs_evt2irq(0x520),
  320. };
  321. static struct resource veu2h_resources[] = {
  322. [0] = {
  323. .name = "VEU2H",
  324. .start = 0xfe93c000,
  325. .end = 0xfe93c27b,
  326. .flags = IORESOURCE_MEM,
  327. },
  328. };
  329. static struct platform_device veu2h_device = {
  330. .name = "uio_pdrv_genirq",
  331. .id = 5,
  332. .dev = {
  333. .platform_data = &veu2h_platform_data,
  334. },
  335. .resource = veu2h_resources,
  336. .num_resources = ARRAY_SIZE(veu2h_resources),
  337. };
  338. /* JPU */
  339. static struct uio_info jpu_platform_data = {
  340. .name = "JPU",
  341. .version = "0",
  342. .irq = intcs_evt2irq(0x560),
  343. };
  344. static struct resource jpu_resources[] = {
  345. [0] = {
  346. .name = "JPU",
  347. .start = 0xfe980000,
  348. .end = 0xfe9902d3,
  349. .flags = IORESOURCE_MEM,
  350. },
  351. };
  352. static struct platform_device jpu_device = {
  353. .name = "uio_pdrv_genirq",
  354. .id = 6,
  355. .dev = {
  356. .platform_data = &jpu_platform_data,
  357. },
  358. .resource = jpu_resources,
  359. .num_resources = ARRAY_SIZE(jpu_resources),
  360. };
  361. /* SPU1 */
  362. static struct uio_info spu1_platform_data = {
  363. .name = "SPU1",
  364. .version = "0",
  365. .irq = evt2irq(0xfc0),
  366. };
  367. static struct resource spu1_resources[] = {
  368. [0] = {
  369. .name = "SPU1",
  370. .start = 0xfe300000,
  371. .end = 0xfe3fffff,
  372. .flags = IORESOURCE_MEM,
  373. },
  374. };
  375. static struct platform_device spu1_device = {
  376. .name = "uio_pdrv_genirq",
  377. .id = 7,
  378. .dev = {
  379. .platform_data = &spu1_platform_data,
  380. },
  381. .resource = spu1_resources,
  382. .num_resources = ARRAY_SIZE(spu1_resources),
  383. };
  384. static struct platform_device *sh7367_early_devices[] __initdata = {
  385. &scif0_device,
  386. &scif1_device,
  387. &scif2_device,
  388. &scif3_device,
  389. &scif4_device,
  390. &scif5_device,
  391. &scif6_device,
  392. &cmt10_device,
  393. };
  394. static struct platform_device *sh7367_devices[] __initdata = {
  395. &vpu_device,
  396. &veu0_device,
  397. &veu1_device,
  398. &veu2_device,
  399. &veu3_device,
  400. &veu2h_device,
  401. &jpu_device,
  402. &spu1_device,
  403. };
  404. void __init sh7367_add_standard_devices(void)
  405. {
  406. platform_add_devices(sh7367_early_devices,
  407. ARRAY_SIZE(sh7367_early_devices));
  408. platform_add_devices(sh7367_devices,
  409. ARRAY_SIZE(sh7367_devices));
  410. }
  411. static void __init sh7367_earlytimer_init(void)
  412. {
  413. sh7367_clock_init();
  414. shmobile_earlytimer_init();
  415. }
  416. #define SYMSTPCR2 0xe6158048
  417. #define SYMSTPCR2_CMT1 (1 << 29)
  418. void __init sh7367_add_early_devices(void)
  419. {
  420. /* enable clock to CMT1 */
  421. __raw_writel(__raw_readl(SYMSTPCR2) & ~SYMSTPCR2_CMT1, SYMSTPCR2);
  422. early_platform_add_devices(sh7367_early_devices,
  423. ARRAY_SIZE(sh7367_early_devices));
  424. /* setup early console here as well */
  425. shmobile_setup_console();
  426. /* override timer setup with soc-specific code */
  427. shmobile_timer.init = sh7367_earlytimer_init;
  428. }