uncompress.h 4.4 KB

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  1. /* linux/arch/arm/mach-s5p64x0/include/mach/uncompress.h
  2. *
  3. * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * S5P64X0 - uncompress code
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #ifndef __ASM_ARCH_UNCOMPRESS_H
  13. #define __ASM_ARCH_UNCOMPRESS_H
  14. #include <mach/map.h>
  15. /*
  16. * cannot use commonly <plat/uncompress.h>
  17. * because uart base of S5P6440 and S5P6450 is different
  18. */
  19. typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
  20. /* uart setup */
  21. unsigned int fifo_mask;
  22. unsigned int fifo_max;
  23. /* forward declerations */
  24. static void arch_detect_cpu(void);
  25. /* defines for UART registers */
  26. #include <plat/regs-serial.h>
  27. #include <plat/regs-watchdog.h>
  28. /* working in physical space... */
  29. #undef S3C2410_WDOGREG
  30. #define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
  31. /* how many bytes we allow into the FIFO at a time in FIFO mode */
  32. #define FIFO_MAX (14)
  33. unsigned long uart_base;
  34. static __inline__ void get_uart_base(void)
  35. {
  36. unsigned int chipid;
  37. chipid = *(const volatile unsigned int __force *) 0xE0100118;
  38. uart_base = S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT;
  39. if ((chipid & 0xff000) == 0x50000)
  40. uart_base += 0xEC800000;
  41. else
  42. uart_base += 0xEC000000;
  43. }
  44. static __inline__ void uart_wr(unsigned int reg, unsigned int val)
  45. {
  46. volatile unsigned int *ptr;
  47. get_uart_base();
  48. ptr = (volatile unsigned int *)(reg + uart_base);
  49. *ptr = val;
  50. }
  51. static __inline__ unsigned int uart_rd(unsigned int reg)
  52. {
  53. volatile unsigned int *ptr;
  54. get_uart_base();
  55. ptr = (volatile unsigned int *)(reg + uart_base);
  56. return *ptr;
  57. }
  58. /*
  59. * we can deal with the case the UARTs are being run
  60. * in FIFO mode, so that we don't hold up our execution
  61. * waiting for tx to happen...
  62. */
  63. static void putc(int ch)
  64. {
  65. if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
  66. int level;
  67. while (1) {
  68. level = uart_rd(S3C2410_UFSTAT);
  69. level &= fifo_mask;
  70. if (level < fifo_max)
  71. break;
  72. }
  73. } else {
  74. /* not using fifos */
  75. while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
  76. barrier();
  77. }
  78. /* write byte to transmission register */
  79. uart_wr(S3C2410_UTXH, ch);
  80. }
  81. static inline void flush(void)
  82. {
  83. }
  84. #define __raw_writel(d, ad) \
  85. do { \
  86. *((volatile unsigned int __force *)(ad)) = (d); \
  87. } while (0)
  88. /*
  89. * CONFIG_S3C_BOOT_WATCHDOG
  90. *
  91. * Simple boot-time watchdog setup, to reboot the system if there is
  92. * any problem with the boot process
  93. */
  94. #ifdef CONFIG_S3C_BOOT_WATCHDOG
  95. #define WDOG_COUNT (0xff00)
  96. static inline void arch_decomp_wdog(void)
  97. {
  98. __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
  99. }
  100. static void arch_decomp_wdog_start(void)
  101. {
  102. __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
  103. __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
  104. __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
  105. }
  106. #else
  107. #define arch_decomp_wdog_start()
  108. #define arch_decomp_wdog()
  109. #endif
  110. #ifdef CONFIG_S3C_BOOT_ERROR_RESET
  111. static void arch_decomp_error(const char *x)
  112. {
  113. putstr("\n\n");
  114. putstr(x);
  115. putstr("\n\n -- System resetting\n");
  116. __raw_writel(0x4000, S3C2410_WTDAT);
  117. __raw_writel(0x4000, S3C2410_WTCNT);
  118. __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
  119. while(1);
  120. }
  121. #define arch_error arch_decomp_error
  122. #endif
  123. #ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
  124. static inline void arch_enable_uart_fifo(void)
  125. {
  126. u32 fifocon = uart_rd(S3C2410_UFCON);
  127. if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
  128. fifocon |= S3C2410_UFCON_RESETBOTH;
  129. uart_wr(S3C2410_UFCON, fifocon);
  130. /* wait for fifo reset to complete */
  131. while (1) {
  132. fifocon = uart_rd(S3C2410_UFCON);
  133. if (!(fifocon & S3C2410_UFCON_RESETBOTH))
  134. break;
  135. }
  136. }
  137. }
  138. #else
  139. #define arch_enable_uart_fifo() do { } while(0)
  140. #endif
  141. static void arch_decomp_setup(void)
  142. {
  143. /*
  144. * we may need to setup the uart(s) here if we are not running
  145. * on an BAST... the BAST will have left the uarts configured
  146. * after calling linux.
  147. */
  148. arch_detect_cpu();
  149. arch_decomp_wdog_start();
  150. /*
  151. * Enable the UART FIFOs if they where not enabled and our
  152. * configuration says we should turn them on.
  153. */
  154. arch_enable_uart_fifo();
  155. }
  156. static void arch_detect_cpu(void)
  157. {
  158. /* we do not need to do any cpu detection here at the moment. */
  159. }
  160. #endif /* __ASM_ARCH_UNCOMPRESS_H */