pm-s3c2410.c 4.6 KB

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  1. /* linux/arch/arm/mach-s3c2410/pm.c
  2. *
  3. * Copyright (c) 2006 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410 (and compatible) Power Manager (Suspend-To-RAM) support
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/init.h>
  23. #include <linux/suspend.h>
  24. #include <linux/errno.h>
  25. #include <linux/time.h>
  26. #include <linux/device.h>
  27. #include <linux/syscore_ops.h>
  28. #include <linux/gpio.h>
  29. #include <linux/io.h>
  30. #include <mach/hardware.h>
  31. #include <asm/mach-types.h>
  32. #include <mach/regs-gpio.h>
  33. #include <mach/h1940.h>
  34. #include <plat/cpu.h>
  35. #include <plat/pm.h>
  36. static void s3c2410_pm_prepare(void)
  37. {
  38. /* ensure at least GSTATUS3 has the resume address */
  39. __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3);
  40. S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
  41. S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
  42. if (machine_is_h1940()) {
  43. void *base = phys_to_virt(H1940_SUSPEND_CHECK);
  44. unsigned long ptr;
  45. unsigned long calc = 0;
  46. /* generate check for the bootloader to check on resume */
  47. for (ptr = 0; ptr < 0x40000; ptr += 0x400)
  48. calc += __raw_readl(base+ptr);
  49. __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
  50. }
  51. /* RX3715 and RX1950 use similar to H1940 code and the
  52. * same offsets for resume and checksum pointers */
  53. if (machine_is_rx3715() || machine_is_rx1950()) {
  54. void *base = phys_to_virt(H1940_SUSPEND_CHECK);
  55. unsigned long ptr;
  56. unsigned long calc = 0;
  57. /* generate check for the bootloader to check on resume */
  58. for (ptr = 0; ptr < 0x40000; ptr += 0x4)
  59. calc += __raw_readl(base+ptr);
  60. __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
  61. }
  62. if ( machine_is_aml_m5900() )
  63. s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
  64. if (machine_is_rx1950()) {
  65. /* According to S3C2442 user's manual, page 7-17,
  66. * when the system is operating in NAND boot mode,
  67. * the hardware pin configuration - EINT[23:21] –
  68. * must be set as input for starting up after
  69. * wakeup from sleep mode
  70. */
  71. s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT);
  72. s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT);
  73. s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT);
  74. }
  75. }
  76. static void s3c2410_pm_resume(void)
  77. {
  78. unsigned long tmp;
  79. /* unset the return-from-sleep flag, to ensure reset */
  80. tmp = __raw_readl(S3C2410_GSTATUS2);
  81. tmp &= S3C2410_GSTATUS2_OFFRESET;
  82. __raw_writel(tmp, S3C2410_GSTATUS2);
  83. if ( machine_is_aml_m5900() )
  84. s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
  85. }
  86. struct syscore_ops s3c2410_pm_syscore_ops = {
  87. .resume = s3c2410_pm_resume,
  88. };
  89. static int s3c2410_pm_add(struct device *dev, struct subsys_interface *sif)
  90. {
  91. pm_cpu_prep = s3c2410_pm_prepare;
  92. pm_cpu_sleep = s3c2410_cpu_suspend;
  93. return 0;
  94. }
  95. #if defined(CONFIG_CPU_S3C2410)
  96. static struct subsys_interface s3c2410_pm_interface = {
  97. .name = "s3c2410_pm",
  98. .subsys = &s3c2410_subsys,
  99. .add_dev = s3c2410_pm_add,
  100. };
  101. /* register ourselves */
  102. static int __init s3c2410_pm_drvinit(void)
  103. {
  104. return subsys_interface_register(&s3c2410_pm_interface);
  105. }
  106. arch_initcall(s3c2410_pm_drvinit);
  107. static struct subsys_interface s3c2410a_pm_interface = {
  108. .name = "s3c2410a_pm",
  109. .subsys = &s3c2410a_subsys,
  110. .add_dev = s3c2410_pm_add,
  111. };
  112. static int __init s3c2410a_pm_drvinit(void)
  113. {
  114. return subsys_interface_register(&s3c2410a_pm_interface);
  115. }
  116. arch_initcall(s3c2410a_pm_drvinit);
  117. #endif
  118. #if defined(CONFIG_CPU_S3C2440)
  119. static struct subsys_interface s3c2440_pm_interface = {
  120. .name = "s3c2440_pm",
  121. .subsys = &s3c2440_subsys,
  122. .add_dev = s3c2410_pm_add,
  123. };
  124. static int __init s3c2440_pm_drvinit(void)
  125. {
  126. return subsys_interface_register(&s3c2440_pm_interface);
  127. }
  128. arch_initcall(s3c2440_pm_drvinit);
  129. #endif
  130. #if defined(CONFIG_CPU_S3C2442)
  131. static struct subsys_interface s3c2442_pm_interface = {
  132. .name = "s3c2442_pm",
  133. .subsys = &s3c2442_subsys,
  134. .add_dev = s3c2410_pm_add,
  135. };
  136. static int __init s3c2442_pm_drvinit(void)
  137. {
  138. return subsys_interface_register(&s3c2442_pm_interface);
  139. }
  140. arch_initcall(s3c2442_pm_drvinit);
  141. #endif