mach-rx3715.c 4.7 KB

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  1. /* linux/arch/arm/mach-s3c2440/mach-rx3715.c
  2. *
  3. * Copyright (c) 2003-2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * http://www.handhelds.org/projects/rx3715.html
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/list.h>
  17. #include <linux/memblock.h>
  18. #include <linux/timer.h>
  19. #include <linux/init.h>
  20. #include <linux/tty.h>
  21. #include <linux/console.h>
  22. #include <linux/device.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/serial_core.h>
  25. #include <linux/serial.h>
  26. #include <linux/io.h>
  27. #include <linux/mtd/mtd.h>
  28. #include <linux/mtd/nand.h>
  29. #include <linux/mtd/nand_ecc.h>
  30. #include <linux/mtd/partitions.h>
  31. #include <asm/mach/arch.h>
  32. #include <asm/mach/map.h>
  33. #include <asm/mach/irq.h>
  34. #include <mach/hardware.h>
  35. #include <asm/irq.h>
  36. #include <asm/mach-types.h>
  37. #include <plat/regs-serial.h>
  38. #include <mach/regs-gpio.h>
  39. #include <mach/regs-lcd.h>
  40. #include <mach/h1940.h>
  41. #include <plat/nand.h>
  42. #include <mach/fb.h>
  43. #include <plat/clock.h>
  44. #include <plat/devs.h>
  45. #include <plat/cpu.h>
  46. #include <plat/pm.h>
  47. #include "common.h"
  48. static struct map_desc rx3715_iodesc[] __initdata = {
  49. /* dump ISA space somewhere unused */
  50. {
  51. .virtual = (u32)S3C24XX_VA_ISA_WORD,
  52. .pfn = __phys_to_pfn(S3C2410_CS3),
  53. .length = SZ_1M,
  54. .type = MT_DEVICE,
  55. }, {
  56. .virtual = (u32)S3C24XX_VA_ISA_BYTE,
  57. .pfn = __phys_to_pfn(S3C2410_CS3),
  58. .length = SZ_1M,
  59. .type = MT_DEVICE,
  60. },
  61. };
  62. static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
  63. [0] = {
  64. .hwport = 0,
  65. .flags = 0,
  66. .ucon = 0x3c5,
  67. .ulcon = 0x03,
  68. .ufcon = 0x51,
  69. .clk_sel = S3C2410_UCON_CLKSEL3,
  70. },
  71. [1] = {
  72. .hwport = 1,
  73. .flags = 0,
  74. .ucon = 0x3c5,
  75. .ulcon = 0x03,
  76. .ufcon = 0x00,
  77. .clk_sel = S3C2410_UCON_CLKSEL3,
  78. },
  79. /* IR port */
  80. [2] = {
  81. .hwport = 2,
  82. .uart_flags = UPF_CONS_FLOW,
  83. .ucon = 0x3c5,
  84. .ulcon = 0x43,
  85. .ufcon = 0x51,
  86. .clk_sel = S3C2410_UCON_CLKSEL3,
  87. }
  88. };
  89. /* framebuffer lcd controller information */
  90. static struct s3c2410fb_display rx3715_lcdcfg __initdata = {
  91. .lcdcon5 = S3C2410_LCDCON5_INVVLINE |
  92. S3C2410_LCDCON5_FRM565 |
  93. S3C2410_LCDCON5_HWSWP,
  94. .type = S3C2410_LCDCON1_TFT,
  95. .width = 240,
  96. .height = 320,
  97. .pixclock = 260000,
  98. .xres = 240,
  99. .yres = 320,
  100. .bpp = 16,
  101. .left_margin = 36,
  102. .right_margin = 36,
  103. .hsync_len = 8,
  104. .upper_margin = 6,
  105. .lower_margin = 7,
  106. .vsync_len = 3,
  107. };
  108. static struct s3c2410fb_mach_info rx3715_fb_info __initdata = {
  109. .displays = &rx3715_lcdcfg,
  110. .num_displays = 1,
  111. .default_display = 0,
  112. .lpcsel = 0xf82,
  113. .gpccon = 0xaa955699,
  114. .gpccon_mask = 0xffc003cc,
  115. .gpcup = 0x0000ffff,
  116. .gpcup_mask = 0xffffffff,
  117. .gpdcon = 0xaa95aaa1,
  118. .gpdcon_mask = 0xffc0fff0,
  119. .gpdup = 0x0000faff,
  120. .gpdup_mask = 0xffffffff,
  121. };
  122. static struct mtd_partition __initdata rx3715_nand_part[] = {
  123. [0] = {
  124. .name = "Whole Flash",
  125. .offset = 0,
  126. .size = MTDPART_SIZ_FULL,
  127. .mask_flags = MTD_WRITEABLE,
  128. }
  129. };
  130. static struct s3c2410_nand_set __initdata rx3715_nand_sets[] = {
  131. [0] = {
  132. .name = "Internal",
  133. .nr_chips = 1,
  134. .nr_partitions = ARRAY_SIZE(rx3715_nand_part),
  135. .partitions = rx3715_nand_part,
  136. },
  137. };
  138. static struct s3c2410_platform_nand __initdata rx3715_nand_info = {
  139. .tacls = 25,
  140. .twrph0 = 50,
  141. .twrph1 = 15,
  142. .nr_sets = ARRAY_SIZE(rx3715_nand_sets),
  143. .sets = rx3715_nand_sets,
  144. };
  145. static struct platform_device *rx3715_devices[] __initdata = {
  146. &s3c_device_ohci,
  147. &s3c_device_lcd,
  148. &s3c_device_wdt,
  149. &s3c_device_i2c0,
  150. &s3c_device_iis,
  151. &s3c_device_nand,
  152. };
  153. static void __init rx3715_map_io(void)
  154. {
  155. s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
  156. s3c24xx_init_clocks(16934000);
  157. s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
  158. }
  159. /* H1940 and RX3715 need to reserve this for suspend */
  160. static void __init rx3715_reserve(void)
  161. {
  162. memblock_reserve(0x30003000, 0x1000);
  163. memblock_reserve(0x30081000, 0x1000);
  164. }
  165. static void __init rx3715_init_irq(void)
  166. {
  167. s3c24xx_init_irq();
  168. }
  169. static void __init rx3715_init_machine(void)
  170. {
  171. #ifdef CONFIG_PM_H1940
  172. memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
  173. #endif
  174. s3c_pm_init();
  175. s3c_nand_set_platdata(&rx3715_nand_info);
  176. s3c24xx_fb_set_platdata(&rx3715_fb_info);
  177. platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
  178. }
  179. MACHINE_START(RX3715, "IPAQ-RX3715")
  180. /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
  181. .atag_offset = 0x100,
  182. .map_io = rx3715_map_io,
  183. .reserve = rx3715_reserve,
  184. .init_irq = rx3715_init_irq,
  185. .init_machine = rx3715_init_machine,
  186. .timer = &s3c24xx_timer,
  187. .restart = s3c244x_restart,
  188. MACHINE_END