tpmi.c 7.0 KB

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  1. /*
  2. * iop13xx tpmi device resources
  3. * Copyright (c) 2005-2006, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  16. * Place - Suite 330, Boston, MA 02111-1307 USA.
  17. *
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/init.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/dma-mapping.h>
  23. #include <linux/io.h>
  24. #include <asm/irq.h>
  25. #include <asm/sizes.h>
  26. /* assumes CONTROLLER_ONLY# is never asserted in the ESSR register */
  27. #define IOP13XX_TPMI_MMR(dev) IOP13XX_REG_ADDR32_PHYS(0x48000 + (dev << 12))
  28. #define IOP13XX_TPMI_MEM(dev) IOP13XX_REG_ADDR32_PHYS(0x60000 + (dev << 13))
  29. #define IOP13XX_TPMI_CTRL(dev) IOP13XX_REG_ADDR32_PHYS(0x50000 + (dev << 10))
  30. #define IOP13XX_TPMI_IOP_CTRL(dev) (IOP13XX_TPMI_CTRL(dev) + 0x2000)
  31. #define IOP13XX_TPMI_MMR_SIZE (SZ_4K - 1)
  32. #define IOP13XX_TPMI_MEM_SIZE (255)
  33. #define IOP13XX_TPMI_MEM_CTRL (SZ_1K - 1)
  34. #define IOP13XX_TPMI_RESOURCE_MMR 0
  35. #define IOP13XX_TPMI_RESOURCE_MEM 1
  36. #define IOP13XX_TPMI_RESOURCE_CTRL 2
  37. #define IOP13XX_TPMI_RESOURCE_IOP_CTRL 3
  38. #define IOP13XX_TPMI_RESOURCE_IRQ 4
  39. static struct resource iop13xx_tpmi_0_resources[] = {
  40. [IOP13XX_TPMI_RESOURCE_MMR] = {
  41. .start = IOP13XX_TPMI_MMR(4), /* tpmi0 starts at dev == 4 */
  42. .end = IOP13XX_TPMI_MMR(4) + IOP13XX_TPMI_MMR_SIZE,
  43. .flags = IORESOURCE_MEM,
  44. },
  45. [IOP13XX_TPMI_RESOURCE_MEM] = {
  46. .start = IOP13XX_TPMI_MEM(0),
  47. .end = IOP13XX_TPMI_MEM(0) + IOP13XX_TPMI_MEM_SIZE,
  48. .flags = IORESOURCE_MEM,
  49. },
  50. [IOP13XX_TPMI_RESOURCE_CTRL] = {
  51. .start = IOP13XX_TPMI_CTRL(0),
  52. .end = IOP13XX_TPMI_CTRL(0) + IOP13XX_TPMI_MEM_CTRL,
  53. .flags = IORESOURCE_MEM,
  54. },
  55. [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
  56. .start = IOP13XX_TPMI_IOP_CTRL(0),
  57. .end = IOP13XX_TPMI_IOP_CTRL(0) + IOP13XX_TPMI_MEM_CTRL,
  58. .flags = IORESOURCE_MEM,
  59. },
  60. [IOP13XX_TPMI_RESOURCE_IRQ] = {
  61. .start = IRQ_IOP13XX_TPMI0_OUT,
  62. .end = IRQ_IOP13XX_TPMI0_OUT,
  63. .flags = IORESOURCE_IRQ
  64. }
  65. };
  66. static struct resource iop13xx_tpmi_1_resources[] = {
  67. [IOP13XX_TPMI_RESOURCE_MMR] = {
  68. .start = IOP13XX_TPMI_MMR(1),
  69. .end = IOP13XX_TPMI_MMR(1) + IOP13XX_TPMI_MMR_SIZE,
  70. .flags = IORESOURCE_MEM,
  71. },
  72. [IOP13XX_TPMI_RESOURCE_MEM] = {
  73. .start = IOP13XX_TPMI_MEM(1),
  74. .end = IOP13XX_TPMI_MEM(1) + IOP13XX_TPMI_MEM_SIZE,
  75. .flags = IORESOURCE_MEM,
  76. },
  77. [IOP13XX_TPMI_RESOURCE_CTRL] = {
  78. .start = IOP13XX_TPMI_CTRL(1),
  79. .end = IOP13XX_TPMI_CTRL(1) + IOP13XX_TPMI_MEM_CTRL,
  80. .flags = IORESOURCE_MEM,
  81. },
  82. [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
  83. .start = IOP13XX_TPMI_IOP_CTRL(1),
  84. .end = IOP13XX_TPMI_IOP_CTRL(1) + IOP13XX_TPMI_MEM_CTRL,
  85. .flags = IORESOURCE_MEM,
  86. },
  87. [IOP13XX_TPMI_RESOURCE_IRQ] = {
  88. .start = IRQ_IOP13XX_TPMI1_OUT,
  89. .end = IRQ_IOP13XX_TPMI1_OUT,
  90. .flags = IORESOURCE_IRQ
  91. }
  92. };
  93. static struct resource iop13xx_tpmi_2_resources[] = {
  94. [IOP13XX_TPMI_RESOURCE_MMR] = {
  95. .start = IOP13XX_TPMI_MMR(2),
  96. .end = IOP13XX_TPMI_MMR(2) + IOP13XX_TPMI_MMR_SIZE,
  97. .flags = IORESOURCE_MEM,
  98. },
  99. [IOP13XX_TPMI_RESOURCE_MEM] = {
  100. .start = IOP13XX_TPMI_MEM(2),
  101. .end = IOP13XX_TPMI_MEM(2) + IOP13XX_TPMI_MEM_SIZE,
  102. .flags = IORESOURCE_MEM,
  103. },
  104. [IOP13XX_TPMI_RESOURCE_CTRL] = {
  105. .start = IOP13XX_TPMI_CTRL(2),
  106. .end = IOP13XX_TPMI_CTRL(2) + IOP13XX_TPMI_MEM_CTRL,
  107. .flags = IORESOURCE_MEM,
  108. },
  109. [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
  110. .start = IOP13XX_TPMI_IOP_CTRL(2),
  111. .end = IOP13XX_TPMI_IOP_CTRL(2) + IOP13XX_TPMI_MEM_CTRL,
  112. .flags = IORESOURCE_MEM,
  113. },
  114. [IOP13XX_TPMI_RESOURCE_IRQ] = {
  115. .start = IRQ_IOP13XX_TPMI2_OUT,
  116. .end = IRQ_IOP13XX_TPMI2_OUT,
  117. .flags = IORESOURCE_IRQ
  118. }
  119. };
  120. static struct resource iop13xx_tpmi_3_resources[] = {
  121. [IOP13XX_TPMI_RESOURCE_MMR] = {
  122. .start = IOP13XX_TPMI_MMR(3),
  123. .end = IOP13XX_TPMI_MMR(3) + IOP13XX_TPMI_MMR_SIZE,
  124. .flags = IORESOURCE_MEM,
  125. },
  126. [IOP13XX_TPMI_RESOURCE_MEM] = {
  127. .start = IOP13XX_TPMI_MEM(3),
  128. .end = IOP13XX_TPMI_MEM(3) + IOP13XX_TPMI_MEM_SIZE,
  129. .flags = IORESOURCE_MEM,
  130. },
  131. [IOP13XX_TPMI_RESOURCE_CTRL] = {
  132. .start = IOP13XX_TPMI_CTRL(3),
  133. .end = IOP13XX_TPMI_CTRL(3) + IOP13XX_TPMI_MEM_CTRL,
  134. .flags = IORESOURCE_MEM,
  135. },
  136. [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
  137. .start = IOP13XX_TPMI_IOP_CTRL(3),
  138. .end = IOP13XX_TPMI_IOP_CTRL(3) + IOP13XX_TPMI_MEM_CTRL,
  139. .flags = IORESOURCE_MEM,
  140. },
  141. [IOP13XX_TPMI_RESOURCE_IRQ] = {
  142. .start = IRQ_IOP13XX_TPMI3_OUT,
  143. .end = IRQ_IOP13XX_TPMI3_OUT,
  144. .flags = IORESOURCE_IRQ
  145. }
  146. };
  147. u64 iop13xx_tpmi_mask = DMA_BIT_MASK(64);
  148. static struct platform_device iop13xx_tpmi_0_device = {
  149. .name = "iop-tpmi",
  150. .id = 0,
  151. .num_resources = ARRAY_SIZE(iop13xx_tpmi_0_resources),
  152. .resource = iop13xx_tpmi_0_resources,
  153. .dev = {
  154. .dma_mask = &iop13xx_tpmi_mask,
  155. .coherent_dma_mask = DMA_BIT_MASK(64),
  156. },
  157. };
  158. static struct platform_device iop13xx_tpmi_1_device = {
  159. .name = "iop-tpmi",
  160. .id = 1,
  161. .num_resources = ARRAY_SIZE(iop13xx_tpmi_1_resources),
  162. .resource = iop13xx_tpmi_1_resources,
  163. .dev = {
  164. .dma_mask = &iop13xx_tpmi_mask,
  165. .coherent_dma_mask = DMA_BIT_MASK(64),
  166. },
  167. };
  168. static struct platform_device iop13xx_tpmi_2_device = {
  169. .name = "iop-tpmi",
  170. .id = 2,
  171. .num_resources = ARRAY_SIZE(iop13xx_tpmi_2_resources),
  172. .resource = iop13xx_tpmi_2_resources,
  173. .dev = {
  174. .dma_mask = &iop13xx_tpmi_mask,
  175. .coherent_dma_mask = DMA_BIT_MASK(64),
  176. },
  177. };
  178. static struct platform_device iop13xx_tpmi_3_device = {
  179. .name = "iop-tpmi",
  180. .id = 3,
  181. .num_resources = ARRAY_SIZE(iop13xx_tpmi_3_resources),
  182. .resource = iop13xx_tpmi_3_resources,
  183. .dev = {
  184. .dma_mask = &iop13xx_tpmi_mask,
  185. .coherent_dma_mask = DMA_BIT_MASK(64),
  186. },
  187. };
  188. __init void iop13xx_add_tpmi_devices(void)
  189. {
  190. unsigned short device_id;
  191. /* tpmi's not present on iop341 or iop342 */
  192. if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
  193. /* ATUE must be present */
  194. device_id = __raw_readw(IOP13XX_ATUE_DID);
  195. else
  196. /* ATUX must be present */
  197. device_id = __raw_readw(IOP13XX_ATUX_DID);
  198. switch (device_id) {
  199. /* iop34[1|2] 0-tpmi */
  200. case 0x3380:
  201. case 0x3384:
  202. case 0x3388:
  203. case 0x338c:
  204. case 0x3382:
  205. case 0x3386:
  206. case 0x338a:
  207. case 0x338e:
  208. return;
  209. /* iop348 1-tpmi */
  210. case 0x3310:
  211. case 0x3312:
  212. case 0x3314:
  213. case 0x3318:
  214. case 0x331a:
  215. case 0x331c:
  216. case 0x33c0:
  217. case 0x33c2:
  218. case 0x33c4:
  219. case 0x33c8:
  220. case 0x33ca:
  221. case 0x33cc:
  222. case 0x33b0:
  223. case 0x33b2:
  224. case 0x33b4:
  225. case 0x33b8:
  226. case 0x33ba:
  227. case 0x33bc:
  228. case 0x3320:
  229. case 0x3322:
  230. case 0x3324:
  231. case 0x3328:
  232. case 0x332a:
  233. case 0x332c:
  234. platform_device_register(&iop13xx_tpmi_0_device);
  235. return;
  236. default:
  237. platform_device_register(&iop13xx_tpmi_0_device);
  238. platform_device_register(&iop13xx_tpmi_1_device);
  239. platform_device_register(&iop13xx_tpmi_2_device);
  240. platform_device_register(&iop13xx_tpmi_3_device);
  241. return;
  242. }
  243. }