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Atzars: lineage-20.0
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kernel_samsu...
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arch
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arm
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mach-at91
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include
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mach
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gsia18s.h

gsia18s.h 1.5 KB
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  1. /* Buttons */
    2. 

  2. #define GPIO_TRIG_NET_IN		AT91_PIN_PB21
    3. 

  3. #define GPIO_CARD_UNMOUNT_0		AT91_PIN_PB13
    4. 

  4. #define GPIO_CARD_UNMOUNT_1		AT91_PIN_PB12
    5. 

  5. #define GPIO_KEY_POWER			AT91_PIN_PA25
    6. 

  6. 

  7. /* PCF8574 0x20 GPIO - U1 on the GS_IA18-CB_V3 board */
    8. 

  8. #define GS_IA18_S_PCF_GPIO_BASE0	NR_BUILTIN_GPIO
    9. 

  9. #define PCF_GPIO_HDC_POWER		(GS_IA18_S_PCF_GPIO_BASE0 + 0)
    10. 

  10. #define PCF_GPIO_WIFI_SETUP		(GS_IA18_S_PCF_GPIO_BASE0 + 1)
    11. 

  11. #define PCF_GPIO_WIFI_ENABLE		(GS_IA18_S_PCF_GPIO_BASE0 + 2)
    12. 

  12. #define PCF_GPIO_WIFI_RESET		(GS_IA18_S_PCF_GPIO_BASE0 + 3)
    13. 

  13. #define PCF_GPIO_ETH_DETECT		4 /* this is a GPI */
    14. 

  14. #define PCF_GPIO_GPS_SETUP		(GS_IA18_S_PCF_GPIO_BASE0 + 5)
    15. 

  15. #define PCF_GPIO_GPS_STANDBY		(GS_IA18_S_PCF_GPIO_BASE0 + 6)
    16. 

  16. #define PCF_GPIO_GPS_POWER		(GS_IA18_S_PCF_GPIO_BASE0 + 7)
    17. 

  17. 

  18. /* PCF8574 0x22 GPIO - U1 on the GS_2G_OPT1-A_V0 board (Alarm) */
    19. 

  19. #define GS_IA18_S_PCF_GPIO_BASE1	(GS_IA18_S_PCF_GPIO_BASE0 + 8)
    20. 

  20. #define PCF_GPIO_ALARM1			(GS_IA18_S_PCF_GPIO_BASE1 + 0)
    21. 

  21. #define PCF_GPIO_ALARM2			(GS_IA18_S_PCF_GPIO_BASE1 + 1)
    22. 

  22. #define PCF_GPIO_ALARM3			(GS_IA18_S_PCF_GPIO_BASE1 + 2)
    23. 

  23. #define PCF_GPIO_ALARM4			(GS_IA18_S_PCF_GPIO_BASE1 + 3)
    24. 

  24. /* bits 4, 5, 6 not used */
    25. 

  25. #define PCF_GPIO_ALARM_V_RELAY_ON	(GS_IA18_S_PCF_GPIO_BASE1 + 7)
    26. 

  26. 

  27. /* PCF8574 0x24 GPIO U1 on the GS_2G-OPT23-A_V0 board (Modem) */
    28. 

  28. #define GS_IA18_S_PCF_GPIO_BASE2	(GS_IA18_S_PCF_GPIO_BASE1 + 8)
    29. 

  29. #define PCF_GPIO_MODEM_POWER		(GS_IA18_S_PCF_GPIO_BASE2 + 0)
    30. 

  30. #define PCF_GPIO_MODEM_RESET		(GS_IA18_S_PCF_GPIO_BASE2 + 3)
    31. 

  31. /* bits 1, 2, 4, 5 not used */
    32. 

  32. #define PCF_GPIO_TRX_RESET		(GS_IA18_S_PCF_GPIO_BASE2 + 6)
    33. 

  33. /* bit 7 not used */
    34. 

  34.