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at91rm9200.h

at91rm9200.h 4.1 KB
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  1. /*
    2. 

  2.  * arch/arm/mach-at91/include/mach/at91rm9200.h
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2005 Ivan Kokshaysky
    5. 

  5.  * Copyright (C) SAN People
    6. 

  6.  *
    7. 

  7.  * Common definitions.
    8. 

  8.  * Based on AT91RM9200 datasheet revision E.
    9. 

  9.  *
    10. 

  10.  * This program is free software; you can redistribute it and/or modify
    11. 

  11.  * it under the terms of the GNU General Public License as published by
    12. 

  12.  * the Free Software Foundation; either version 2 of the License, or
    13. 

  13.  * (at your option) any later version.
    14. 

  14.  */
    15. 

  15. 

  16. #ifndef AT91RM9200_H
    17. 

  17. #define AT91RM9200_H
    18. 

  18. 

  19. /*
    20. 

  20.  * Peripheral identifiers/interrupts.
    21. 

  21.  */
    22. 

  22. #define AT91RM9200_ID_PIOA	2	/* Parallel IO Controller A */
    23. 

  23. #define AT91RM9200_ID_PIOB	3	/* Parallel IO Controller B */
    24. 

  24. #define AT91RM9200_ID_PIOC	4	/* Parallel IO Controller C */
    25. 

  25. #define AT91RM9200_ID_PIOD	5	/* Parallel IO Controller D */
    26. 

  26. #define AT91RM9200_ID_US0	6	/* USART 0 */
    27. 

  27. #define AT91RM9200_ID_US1	7	/* USART 1 */
    28. 

  28. #define AT91RM9200_ID_US2	8	/* USART 2 */
    29. 

  29. #define AT91RM9200_ID_US3	9	/* USART 3 */
    30. 

  30. #define AT91RM9200_ID_MCI	10	/* Multimedia Card Interface */
    31. 

  31. #define AT91RM9200_ID_UDP	11	/* USB Device Port */
    32. 

  32. #define AT91RM9200_ID_TWI	12	/* Two-Wire Interface */
    33. 

  33. #define AT91RM9200_ID_SPI	13	/* Serial Peripheral Interface */
    34. 

  34. #define AT91RM9200_ID_SSC0	14	/* Serial Synchronous Controller 0 */
    35. 

  35. #define AT91RM9200_ID_SSC1	15	/* Serial Synchronous Controller 1 */
    36. 

  36. #define AT91RM9200_ID_SSC2	16	/* Serial Synchronous Controller 2 */
    37. 

  37. #define AT91RM9200_ID_TC0	17	/* Timer Counter 0 */
    38. 

  38. #define AT91RM9200_ID_TC1	18	/* Timer Counter 1 */
    39. 

  39. #define AT91RM9200_ID_TC2	19	/* Timer Counter 2 */
    40. 

  40. #define AT91RM9200_ID_TC3	20	/* Timer Counter 3 */
    41. 

  41. #define AT91RM9200_ID_TC4	21	/* Timer Counter 4 */
    42. 

  42. #define AT91RM9200_ID_TC5	22	/* Timer Counter 5 */
    43. 

  43. #define AT91RM9200_ID_UHP	23	/* USB Host port */
    44. 

  44. #define AT91RM9200_ID_EMAC	24	/* Ethernet MAC */
    45. 

  45. #define AT91RM9200_ID_IRQ0	25	/* Advanced Interrupt Controller (IRQ0) */
    46. 

  46. #define AT91RM9200_ID_IRQ1	26	/* Advanced Interrupt Controller (IRQ1) */
    47. 

  47. #define AT91RM9200_ID_IRQ2	27	/* Advanced Interrupt Controller (IRQ2) */
    48. 

  48. #define AT91RM9200_ID_IRQ3	28	/* Advanced Interrupt Controller (IRQ3) */
    49. 

  49. #define AT91RM9200_ID_IRQ4	29	/* Advanced Interrupt Controller (IRQ4) */
    50. 

  50. #define AT91RM9200_ID_IRQ5	30	/* Advanced Interrupt Controller (IRQ5) */
    51. 

  51. #define AT91RM9200_ID_IRQ6	31	/* Advanced Interrupt Controller (IRQ6) */
    52. 

  52. 

  53. 

  54. /*
    55. 

  55.  * Peripheral physical base addresses.
    56. 

  56.  */
    57. 

  57. #define AT91RM9200_BASE_TCB0	0xfffa0000
    58. 

  58. #define AT91RM9200_BASE_TC0	0xfffa0000
    59. 

  59. #define AT91RM9200_BASE_TC1	0xfffa0040
    60. 

  60. #define AT91RM9200_BASE_TC2	0xfffa0080
    61. 

  61. #define AT91RM9200_BASE_TCB1	0xfffa4000
    62. 

  62. #define AT91RM9200_BASE_TC3	0xfffa4000
    63. 

  63. #define AT91RM9200_BASE_TC4	0xfffa4040
    64. 

  64. #define AT91RM9200_BASE_TC5	0xfffa4080
    65. 

  65. #define AT91RM9200_BASE_UDP	0xfffb0000
    66. 

  66. #define AT91RM9200_BASE_MCI	0xfffb4000
    67. 

  67. #define AT91RM9200_BASE_TWI	0xfffb8000
    68. 

  68. #define AT91RM9200_BASE_EMAC	0xfffbc000
    69. 

  69. #define AT91RM9200_BASE_US0	0xfffc0000
    70. 

  70. #define AT91RM9200_BASE_US1	0xfffc4000
    71. 

  71. #define AT91RM9200_BASE_US2	0xfffc8000
    72. 

  72. #define AT91RM9200_BASE_US3	0xfffcc000
    73. 

  73. #define AT91RM9200_BASE_SSC0	0xfffd0000
    74. 

  74. #define AT91RM9200_BASE_SSC1	0xfffd4000
    75. 

  75. #define AT91RM9200_BASE_SSC2	0xfffd8000
    76. 

  76. #define AT91RM9200_BASE_SPI	0xfffe0000
    77. 

  77. 

  78. 

  79. /*
    80. 

  80.  * System Peripherals
    81. 

  81.  */
    82. 

  82. #define AT91RM9200_BASE_DBGU	AT91_BASE_DBGU0	/* Debug Unit */
    83. 

  83. #define AT91RM9200_BASE_PIOA	0xfffff400	/* PIO Controller A */
    84. 

  84. #define AT91RM9200_BASE_PIOB	0xfffff600	/* PIO Controller B */
    85. 

  85. #define AT91RM9200_BASE_PIOC	0xfffff800	/* PIO Controller C */
    86. 

  86. #define AT91RM9200_BASE_PIOD	0xfffffa00	/* PIO Controller D */
    87. 

  87. #define AT91RM9200_BASE_ST	0xfffffd00	/* System Timer */
    88. 

  88. #define AT91RM9200_BASE_RTC	0xfffffe00	/* Real-Time Clock */
    89. 

  89. #define AT91RM9200_BASE_MC	0xffffff00	/* Memory Controllers */
    90. 

  90. 

  91. #define AT91_USART0	AT91RM9200_BASE_US0
    92. 

  92. #define AT91_USART1	AT91RM9200_BASE_US1
    93. 

  93. #define AT91_USART2	AT91RM9200_BASE_US2
    94. 

  94. #define AT91_USART3	AT91RM9200_BASE_US3
    95. 

  95. 

  96. /*
    97. 

  97.  * Internal Memory.
    98. 

  98.  */
    99. 

  99. #define AT91RM9200_ROM_BASE	0x00100000	/* Internal ROM base address */
    100. 

  100. #define AT91RM9200_ROM_SIZE	SZ_128K		/* Internal ROM size (128Kb) */
    101. 

  101. 

  102. #define AT91RM9200_SRAM_BASE	0x00200000	/* Internal SRAM base address */
    103. 

  103. #define AT91RM9200_SRAM_SIZE	SZ_16K		/* Internal SRAM size (16Kb) */
    104. 

  104. 

  105. #define AT91RM9200_UHP_BASE	0x00300000	/* USB Host controller */
    106. 

  106. 

  107. 

  108. #endif
    109. 

  109.