consistent.c 6.4 KB

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  1. /*
  2. * Microblaze support for cache consistent memory.
  3. * Copyright (C) 2010 Michal Simek <monstr@monstr.eu>
  4. * Copyright (C) 2010 PetaLogix
  5. * Copyright (C) 2005 John Williams <jwilliams@itee.uq.edu.au>
  6. *
  7. * Based on PowerPC version derived from arch/arm/mm/consistent.c
  8. * Copyright (C) 2001 Dan Malek (dmalek@jlc.net)
  9. * Copyright (C) 2000 Russell King
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/module.h>
  16. #include <linux/signal.h>
  17. #include <linux/sched.h>
  18. #include <linux/kernel.h>
  19. #include <linux/errno.h>
  20. #include <linux/string.h>
  21. #include <linux/types.h>
  22. #include <linux/ptrace.h>
  23. #include <linux/mman.h>
  24. #include <linux/mm.h>
  25. #include <linux/swap.h>
  26. #include <linux/stddef.h>
  27. #include <linux/vmalloc.h>
  28. #include <linux/init.h>
  29. #include <linux/delay.h>
  30. #include <linux/bootmem.h>
  31. #include <linux/highmem.h>
  32. #include <linux/pci.h>
  33. #include <linux/interrupt.h>
  34. #include <linux/gfp.h>
  35. #include <asm/pgalloc.h>
  36. #include <linux/io.h>
  37. #include <linux/hardirq.h>
  38. #include <asm/mmu_context.h>
  39. #include <asm/mmu.h>
  40. #include <linux/uaccess.h>
  41. #include <asm/pgtable.h>
  42. #include <asm/cpuinfo.h>
  43. #include <asm/tlbflush.h>
  44. #ifndef CONFIG_MMU
  45. /* I have to use dcache values because I can't relate on ram size */
  46. # define UNCACHED_SHADOW_MASK (cpuinfo.dcache_high - cpuinfo.dcache_base + 1)
  47. #endif
  48. /*
  49. * Consistent memory allocators. Used for DMA devices that want to
  50. * share uncached memory with the processor core.
  51. * My crufty no-MMU approach is simple. In the HW platform we can optionally
  52. * mirror the DDR up above the processor cacheable region. So, memory accessed
  53. * in this mirror region will not be cached. It's alloced from the same
  54. * pool as normal memory, but the handle we return is shifted up into the
  55. * uncached region. This will no doubt cause big problems if memory allocated
  56. * here is not also freed properly. -- JW
  57. */
  58. void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle)
  59. {
  60. unsigned long order, vaddr;
  61. void *ret;
  62. unsigned int i, err = 0;
  63. struct page *page, *end;
  64. #ifdef CONFIG_MMU
  65. phys_addr_t pa;
  66. struct vm_struct *area;
  67. unsigned long va;
  68. #endif
  69. if (in_interrupt())
  70. BUG();
  71. /* Only allocate page size areas. */
  72. size = PAGE_ALIGN(size);
  73. order = get_order(size);
  74. vaddr = __get_free_pages(gfp, order);
  75. if (!vaddr)
  76. return NULL;
  77. /*
  78. * we need to ensure that there are no cachelines in use,
  79. * or worse dirty in this area.
  80. */
  81. flush_dcache_range(virt_to_phys((void *)vaddr),
  82. virt_to_phys((void *)vaddr) + size);
  83. #ifndef CONFIG_MMU
  84. ret = (void *)vaddr;
  85. /*
  86. * Here's the magic! Note if the uncached shadow is not implemented,
  87. * it's up to the calling code to also test that condition and make
  88. * other arranegments, such as manually flushing the cache and so on.
  89. */
  90. # ifdef CONFIG_XILINX_UNCACHED_SHADOW
  91. ret = (void *)((unsigned) ret | UNCACHED_SHADOW_MASK);
  92. # endif
  93. if ((unsigned int)ret > cpuinfo.dcache_base &&
  94. (unsigned int)ret < cpuinfo.dcache_high)
  95. printk(KERN_WARNING
  96. "ERROR: Your cache coherent area is CACHED!!!\n");
  97. /* dma_handle is same as physical (shadowed) address */
  98. *dma_handle = (dma_addr_t)ret;
  99. #else
  100. /* Allocate some common virtual space to map the new pages. */
  101. area = get_vm_area(size, VM_ALLOC);
  102. if (!area) {
  103. free_pages(vaddr, order);
  104. return NULL;
  105. }
  106. va = (unsigned long) area->addr;
  107. ret = (void *)va;
  108. /* This gives us the real physical address of the first page. */
  109. *dma_handle = pa = virt_to_bus((void *)vaddr);
  110. #endif
  111. /*
  112. * free wasted pages. We skip the first page since we know
  113. * that it will have count = 1 and won't require freeing.
  114. * We also mark the pages in use as reserved so that
  115. * remap_page_range works.
  116. */
  117. page = virt_to_page(vaddr);
  118. end = page + (1 << order);
  119. split_page(page, order);
  120. for (i = 0; i < size && err == 0; i += PAGE_SIZE) {
  121. #ifdef CONFIG_MMU
  122. /* MS: This is the whole magic - use cache inhibit pages */
  123. err = map_page(va + i, pa + i, _PAGE_KERNEL | _PAGE_NO_CACHE);
  124. #endif
  125. SetPageReserved(page);
  126. page++;
  127. }
  128. /* Free the otherwise unused pages. */
  129. while (page < end) {
  130. __free_page(page);
  131. page++;
  132. }
  133. if (err) {
  134. free_pages(vaddr, order);
  135. return NULL;
  136. }
  137. return ret;
  138. }
  139. EXPORT_SYMBOL(consistent_alloc);
  140. /*
  141. * free page(s) as defined by the above mapping.
  142. */
  143. void consistent_free(size_t size, void *vaddr)
  144. {
  145. struct page *page;
  146. if (in_interrupt())
  147. BUG();
  148. size = PAGE_ALIGN(size);
  149. #ifndef CONFIG_MMU
  150. /* Clear SHADOW_MASK bit in address, and free as per usual */
  151. # ifdef CONFIG_XILINX_UNCACHED_SHADOW
  152. vaddr = (void *)((unsigned)vaddr & ~UNCACHED_SHADOW_MASK);
  153. # endif
  154. page = virt_to_page(vaddr);
  155. do {
  156. ClearPageReserved(page);
  157. __free_page(page);
  158. page++;
  159. } while (size -= PAGE_SIZE);
  160. #else
  161. do {
  162. pte_t *ptep;
  163. unsigned long pfn;
  164. ptep = pte_offset_kernel(pmd_offset(pgd_offset_k(
  165. (unsigned int)vaddr),
  166. (unsigned int)vaddr),
  167. (unsigned int)vaddr);
  168. if (!pte_none(*ptep) && pte_present(*ptep)) {
  169. pfn = pte_pfn(*ptep);
  170. pte_clear(&init_mm, (unsigned int)vaddr, ptep);
  171. if (pfn_valid(pfn)) {
  172. page = pfn_to_page(pfn);
  173. ClearPageReserved(page);
  174. __free_page(page);
  175. }
  176. }
  177. vaddr += PAGE_SIZE;
  178. } while (size -= PAGE_SIZE);
  179. /* flush tlb */
  180. flush_tlb_all();
  181. #endif
  182. }
  183. EXPORT_SYMBOL(consistent_free);
  184. /*
  185. * make an area consistent.
  186. */
  187. void consistent_sync(void *vaddr, size_t size, int direction)
  188. {
  189. unsigned long start;
  190. unsigned long end;
  191. start = (unsigned long)vaddr;
  192. /* Convert start address back down to unshadowed memory region */
  193. #ifdef CONFIG_XILINX_UNCACHED_SHADOW
  194. start &= ~UNCACHED_SHADOW_MASK;
  195. #endif
  196. end = start + size;
  197. switch (direction) {
  198. case PCI_DMA_NONE:
  199. BUG();
  200. case PCI_DMA_FROMDEVICE: /* invalidate only */
  201. invalidate_dcache_range(start, end);
  202. break;
  203. case PCI_DMA_TODEVICE: /* writeback only */
  204. flush_dcache_range(start, end);
  205. break;
  206. case PCI_DMA_BIDIRECTIONAL: /* writeback and invalidate */
  207. flush_dcache_range(start, end);
  208. break;
  209. }
  210. }
  211. EXPORT_SYMBOL(consistent_sync);
  212. /*
  213. * consistent_sync_page makes memory consistent. identical
  214. * to consistent_sync, but takes a struct page instead of a
  215. * virtual address
  216. */
  217. void consistent_sync_page(struct page *page, unsigned long offset,
  218. size_t size, int direction)
  219. {
  220. unsigned long start = (unsigned long)page_address(page) + offset;
  221. consistent_sync((void *)start, size, direction);
  222. }
  223. EXPORT_SYMBOL(consistent_sync_page);