ar7_wdt.c 8.3 KB

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  1. /*
  2. * drivers/watchdog/ar7_wdt.c
  3. *
  4. * Copyright (C) 2007 Nicolas Thill <nico@openwrt.org>
  5. * Copyright (c) 2005 Enrik Berkhan <Enrik.Berkhan@akk.org>
  6. *
  7. * Some code taken from:
  8. * National Semiconductor SCx200 Watchdog support
  9. * Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  24. */
  25. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  26. #include <linux/module.h>
  27. #include <linux/moduleparam.h>
  28. #include <linux/errno.h>
  29. #include <linux/init.h>
  30. #include <linux/miscdevice.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/watchdog.h>
  33. #include <linux/fs.h>
  34. #include <linux/ioport.h>
  35. #include <linux/io.h>
  36. #include <linux/uaccess.h>
  37. #include <linux/clk.h>
  38. #include <asm/addrspace.h>
  39. #include <asm/mach-ar7/ar7.h>
  40. #define LONGNAME "TI AR7 Watchdog Timer"
  41. MODULE_AUTHOR("Nicolas Thill <nico@openwrt.org>");
  42. MODULE_DESCRIPTION(LONGNAME);
  43. MODULE_LICENSE("GPL");
  44. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  45. static int margin = 60;
  46. module_param(margin, int, 0);
  47. MODULE_PARM_DESC(margin, "Watchdog margin in seconds");
  48. static bool nowayout = WATCHDOG_NOWAYOUT;
  49. module_param(nowayout, bool, 0);
  50. MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close");
  51. #define READ_REG(x) readl((void __iomem *)&(x))
  52. #define WRITE_REG(x, v) writel((v), (void __iomem *)&(x))
  53. struct ar7_wdt {
  54. u32 kick_lock;
  55. u32 kick;
  56. u32 change_lock;
  57. u32 change;
  58. u32 disable_lock;
  59. u32 disable;
  60. u32 prescale_lock;
  61. u32 prescale;
  62. };
  63. static unsigned long wdt_is_open;
  64. static unsigned expect_close;
  65. static DEFINE_SPINLOCK(wdt_lock);
  66. /* XXX currently fixed, allows max margin ~68.72 secs */
  67. #define prescale_value 0xffff
  68. /* Resource of the WDT registers */
  69. static struct resource *ar7_regs_wdt;
  70. /* Pointer to the remapped WDT IO space */
  71. static struct ar7_wdt *ar7_wdt;
  72. static struct clk *vbus_clk;
  73. static void ar7_wdt_kick(u32 value)
  74. {
  75. WRITE_REG(ar7_wdt->kick_lock, 0x5555);
  76. if ((READ_REG(ar7_wdt->kick_lock) & 3) == 1) {
  77. WRITE_REG(ar7_wdt->kick_lock, 0xaaaa);
  78. if ((READ_REG(ar7_wdt->kick_lock) & 3) == 3) {
  79. WRITE_REG(ar7_wdt->kick, value);
  80. return;
  81. }
  82. }
  83. pr_err("failed to unlock WDT kick reg\n");
  84. }
  85. static void ar7_wdt_prescale(u32 value)
  86. {
  87. WRITE_REG(ar7_wdt->prescale_lock, 0x5a5a);
  88. if ((READ_REG(ar7_wdt->prescale_lock) & 3) == 1) {
  89. WRITE_REG(ar7_wdt->prescale_lock, 0xa5a5);
  90. if ((READ_REG(ar7_wdt->prescale_lock) & 3) == 3) {
  91. WRITE_REG(ar7_wdt->prescale, value);
  92. return;
  93. }
  94. }
  95. pr_err("failed to unlock WDT prescale reg\n");
  96. }
  97. static void ar7_wdt_change(u32 value)
  98. {
  99. WRITE_REG(ar7_wdt->change_lock, 0x6666);
  100. if ((READ_REG(ar7_wdt->change_lock) & 3) == 1) {
  101. WRITE_REG(ar7_wdt->change_lock, 0xbbbb);
  102. if ((READ_REG(ar7_wdt->change_lock) & 3) == 3) {
  103. WRITE_REG(ar7_wdt->change, value);
  104. return;
  105. }
  106. }
  107. pr_err("failed to unlock WDT change reg\n");
  108. }
  109. static void ar7_wdt_disable(u32 value)
  110. {
  111. WRITE_REG(ar7_wdt->disable_lock, 0x7777);
  112. if ((READ_REG(ar7_wdt->disable_lock) & 3) == 1) {
  113. WRITE_REG(ar7_wdt->disable_lock, 0xcccc);
  114. if ((READ_REG(ar7_wdt->disable_lock) & 3) == 2) {
  115. WRITE_REG(ar7_wdt->disable_lock, 0xdddd);
  116. if ((READ_REG(ar7_wdt->disable_lock) & 3) == 3) {
  117. WRITE_REG(ar7_wdt->disable, value);
  118. return;
  119. }
  120. }
  121. }
  122. pr_err("failed to unlock WDT disable reg\n");
  123. }
  124. static void ar7_wdt_update_margin(int new_margin)
  125. {
  126. u32 change;
  127. u32 vbus_rate;
  128. vbus_rate = clk_get_rate(vbus_clk);
  129. change = new_margin * (vbus_rate / prescale_value);
  130. if (change < 1)
  131. change = 1;
  132. if (change > 0xffff)
  133. change = 0xffff;
  134. ar7_wdt_change(change);
  135. margin = change * prescale_value / vbus_rate;
  136. pr_info("timer margin %d seconds (prescale %d, change %d, freq %d)\n",
  137. margin, prescale_value, change, vbus_rate);
  138. }
  139. static void ar7_wdt_enable_wdt(void)
  140. {
  141. pr_debug("enabling watchdog timer\n");
  142. ar7_wdt_disable(1);
  143. ar7_wdt_kick(1);
  144. }
  145. static void ar7_wdt_disable_wdt(void)
  146. {
  147. pr_debug("disabling watchdog timer\n");
  148. ar7_wdt_disable(0);
  149. }
  150. static int ar7_wdt_open(struct inode *inode, struct file *file)
  151. {
  152. /* only allow one at a time */
  153. if (test_and_set_bit(0, &wdt_is_open))
  154. return -EBUSY;
  155. ar7_wdt_enable_wdt();
  156. expect_close = 0;
  157. return nonseekable_open(inode, file);
  158. }
  159. static int ar7_wdt_release(struct inode *inode, struct file *file)
  160. {
  161. if (!expect_close)
  162. pr_warn("watchdog device closed unexpectedly, will not disable the watchdog timer\n");
  163. else if (!nowayout)
  164. ar7_wdt_disable_wdt();
  165. clear_bit(0, &wdt_is_open);
  166. return 0;
  167. }
  168. static ssize_t ar7_wdt_write(struct file *file, const char *data,
  169. size_t len, loff_t *ppos)
  170. {
  171. /* check for a magic close character */
  172. if (len) {
  173. size_t i;
  174. spin_lock(&wdt_lock);
  175. ar7_wdt_kick(1);
  176. spin_unlock(&wdt_lock);
  177. expect_close = 0;
  178. for (i = 0; i < len; ++i) {
  179. char c;
  180. if (get_user(c, data + i))
  181. return -EFAULT;
  182. if (c == 'V')
  183. expect_close = 1;
  184. }
  185. }
  186. return len;
  187. }
  188. static long ar7_wdt_ioctl(struct file *file,
  189. unsigned int cmd, unsigned long arg)
  190. {
  191. static const struct watchdog_info ident = {
  192. .identity = LONGNAME,
  193. .firmware_version = 1,
  194. .options = (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
  195. WDIOF_MAGICCLOSE),
  196. };
  197. int new_margin;
  198. switch (cmd) {
  199. case WDIOC_GETSUPPORT:
  200. if (copy_to_user((struct watchdog_info *)arg, &ident,
  201. sizeof(ident)))
  202. return -EFAULT;
  203. return 0;
  204. case WDIOC_GETSTATUS:
  205. case WDIOC_GETBOOTSTATUS:
  206. if (put_user(0, (int *)arg))
  207. return -EFAULT;
  208. return 0;
  209. case WDIOC_KEEPALIVE:
  210. ar7_wdt_kick(1);
  211. return 0;
  212. case WDIOC_SETTIMEOUT:
  213. if (get_user(new_margin, (int *)arg))
  214. return -EFAULT;
  215. if (new_margin < 1)
  216. return -EINVAL;
  217. spin_lock(&wdt_lock);
  218. ar7_wdt_update_margin(new_margin);
  219. ar7_wdt_kick(1);
  220. spin_unlock(&wdt_lock);
  221. case WDIOC_GETTIMEOUT:
  222. if (put_user(margin, (int *)arg))
  223. return -EFAULT;
  224. return 0;
  225. default:
  226. return -ENOTTY;
  227. }
  228. }
  229. static const struct file_operations ar7_wdt_fops = {
  230. .owner = THIS_MODULE,
  231. .write = ar7_wdt_write,
  232. .unlocked_ioctl = ar7_wdt_ioctl,
  233. .open = ar7_wdt_open,
  234. .release = ar7_wdt_release,
  235. .llseek = no_llseek,
  236. };
  237. static struct miscdevice ar7_wdt_miscdev = {
  238. .minor = WATCHDOG_MINOR,
  239. .name = "watchdog",
  240. .fops = &ar7_wdt_fops,
  241. };
  242. static int __devinit ar7_wdt_probe(struct platform_device *pdev)
  243. {
  244. int rc;
  245. ar7_regs_wdt =
  246. platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
  247. if (!ar7_regs_wdt) {
  248. pr_err("could not get registers resource\n");
  249. rc = -ENODEV;
  250. goto out;
  251. }
  252. if (!request_mem_region(ar7_regs_wdt->start,
  253. resource_size(ar7_regs_wdt), LONGNAME)) {
  254. pr_warn("watchdog I/O region busy\n");
  255. rc = -EBUSY;
  256. goto out;
  257. }
  258. ar7_wdt = ioremap(ar7_regs_wdt->start, resource_size(ar7_regs_wdt));
  259. if (!ar7_wdt) {
  260. pr_err("could not ioremap registers\n");
  261. rc = -ENXIO;
  262. goto out_mem_region;
  263. }
  264. vbus_clk = clk_get(NULL, "vbus");
  265. if (IS_ERR(vbus_clk)) {
  266. pr_err("could not get vbus clock\n");
  267. rc = PTR_ERR(vbus_clk);
  268. goto out_mem_region;
  269. }
  270. ar7_wdt_disable_wdt();
  271. ar7_wdt_prescale(prescale_value);
  272. ar7_wdt_update_margin(margin);
  273. rc = misc_register(&ar7_wdt_miscdev);
  274. if (rc) {
  275. pr_err("unable to register misc device\n");
  276. goto out_alloc;
  277. }
  278. goto out;
  279. out_alloc:
  280. iounmap(ar7_wdt);
  281. out_mem_region:
  282. release_mem_region(ar7_regs_wdt->start, resource_size(ar7_regs_wdt));
  283. out:
  284. return rc;
  285. }
  286. static int __devexit ar7_wdt_remove(struct platform_device *pdev)
  287. {
  288. misc_deregister(&ar7_wdt_miscdev);
  289. iounmap(ar7_wdt);
  290. release_mem_region(ar7_regs_wdt->start, resource_size(ar7_regs_wdt));
  291. return 0;
  292. }
  293. static void ar7_wdt_shutdown(struct platform_device *pdev)
  294. {
  295. if (!nowayout)
  296. ar7_wdt_disable_wdt();
  297. }
  298. static struct platform_driver ar7_wdt_driver = {
  299. .probe = ar7_wdt_probe,
  300. .remove = __devexit_p(ar7_wdt_remove),
  301. .shutdown = ar7_wdt_shutdown,
  302. .driver = {
  303. .owner = THIS_MODULE,
  304. .name = "ar7_wdt",
  305. },
  306. };
  307. module_platform_driver(ar7_wdt_driver);