bma255_reg.h 6.0 KB

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  1. /*
  2. * Copyright (C) 2013 Samsung Electronics. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * version 2 as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful, but
  9. * WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  11. * General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  16. * 02110-1301 USA
  17. */
  18. #ifndef _BMA255_REG_H_
  19. #define _BMA255_REG_H_
  20. /* For Mode Settings */
  21. #define BMA255_MODE_NORMAL 0
  22. #define BMA255_MODE_LOWPOWER1 1
  23. #define BMA255_MODE_SUSPEND 2
  24. #define BMA255_MODE_DEEP_SUSPEND 3
  25. #define BMA255_MODE_LOWPOWER2 4
  26. #define BMA255_MODE_STANDBY 5
  27. #define BMA255_MODE_MAX 6
  28. #define BMA255_RANGE_2G 3
  29. #define BMA255_RANGE_4G 5
  30. #define BMA255_RANGE_8G 8
  31. #define BMA255_RANGE_16G 12
  32. #define BMA255_BW_7_81HZ 0x08
  33. #define BMA255_BW_15_63HZ 0x09
  34. #define BMA255_BW_31_25HZ 0x0A
  35. #define BMA255_BW_62_50HZ 0x0B
  36. #define BMA255_BW_125HZ 0x0C
  37. #define BMA255_BW_250HZ 0x0D
  38. #define BMA255_BW_500HZ 0x0E
  39. #define BMA255_BW_1000HZ 0x0F
  40. /* Data Register */
  41. #define BMA255_CHIP_ID_REG 0x00
  42. #define BMA255_VERSION_REG 0x01
  43. #define BMA255_X_AXIS_LSB_REG 0x02
  44. #define BMA255_X_AXIS_MSB_REG 0x03
  45. #define BMA255_Y_AXIS_LSB_REG 0x04
  46. #define BMA255_Y_AXIS_MSB_REG 0x05
  47. #define BMA255_Z_AXIS_LSB_REG 0x06
  48. #define BMA255_Z_AXIS_MSB_REG 0x07
  49. /* Control Register */
  50. #define BMA255_STATUS1_REG 0x09
  51. #define BMA255_RANGE_SEL_REG 0x0F
  52. #define BMA255_BW_SEL_REG 0x10
  53. #define BMA255_MODE_CTRL_REG 0x11
  54. #define BMA255_LOW_NOISE_CTRL_REG 0x12
  55. #define BMA255_INT_ENABLE1_REG 0x16
  56. #define BMA255_INT1_PAD_SEL_REG 0x19
  57. #define BMA255_STATUS_TAP_SLOPE_REG 0x0B
  58. #define BMA255_INT_CTRL_REG 0x21
  59. #define BMA255_SLOPE_DURN_REG 0x27
  60. #define BMA255_SLOPE_THRES_REG 0x28
  61. #define BMA255_LOW_POWER_MODE__POS 6
  62. #define BMA255_LOW_POWER_MODE__LEN 1
  63. #define BMA255_LOW_POWER_MODE__MSK 0x40
  64. #define BMA255_LOW_POWER_MODE__REG BMA255_LOW_NOISE_CTRL_REG
  65. #define BMA255_MODE_CTRL__POS 5
  66. #define BMA255_MODE_CTRL__LEN 3
  67. #define BMA255_MODE_CTRL__MSK 0xE0
  68. #define BMA255_MODE_CTRL__REG BMA255_MODE_CTRL_REG
  69. #define BMA255_RANGE_SEL__POS 0
  70. #define BMA255_RANGE_SEL__LEN 4
  71. #define BMA255_RANGE_SEL__MSK 0x0F
  72. #define BMA255_RANGE_SEL__REG BMA255_RANGE_SEL_REG
  73. #define BMA255_BANDWIDTH__POS 0
  74. #define BMA255_BANDWIDTH__LEN 5
  75. #define BMA255_BANDWIDTH__MSK 0x1F
  76. #define BMA255_BANDWIDTH__REG BMA255_BW_SEL_REG
  77. #define BMA255_ACC_X_MSB__POS 0
  78. #define BMA255_ACC_X_MSB__LEN 8
  79. #define BMA255_ACC_X_MSB__MSK 0xFF
  80. #define BMA255_ACC_X_MSB__REG BMA255_X_AXIS_MSB_REG
  81. #define BMA255_ACC_Y_MSB__POS 0
  82. #define BMA255_ACC_Y_MSB__LEN 8
  83. #define BMA255_ACC_Y_MSB__MSK 0xFF
  84. #define BMA255_ACC_Y_MSB__REG BMA255_Y_AXIS_MSB_REG
  85. #define BMA255_ACC_Z_MSB__POS 0
  86. #define BMA255_ACC_Z_MSB__LEN 8
  87. #define BMA255_ACC_Z_MSB__MSK 0xFF
  88. #define BMA255_ACC_Z_MSB__REG BMA255_Z_AXIS_MSB_REG
  89. #define BMA255_ACC_X12_LSB__POS 4
  90. #define BMA255_ACC_X12_LSB__LEN 4
  91. #define BMA255_ACC_X12_LSB__MSK 0xF0
  92. #define BMA255_ACC_X12_LSB__REG BMA255_X_AXIS_LSB_REG
  93. #define BMA255_ACC_Y12_LSB__POS 4
  94. #define BMA255_ACC_Y12_LSB__LEN 4
  95. #define BMA255_ACC_Y12_LSB__MSK 0xF0
  96. #define BMA255_ACC_Y12_LSB__REG BMA255_Y_AXIS_LSB_REG
  97. #define BMA255_ACC_Z12_LSB__POS 4
  98. #define BMA255_ACC_Z12_LSB__LEN 4
  99. #define BMA255_ACC_Z12_LSB__MSK 0xF0
  100. #define BMA255_ACC_Z12_LSB__REG BMA255_Z_AXIS_LSB_REG
  101. #define BMA255_SLOPE_INT_S__POS 2
  102. #define BMA255_SLOPE_INT_S__LEN 1
  103. #define BMA255_SLOPE_INT_S__MSK 0x04
  104. #define BMA255_SLOPE_INT_S__REG BMA255_STATUS1_REG
  105. #define BMA255_EN_SLOPE_X_INT__POS 0
  106. #define BMA255_EN_SLOPE_X_INT__LEN 1
  107. #define BMA255_EN_SLOPE_X_INT__MSK 0x01
  108. #define BMA255_EN_SLOPE_X_INT__REG BMA255_INT_ENABLE1_REG
  109. #define BMA255_EN_SLOPE_Y_INT__POS 1
  110. #define BMA255_EN_SLOPE_Y_INT__LEN 1
  111. #define BMA255_EN_SLOPE_Y_INT__MSK 0x02
  112. #define BMA255_EN_SLOPE_Y_INT__REG BMA255_INT_ENABLE1_REG
  113. #define BMA255_EN_SLOPE_Z_INT__POS 2
  114. #define BMA255_EN_SLOPE_Z_INT__LEN 1
  115. #define BMA255_EN_SLOPE_Z_INT__MSK 0x04
  116. #define BMA255_EN_SLOPE_Z_INT__REG BMA255_INT_ENABLE1_REG
  117. #define BMA255_EN_INT1_PAD_SLOPE__POS 2
  118. #define BMA255_EN_INT1_PAD_SLOPE__LEN 1
  119. #define BMA255_EN_INT1_PAD_SLOPE__MSK 0x04
  120. #define BMA255_EN_INT1_PAD_SLOPE__REG BMA255_INT1_PAD_SEL_REG
  121. #define BMA255_SLOPE_DUR__POS 0
  122. #define BMA255_SLOPE_DUR__LEN 2
  123. #define BMA255_SLOPE_DUR__MSK 0x03
  124. #define BMA255_SLOPE_DUR__REG BMA255_SLOPE_DURN_REG
  125. #define BMA255_SLOPE_THRES__POS 0
  126. #define BMA255_SLOPE_THRES__LEN 8
  127. #define BMA255_SLOPE_THRES__MSK 0xFF
  128. #define BMA255_SLOPE_THRES__REG BMA255_SLOPE_THRES_REG
  129. #define BMA255_INT_MODE_SEL__POS 0
  130. #define BMA255_INT_MODE_SEL__LEN 4
  131. #define BMA255_INT_MODE_SEL__MSK 0x0F
  132. #define BMA255_INT_MODE_SEL__REG BMA255_INT_CTRL_REG
  133. #define BMA255_GET_BITSLICE(regvar, bitname)\
  134. ((regvar & bitname##__MSK) >> bitname##__POS)
  135. #define BMA255_SET_BITSLICE(regvar, bitname, val)\
  136. ((regvar & ~bitname##__MSK) | ((val<<bitname##__POS)&bitname##__MSK))
  137. #endif