mvumi.h 11 KB

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  1. /*
  2. * Marvell UMI head file
  3. *
  4. * Copyright 2011 Marvell. <jyli@marvell.com>
  5. *
  6. * This file is licensed under GPLv2.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; version 2 of the
  11. * License.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  16. * General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  21. * USA
  22. */
  23. #ifndef MVUMI_H
  24. #define MVUMI_H
  25. #define MAX_BASE_ADDRESS 6
  26. #define VER_MAJOR 1
  27. #define VER_MINOR 1
  28. #define VER_OEM 0
  29. #define VER_BUILD 1500
  30. #define MV_DRIVER_NAME "mvumi"
  31. #define PCI_VENDOR_ID_MARVELL_2 0x1b4b
  32. #define PCI_DEVICE_ID_MARVELL_MV9143 0x9143
  33. #define MVUMI_INTERNAL_CMD_WAIT_TIME 45
  34. #define IS_DMA64 (sizeof(dma_addr_t) == 8)
  35. enum mvumi_qc_result {
  36. MV_QUEUE_COMMAND_RESULT_SENT = 0,
  37. MV_QUEUE_COMMAND_RESULT_NO_RESOURCE,
  38. };
  39. enum {
  40. /*******************************************/
  41. /* ARM Mbus Registers Map */
  42. /*******************************************/
  43. CPU_MAIN_INT_CAUSE_REG = 0x20200,
  44. CPU_MAIN_IRQ_MASK_REG = 0x20204,
  45. CPU_MAIN_FIQ_MASK_REG = 0x20208,
  46. CPU_ENPOINTA_MASK_REG = 0x2020C,
  47. CPU_ENPOINTB_MASK_REG = 0x20210,
  48. INT_MAP_COMAERR = 1 << 6,
  49. INT_MAP_COMAIN = 1 << 7,
  50. INT_MAP_COMAOUT = 1 << 8,
  51. INT_MAP_COMBERR = 1 << 9,
  52. INT_MAP_COMBIN = 1 << 10,
  53. INT_MAP_COMBOUT = 1 << 11,
  54. INT_MAP_COMAINT = (INT_MAP_COMAOUT | INT_MAP_COMAERR),
  55. INT_MAP_COMBINT = (INT_MAP_COMBOUT | INT_MAP_COMBIN | INT_MAP_COMBERR),
  56. INT_MAP_DL_PCIEA2CPU = 1 << 0,
  57. INT_MAP_DL_CPU2PCIEA = 1 << 1,
  58. /***************************************/
  59. /* ARM Doorbell Registers Map */
  60. /***************************************/
  61. CPU_PCIEA_TO_ARM_DRBL_REG = 0x20400,
  62. CPU_PCIEA_TO_ARM_MASK_REG = 0x20404,
  63. CPU_ARM_TO_PCIEA_DRBL_REG = 0x20408,
  64. CPU_ARM_TO_PCIEA_MASK_REG = 0x2040C,
  65. DRBL_HANDSHAKE = 1 << 0,
  66. DRBL_SOFT_RESET = 1 << 1,
  67. DRBL_BUS_CHANGE = 1 << 2,
  68. DRBL_EVENT_NOTIFY = 1 << 3,
  69. DRBL_MU_RESET = 1 << 4,
  70. DRBL_HANDSHAKE_ISR = DRBL_HANDSHAKE,
  71. CPU_PCIEA_TO_ARM_MSG0 = 0x20430,
  72. CPU_PCIEA_TO_ARM_MSG1 = 0x20434,
  73. CPU_ARM_TO_PCIEA_MSG0 = 0x20438,
  74. CPU_ARM_TO_PCIEA_MSG1 = 0x2043C,
  75. /*******************************************/
  76. /* ARM Communication List Registers Map */
  77. /*******************************************/
  78. CLA_INB_LIST_BASEL = 0x500,
  79. CLA_INB_LIST_BASEH = 0x504,
  80. CLA_INB_AVAL_COUNT_BASEL = 0x508,
  81. CLA_INB_AVAL_COUNT_BASEH = 0x50C,
  82. CLA_INB_DESTI_LIST_BASEL = 0x510,
  83. CLA_INB_DESTI_LIST_BASEH = 0x514,
  84. CLA_INB_WRITE_POINTER = 0x518,
  85. CLA_INB_READ_POINTER = 0x51C,
  86. CLA_OUTB_LIST_BASEL = 0x530,
  87. CLA_OUTB_LIST_BASEH = 0x534,
  88. CLA_OUTB_SOURCE_LIST_BASEL = 0x538,
  89. CLA_OUTB_SOURCE_LIST_BASEH = 0x53C,
  90. CLA_OUTB_COPY_POINTER = 0x544,
  91. CLA_OUTB_READ_POINTER = 0x548,
  92. CLA_ISR_CAUSE = 0x560,
  93. CLA_ISR_MASK = 0x564,
  94. INT_MAP_MU = (INT_MAP_DL_CPU2PCIEA | INT_MAP_COMAINT),
  95. CL_POINTER_TOGGLE = 1 << 12,
  96. CLIC_IN_IRQ = 1 << 0,
  97. CLIC_OUT_IRQ = 1 << 1,
  98. CLIC_IN_ERR_IRQ = 1 << 8,
  99. CLIC_OUT_ERR_IRQ = 1 << 12,
  100. CL_SLOT_NUM_MASK = 0xFFF,
  101. /*
  102. * Command flag is the flag for the CDB command itself
  103. */
  104. /* 1-non data; 0-data command */
  105. CMD_FLAG_NON_DATA = 1 << 0,
  106. CMD_FLAG_DMA = 1 << 1,
  107. CMD_FLAG_PIO = 1 << 2,
  108. /* 1-host read data */
  109. CMD_FLAG_DATA_IN = 1 << 3,
  110. /* 1-host write data */
  111. CMD_FLAG_DATA_OUT = 1 << 4,
  112. SCSI_CMD_MARVELL_SPECIFIC = 0xE1,
  113. CDB_CORE_SHUTDOWN = 0xB,
  114. };
  115. #define APICDB0_EVENT 0xF4
  116. #define APICDB1_EVENT_GETEVENT 0
  117. #define MAX_EVENTS_RETURNED 6
  118. struct mvumi_driver_event {
  119. u32 time_stamp;
  120. u32 sequence_no;
  121. u32 event_id;
  122. u8 severity;
  123. u8 param_count;
  124. u16 device_id;
  125. u32 params[4];
  126. u8 sense_data_length;
  127. u8 Reserved1;
  128. u8 sense_data[30];
  129. };
  130. struct mvumi_event_req {
  131. unsigned char count;
  132. unsigned char reserved[3];
  133. struct mvumi_driver_event events[MAX_EVENTS_RETURNED];
  134. };
  135. struct mvumi_events_wq {
  136. struct work_struct work_q;
  137. struct mvumi_hba *mhba;
  138. unsigned int event;
  139. void *param;
  140. };
  141. #define MVUMI_MAX_SG_ENTRY 32
  142. #define SGD_EOT (1L << 27)
  143. struct mvumi_sgl {
  144. u32 baseaddr_l;
  145. u32 baseaddr_h;
  146. u32 flags;
  147. u32 size;
  148. };
  149. struct mvumi_res {
  150. struct list_head entry;
  151. dma_addr_t bus_addr;
  152. void *virt_addr;
  153. unsigned int size;
  154. unsigned short type; /* enum Resource_Type */
  155. };
  156. /* Resource type */
  157. enum resource_type {
  158. RESOURCE_CACHED_MEMORY = 0,
  159. RESOURCE_UNCACHED_MEMORY
  160. };
  161. struct mvumi_sense_data {
  162. u8 error_eode:7;
  163. u8 valid:1;
  164. u8 segment_number;
  165. u8 sense_key:4;
  166. u8 reserved:1;
  167. u8 incorrect_length:1;
  168. u8 end_of_media:1;
  169. u8 file_mark:1;
  170. u8 information[4];
  171. u8 additional_sense_length;
  172. u8 command_specific_information[4];
  173. u8 additional_sense_code;
  174. u8 additional_sense_code_qualifier;
  175. u8 field_replaceable_unit_code;
  176. u8 sense_key_specific[3];
  177. };
  178. /* Request initiator must set the status to REQ_STATUS_PENDING. */
  179. #define REQ_STATUS_PENDING 0x80
  180. struct mvumi_cmd {
  181. struct list_head queue_pointer;
  182. struct mvumi_msg_frame *frame;
  183. struct scsi_cmnd *scmd;
  184. atomic_t sync_cmd;
  185. void *data_buf;
  186. unsigned short request_id;
  187. unsigned char cmd_status;
  188. };
  189. /*
  190. * the function type of the in bound frame
  191. */
  192. #define CL_FUN_SCSI_CMD 0x1
  193. struct mvumi_msg_frame {
  194. u16 device_id;
  195. u16 tag;
  196. u8 cmd_flag;
  197. u8 req_function;
  198. u8 cdb_length;
  199. u8 sg_counts;
  200. u32 data_transfer_length;
  201. u16 request_id;
  202. u16 reserved1;
  203. u8 cdb[MAX_COMMAND_SIZE];
  204. u32 payload[1];
  205. };
  206. /*
  207. * the respond flag for data_payload of the out bound frame
  208. */
  209. #define CL_RSP_FLAG_NODATA 0x0
  210. #define CL_RSP_FLAG_SENSEDATA 0x1
  211. struct mvumi_rsp_frame {
  212. u16 device_id;
  213. u16 tag;
  214. u8 req_status;
  215. u8 rsp_flag; /* Indicates the type of Data_Payload.*/
  216. u16 request_id;
  217. u32 payload[1];
  218. };
  219. struct mvumi_ob_data {
  220. struct list_head list;
  221. unsigned char data[0];
  222. };
  223. struct version_info {
  224. u32 ver_major;
  225. u32 ver_minor;
  226. u32 ver_oem;
  227. u32 ver_build;
  228. };
  229. #define FW_MAX_DELAY 30
  230. #define MVUMI_FW_BUSY (1U << 0)
  231. #define MVUMI_FW_ATTACH (1U << 1)
  232. #define MVUMI_FW_ALLOC (1U << 2)
  233. /*
  234. * State is the state of the MU
  235. */
  236. #define FW_STATE_IDLE 0
  237. #define FW_STATE_STARTING 1
  238. #define FW_STATE_HANDSHAKING 2
  239. #define FW_STATE_STARTED 3
  240. #define FW_STATE_ABORT 4
  241. #define HANDSHAKE_SIGNATURE 0x5A5A5A5AL
  242. #define HANDSHAKE_READYSTATE 0x55AA5AA5L
  243. #define HANDSHAKE_DONESTATE 0x55AAA55AL
  244. /* HandShake Status definition */
  245. #define HS_STATUS_OK 1
  246. #define HS_STATUS_ERR 2
  247. #define HS_STATUS_INVALID 3
  248. /* HandShake State/Cmd definition */
  249. #define HS_S_START 1
  250. #define HS_S_RESET 2
  251. #define HS_S_PAGE_ADDR 3
  252. #define HS_S_QUERY_PAGE 4
  253. #define HS_S_SEND_PAGE 5
  254. #define HS_S_END 6
  255. #define HS_S_ABORT 7
  256. #define HS_PAGE_VERIFY_SIZE 128
  257. #define HS_GET_STATE(a) (a & 0xFFFF)
  258. #define HS_GET_STATUS(a) ((a & 0xFFFF0000) >> 16)
  259. #define HS_SET_STATE(a, b) (a |= (b & 0xFFFF))
  260. #define HS_SET_STATUS(a, b) (a |= ((b & 0xFFFF) << 16))
  261. /* handshake frame */
  262. struct mvumi_hs_frame {
  263. u16 size;
  264. /* host information */
  265. u8 host_type;
  266. u8 reserved_1[1];
  267. struct version_info host_ver; /* bios or driver version */
  268. /* controller information */
  269. u32 system_io_bus;
  270. u32 slot_number;
  271. u32 intr_level;
  272. u32 intr_vector;
  273. /* communication list configuration */
  274. u32 ib_baseaddr_l;
  275. u32 ib_baseaddr_h;
  276. u32 ob_baseaddr_l;
  277. u32 ob_baseaddr_h;
  278. u8 ib_entry_size;
  279. u8 ob_entry_size;
  280. u8 ob_depth;
  281. u8 ib_depth;
  282. /* system time */
  283. u64 seconds_since1970;
  284. };
  285. struct mvumi_hs_header {
  286. u8 page_code;
  287. u8 checksum;
  288. u16 frame_length;
  289. u32 frame_content[1];
  290. };
  291. /*
  292. * the page code type of the handshake header
  293. */
  294. #define HS_PAGE_FIRM_CAP 0x1
  295. #define HS_PAGE_HOST_INFO 0x2
  296. #define HS_PAGE_FIRM_CTL 0x3
  297. #define HS_PAGE_CL_INFO 0x4
  298. #define HS_PAGE_TOTAL 0x5
  299. #define HSP_SIZE(i) sizeof(struct mvumi_hs_page##i)
  300. #define HSP_MAX_SIZE ({ \
  301. int size, m1, m2; \
  302. m1 = max(HSP_SIZE(1), HSP_SIZE(3)); \
  303. m2 = max(HSP_SIZE(2), HSP_SIZE(4)); \
  304. size = max(m1, m2); \
  305. size; \
  306. })
  307. /* The format of the page code for Firmware capability */
  308. struct mvumi_hs_page1 {
  309. u8 pagecode;
  310. u8 checksum;
  311. u16 frame_length;
  312. u16 number_of_ports;
  313. u16 max_devices_support;
  314. u16 max_io_support;
  315. u16 umi_ver;
  316. u32 max_transfer_size;
  317. struct version_info fw_ver;
  318. u8 cl_in_max_entry_size;
  319. u8 cl_out_max_entry_size;
  320. u8 cl_inout_list_depth;
  321. u8 total_pages;
  322. u16 capability;
  323. u16 reserved1;
  324. };
  325. /* The format of the page code for Host information */
  326. struct mvumi_hs_page2 {
  327. u8 pagecode;
  328. u8 checksum;
  329. u16 frame_length;
  330. u8 host_type;
  331. u8 reserved[3];
  332. struct version_info host_ver;
  333. u32 system_io_bus;
  334. u32 slot_number;
  335. u32 intr_level;
  336. u32 intr_vector;
  337. u64 seconds_since1970;
  338. };
  339. /* The format of the page code for firmware control */
  340. struct mvumi_hs_page3 {
  341. u8 pagecode;
  342. u8 checksum;
  343. u16 frame_length;
  344. u16 control;
  345. u8 reserved[2];
  346. u32 host_bufferaddr_l;
  347. u32 host_bufferaddr_h;
  348. u32 host_eventaddr_l;
  349. u32 host_eventaddr_h;
  350. };
  351. struct mvumi_hs_page4 {
  352. u8 pagecode;
  353. u8 checksum;
  354. u16 frame_length;
  355. u32 ib_baseaddr_l;
  356. u32 ib_baseaddr_h;
  357. u32 ob_baseaddr_l;
  358. u32 ob_baseaddr_h;
  359. u8 ib_entry_size;
  360. u8 ob_entry_size;
  361. u8 ob_depth;
  362. u8 ib_depth;
  363. };
  364. struct mvumi_tag {
  365. unsigned short *stack;
  366. unsigned short top;
  367. unsigned short size;
  368. };
  369. struct mvumi_hba {
  370. void *base_addr[MAX_BASE_ADDRESS];
  371. void *mmio;
  372. struct list_head cmd_pool;
  373. struct Scsi_Host *shost;
  374. wait_queue_head_t int_cmd_wait_q;
  375. struct pci_dev *pdev;
  376. unsigned int unique_id;
  377. atomic_t fw_outstanding;
  378. struct mvumi_instance_template *instancet;
  379. void *ib_list;
  380. dma_addr_t ib_list_phys;
  381. void *ob_list;
  382. dma_addr_t ob_list_phys;
  383. void *ib_shadow;
  384. dma_addr_t ib_shadow_phys;
  385. void *ob_shadow;
  386. dma_addr_t ob_shadow_phys;
  387. void *handshake_page;
  388. dma_addr_t handshake_page_phys;
  389. unsigned int global_isr;
  390. unsigned int isr_status;
  391. unsigned short max_sge;
  392. unsigned short max_target_id;
  393. unsigned char *target_map;
  394. unsigned int max_io;
  395. unsigned int list_num_io;
  396. unsigned int ib_max_size;
  397. unsigned int ob_max_size;
  398. unsigned int ib_max_size_setting;
  399. unsigned int ob_max_size_setting;
  400. unsigned int max_transfer_size;
  401. unsigned char hba_total_pages;
  402. unsigned char fw_flag;
  403. unsigned char request_id_enabled;
  404. unsigned short hba_capability;
  405. unsigned short io_seq;
  406. unsigned int ib_cur_slot;
  407. unsigned int ob_cur_slot;
  408. unsigned int fw_state;
  409. struct list_head ob_data_list;
  410. struct list_head free_ob_list;
  411. struct list_head res_list;
  412. struct list_head waiting_req_list;
  413. struct mvumi_tag tag_pool;
  414. struct mvumi_cmd **tag_cmd;
  415. };
  416. struct mvumi_instance_template {
  417. void (*fire_cmd)(struct mvumi_hba *, struct mvumi_cmd *);
  418. void (*enable_intr)(void *) ;
  419. void (*disable_intr)(void *);
  420. int (*clear_intr)(void *);
  421. unsigned int (*read_fw_status_reg)(void *);
  422. };
  423. extern struct timezone sys_tz;
  424. #endif