rtc-s3c.c 17 KB

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  1. /* drivers/rtc/rtc-s3c.c
  2. *
  3. * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com/
  5. *
  6. * Copyright (c) 2004,2006 Simtec Electronics
  7. * Ben Dooks, <ben@simtec.co.uk>
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. *
  14. * S3C2410/S3C2440/S3C24XX Internal RTC Driver
  15. */
  16. #include <linux/module.h>
  17. #include <linux/fs.h>
  18. #include <linux/string.h>
  19. #include <linux/init.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/rtc.h>
  23. #include <linux/bcd.h>
  24. #include <linux/clk.h>
  25. #include <linux/log2.h>
  26. #include <linux/slab.h>
  27. #include <linux/of.h>
  28. #include <mach/hardware.h>
  29. #include <asm/uaccess.h>
  30. #include <asm/io.h>
  31. #include <asm/irq.h>
  32. #include <plat/regs-rtc.h>
  33. enum s3c_cpu_type {
  34. TYPE_S3C2410,
  35. TYPE_S3C2416,
  36. TYPE_S3C2443,
  37. TYPE_S3C64XX,
  38. };
  39. struct s3c_rtc_drv_data {
  40. int cpu_type;
  41. };
  42. /* I have yet to find an S3C implementation with more than one
  43. * of these rtc blocks in */
  44. static struct resource *s3c_rtc_mem;
  45. static struct clk *rtc_clk;
  46. static void __iomem *s3c_rtc_base;
  47. static int s3c_rtc_alarmno = NO_IRQ;
  48. static int s3c_rtc_tickno = NO_IRQ;
  49. static bool wake_en;
  50. static enum s3c_cpu_type s3c_rtc_cpu_type;
  51. static DEFINE_SPINLOCK(s3c_rtc_pie_lock);
  52. static void s3c_rtc_alarm_clk_enable(bool enable)
  53. {
  54. static DEFINE_SPINLOCK(s3c_rtc_alarm_clk_lock);
  55. static bool alarm_clk_enabled;
  56. unsigned long irq_flags;
  57. spin_lock_irqsave(&s3c_rtc_alarm_clk_lock, irq_flags);
  58. if (enable) {
  59. if (!alarm_clk_enabled) {
  60. clk_enable(rtc_clk);
  61. alarm_clk_enabled = true;
  62. }
  63. } else {
  64. if (alarm_clk_enabled) {
  65. clk_disable(rtc_clk);
  66. alarm_clk_enabled = false;
  67. }
  68. }
  69. spin_unlock_irqrestore(&s3c_rtc_alarm_clk_lock, irq_flags);
  70. }
  71. /* IRQ Handlers */
  72. static irqreturn_t s3c_rtc_alarmirq(int irq, void *id)
  73. {
  74. struct rtc_device *rdev = id;
  75. clk_enable(rtc_clk);
  76. rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF);
  77. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  78. writeb(S3C2410_INTP_ALM, s3c_rtc_base + S3C2410_INTP);
  79. clk_disable(rtc_clk);
  80. s3c_rtc_alarm_clk_enable(false);
  81. return IRQ_HANDLED;
  82. }
  83. static irqreturn_t s3c_rtc_tickirq(int irq, void *id)
  84. {
  85. struct rtc_device *rdev = id;
  86. clk_enable(rtc_clk);
  87. rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF);
  88. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  89. writeb(S3C2410_INTP_TIC, s3c_rtc_base + S3C2410_INTP);
  90. clk_disable(rtc_clk);
  91. return IRQ_HANDLED;
  92. }
  93. /* Update control registers */
  94. static int s3c_rtc_setaie(struct device *dev, unsigned int enabled)
  95. {
  96. unsigned int tmp;
  97. pr_debug("%s: aie=%d\n", __func__, enabled);
  98. clk_enable(rtc_clk);
  99. tmp = readb(s3c_rtc_base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN;
  100. if (enabled)
  101. tmp |= S3C2410_RTCALM_ALMEN;
  102. writeb(tmp, s3c_rtc_base + S3C2410_RTCALM);
  103. clk_disable(rtc_clk);
  104. s3c_rtc_alarm_clk_enable(enabled);
  105. return 0;
  106. }
  107. static int s3c_rtc_setfreq(struct device *dev, int freq)
  108. {
  109. struct platform_device *pdev = to_platform_device(dev);
  110. struct rtc_device *rtc_dev = platform_get_drvdata(pdev);
  111. unsigned int tmp = 0;
  112. int val;
  113. if (!is_power_of_2(freq))
  114. return -EINVAL;
  115. clk_enable(rtc_clk);
  116. spin_lock_irq(&s3c_rtc_pie_lock);
  117. if (s3c_rtc_cpu_type != TYPE_S3C64XX) {
  118. tmp = readb(s3c_rtc_base + S3C2410_TICNT);
  119. tmp &= S3C2410_TICNT_ENABLE;
  120. }
  121. val = (rtc_dev->max_user_freq / freq) - 1;
  122. if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) {
  123. tmp |= S3C2443_TICNT_PART(val);
  124. writel(S3C2443_TICNT1_PART(val), s3c_rtc_base + S3C2443_TICNT1);
  125. if (s3c_rtc_cpu_type == TYPE_S3C2416)
  126. writel(S3C2416_TICNT2_PART(val), s3c_rtc_base + S3C2416_TICNT2);
  127. } else {
  128. tmp |= val;
  129. }
  130. writel(tmp, s3c_rtc_base + S3C2410_TICNT);
  131. spin_unlock_irq(&s3c_rtc_pie_lock);
  132. clk_disable(rtc_clk);
  133. return 0;
  134. }
  135. /* Time read/write */
  136. static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
  137. {
  138. unsigned int have_retried = 0;
  139. void __iomem *base = s3c_rtc_base;
  140. clk_enable(rtc_clk);
  141. retry_get_time:
  142. rtc_tm->tm_min = readb(base + S3C2410_RTCMIN);
  143. rtc_tm->tm_hour = readb(base + S3C2410_RTCHOUR);
  144. rtc_tm->tm_mday = readb(base + S3C2410_RTCDATE);
  145. rtc_tm->tm_mon = readb(base + S3C2410_RTCMON);
  146. rtc_tm->tm_year = readb(base + S3C2410_RTCYEAR);
  147. rtc_tm->tm_sec = readb(base + S3C2410_RTCSEC);
  148. /* the only way to work out wether the system was mid-update
  149. * when we read it is to check the second counter, and if it
  150. * is zero, then we re-try the entire read
  151. */
  152. if (rtc_tm->tm_sec == 0 && !have_retried) {
  153. have_retried = 1;
  154. goto retry_get_time;
  155. }
  156. rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
  157. rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
  158. rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
  159. rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
  160. rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
  161. rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
  162. rtc_tm->tm_year += 100;
  163. pr_debug("read time %04d.%02d.%02d %02d:%02d:%02d\n",
  164. 1900 + rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday,
  165. rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec);
  166. rtc_tm->tm_mon -= 1;
  167. clk_disable(rtc_clk);
  168. return rtc_valid_tm(rtc_tm);
  169. }
  170. static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
  171. {
  172. void __iomem *base = s3c_rtc_base;
  173. int year = tm->tm_year - 100;
  174. pr_debug("set time %04d.%02d.%02d %02d:%02d:%02d\n",
  175. 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
  176. tm->tm_hour, tm->tm_min, tm->tm_sec);
  177. /* we get around y2k by simply not supporting it */
  178. if (year < 0 || year >= 100) {
  179. dev_err(dev, "rtc only supports 100 years\n");
  180. return -EINVAL;
  181. }
  182. clk_enable(rtc_clk);
  183. writeb(bin2bcd(tm->tm_sec), base + S3C2410_RTCSEC);
  184. writeb(bin2bcd(tm->tm_min), base + S3C2410_RTCMIN);
  185. writeb(bin2bcd(tm->tm_hour), base + S3C2410_RTCHOUR);
  186. writeb(bin2bcd(tm->tm_mday), base + S3C2410_RTCDATE);
  187. writeb(bin2bcd(tm->tm_mon + 1), base + S3C2410_RTCMON);
  188. writeb(bin2bcd(year), base + S3C2410_RTCYEAR);
  189. clk_disable(rtc_clk);
  190. return 0;
  191. }
  192. static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
  193. {
  194. struct rtc_time *alm_tm = &alrm->time;
  195. void __iomem *base = s3c_rtc_base;
  196. unsigned int alm_en;
  197. clk_enable(rtc_clk);
  198. alm_tm->tm_sec = readb(base + S3C2410_ALMSEC);
  199. alm_tm->tm_min = readb(base + S3C2410_ALMMIN);
  200. alm_tm->tm_hour = readb(base + S3C2410_ALMHOUR);
  201. alm_tm->tm_mon = readb(base + S3C2410_ALMMON);
  202. alm_tm->tm_mday = readb(base + S3C2410_ALMDATE);
  203. alm_tm->tm_year = readb(base + S3C2410_ALMYEAR);
  204. alm_en = readb(base + S3C2410_RTCALM);
  205. alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0;
  206. pr_debug("read alarm %d, %04d.%02d.%02d %02d:%02d:%02d\n",
  207. alm_en,
  208. 1900 + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday,
  209. alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec);
  210. /* decode the alarm enable field */
  211. if (alm_en & S3C2410_RTCALM_SECEN)
  212. alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec);
  213. else
  214. alm_tm->tm_sec = -1;
  215. if (alm_en & S3C2410_RTCALM_MINEN)
  216. alm_tm->tm_min = bcd2bin(alm_tm->tm_min);
  217. else
  218. alm_tm->tm_min = -1;
  219. if (alm_en & S3C2410_RTCALM_HOUREN)
  220. alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour);
  221. else
  222. alm_tm->tm_hour = -1;
  223. if (alm_en & S3C2410_RTCALM_DAYEN)
  224. alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday);
  225. else
  226. alm_tm->tm_mday = -1;
  227. if (alm_en & S3C2410_RTCALM_MONEN) {
  228. alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon);
  229. alm_tm->tm_mon -= 1;
  230. } else {
  231. alm_tm->tm_mon = -1;
  232. }
  233. if (alm_en & S3C2410_RTCALM_YEAREN)
  234. alm_tm->tm_year = bcd2bin(alm_tm->tm_year);
  235. else
  236. alm_tm->tm_year = -1;
  237. clk_disable(rtc_clk);
  238. return 0;
  239. }
  240. static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
  241. {
  242. struct rtc_time *tm = &alrm->time;
  243. void __iomem *base = s3c_rtc_base;
  244. unsigned int alrm_en;
  245. clk_enable(rtc_clk);
  246. pr_debug("s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n",
  247. alrm->enabled,
  248. 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
  249. tm->tm_hour, tm->tm_min, tm->tm_sec);
  250. alrm_en = readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN;
  251. writeb(0x00, base + S3C2410_RTCALM);
  252. if (tm->tm_sec < 60 && tm->tm_sec >= 0) {
  253. alrm_en |= S3C2410_RTCALM_SECEN;
  254. writeb(bin2bcd(tm->tm_sec), base + S3C2410_ALMSEC);
  255. }
  256. if (tm->tm_min < 60 && tm->tm_min >= 0) {
  257. alrm_en |= S3C2410_RTCALM_MINEN;
  258. writeb(bin2bcd(tm->tm_min), base + S3C2410_ALMMIN);
  259. }
  260. if (tm->tm_hour < 24 && tm->tm_hour >= 0) {
  261. alrm_en |= S3C2410_RTCALM_HOUREN;
  262. writeb(bin2bcd(tm->tm_hour), base + S3C2410_ALMHOUR);
  263. }
  264. pr_debug("setting S3C2410_RTCALM to %08x\n", alrm_en);
  265. writeb(alrm_en, base + S3C2410_RTCALM);
  266. s3c_rtc_setaie(dev, alrm->enabled);
  267. clk_disable(rtc_clk);
  268. return 0;
  269. }
  270. static int s3c_rtc_proc(struct device *dev, struct seq_file *seq)
  271. {
  272. unsigned int ticnt;
  273. clk_enable(rtc_clk);
  274. if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
  275. ticnt = readw(s3c_rtc_base + S3C2410_RTCCON);
  276. ticnt &= S3C64XX_RTCCON_TICEN;
  277. } else {
  278. ticnt = readb(s3c_rtc_base + S3C2410_TICNT);
  279. ticnt &= S3C2410_TICNT_ENABLE;
  280. }
  281. seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no");
  282. clk_disable(rtc_clk);
  283. return 0;
  284. }
  285. static const struct rtc_class_ops s3c_rtcops = {
  286. .read_time = s3c_rtc_gettime,
  287. .set_time = s3c_rtc_settime,
  288. .read_alarm = s3c_rtc_getalarm,
  289. .set_alarm = s3c_rtc_setalarm,
  290. .proc = s3c_rtc_proc,
  291. .alarm_irq_enable = s3c_rtc_setaie,
  292. };
  293. static void s3c_rtc_enable(struct platform_device *pdev, int en)
  294. {
  295. void __iomem *base = s3c_rtc_base;
  296. unsigned int tmp;
  297. if (s3c_rtc_base == NULL)
  298. return;
  299. clk_enable(rtc_clk);
  300. if (!en) {
  301. tmp = readw(base + S3C2410_RTCCON);
  302. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  303. tmp &= ~S3C64XX_RTCCON_TICEN;
  304. tmp &= ~S3C2410_RTCCON_RTCEN;
  305. writew(tmp, base + S3C2410_RTCCON);
  306. if (s3c_rtc_cpu_type != TYPE_S3C64XX) {
  307. tmp = readb(base + S3C2410_TICNT);
  308. tmp &= ~S3C2410_TICNT_ENABLE;
  309. writeb(tmp, base + S3C2410_TICNT);
  310. }
  311. } else {
  312. /* re-enable the device, and check it is ok */
  313. if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0) {
  314. dev_info(&pdev->dev, "rtc disabled, re-enabling\n");
  315. tmp = readw(base + S3C2410_RTCCON);
  316. writew(tmp | S3C2410_RTCCON_RTCEN,
  317. base + S3C2410_RTCCON);
  318. }
  319. if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)) {
  320. dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n");
  321. tmp = readw(base + S3C2410_RTCCON);
  322. writew(tmp & ~S3C2410_RTCCON_CNTSEL,
  323. base + S3C2410_RTCCON);
  324. }
  325. if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)) {
  326. dev_info(&pdev->dev, "removing RTCCON_CLKRST\n");
  327. tmp = readw(base + S3C2410_RTCCON);
  328. writew(tmp & ~S3C2410_RTCCON_CLKRST,
  329. base + S3C2410_RTCCON);
  330. }
  331. }
  332. clk_disable(rtc_clk);
  333. }
  334. static int __devexit s3c_rtc_remove(struct platform_device *dev)
  335. {
  336. struct rtc_device *rtc = platform_get_drvdata(dev);
  337. free_irq(s3c_rtc_alarmno, rtc);
  338. free_irq(s3c_rtc_tickno, rtc);
  339. platform_set_drvdata(dev, NULL);
  340. rtc_device_unregister(rtc);
  341. s3c_rtc_setaie(&dev->dev, 0);
  342. clk_put(rtc_clk);
  343. rtc_clk = NULL;
  344. iounmap(s3c_rtc_base);
  345. release_resource(s3c_rtc_mem);
  346. kfree(s3c_rtc_mem);
  347. return 0;
  348. }
  349. static const struct of_device_id s3c_rtc_dt_match[];
  350. static inline int s3c_rtc_get_driver_data(struct platform_device *pdev)
  351. {
  352. #ifdef CONFIG_OF
  353. struct s3c_rtc_drv_data *data;
  354. if (pdev->dev.of_node) {
  355. const struct of_device_id *match;
  356. match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node);
  357. data = (struct s3c_rtc_drv_data *) match->data;
  358. return data->cpu_type;
  359. }
  360. #endif
  361. return platform_get_device_id(pdev)->driver_data;
  362. }
  363. static int __devinit s3c_rtc_probe(struct platform_device *pdev)
  364. {
  365. struct rtc_device *rtc;
  366. struct rtc_time rtc_tm;
  367. struct resource *res;
  368. int ret;
  369. int tmp;
  370. pr_debug("%s: probe=%p\n", __func__, pdev);
  371. /* find the IRQs */
  372. s3c_rtc_tickno = platform_get_irq(pdev, 1);
  373. if (s3c_rtc_tickno < 0) {
  374. dev_err(&pdev->dev, "no irq for rtc tick\n");
  375. return -ENOENT;
  376. }
  377. s3c_rtc_alarmno = platform_get_irq(pdev, 0);
  378. if (s3c_rtc_alarmno < 0) {
  379. dev_err(&pdev->dev, "no irq for alarm\n");
  380. return -ENOENT;
  381. }
  382. pr_debug("s3c2410_rtc: tick irq %d, alarm irq %d\n",
  383. s3c_rtc_tickno, s3c_rtc_alarmno);
  384. /* get the memory region */
  385. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  386. if (res == NULL) {
  387. dev_err(&pdev->dev, "failed to get memory region resource\n");
  388. return -ENOENT;
  389. }
  390. s3c_rtc_mem = request_mem_region(res->start, resource_size(res),
  391. pdev->name);
  392. if (s3c_rtc_mem == NULL) {
  393. dev_err(&pdev->dev, "failed to reserve memory region\n");
  394. ret = -ENOENT;
  395. goto err_nores;
  396. }
  397. s3c_rtc_base = ioremap(res->start, resource_size(res));
  398. if (s3c_rtc_base == NULL) {
  399. dev_err(&pdev->dev, "failed ioremap()\n");
  400. ret = -EINVAL;
  401. goto err_nomap;
  402. }
  403. rtc_clk = clk_get(&pdev->dev, "rtc");
  404. if (IS_ERR(rtc_clk)) {
  405. dev_err(&pdev->dev, "failed to find rtc clock source\n");
  406. ret = PTR_ERR(rtc_clk);
  407. rtc_clk = NULL;
  408. goto err_clk;
  409. }
  410. clk_enable(rtc_clk);
  411. /* check to see if everything is setup correctly */
  412. s3c_rtc_enable(pdev, 1);
  413. pr_debug("s3c2410_rtc: RTCCON=%02x\n",
  414. readw(s3c_rtc_base + S3C2410_RTCCON));
  415. device_init_wakeup(&pdev->dev, 1);
  416. /* register RTC and exit */
  417. rtc = rtc_device_register("s3c", &pdev->dev, &s3c_rtcops,
  418. THIS_MODULE);
  419. if (IS_ERR(rtc)) {
  420. dev_err(&pdev->dev, "cannot attach rtc\n");
  421. ret = PTR_ERR(rtc);
  422. goto err_nortc;
  423. }
  424. s3c_rtc_cpu_type = s3c_rtc_get_driver_data(pdev);
  425. /* Check RTC Time */
  426. s3c_rtc_gettime(NULL, &rtc_tm);
  427. if (rtc_valid_tm(&rtc_tm)) {
  428. rtc_tm.tm_year = 100;
  429. rtc_tm.tm_mon = 0;
  430. rtc_tm.tm_mday = 1;
  431. rtc_tm.tm_hour = 0;
  432. rtc_tm.tm_min = 0;
  433. rtc_tm.tm_sec = 0;
  434. s3c_rtc_settime(NULL, &rtc_tm);
  435. dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n");
  436. }
  437. if (s3c_rtc_cpu_type != TYPE_S3C2410)
  438. rtc->max_user_freq = 32768;
  439. else
  440. rtc->max_user_freq = 128;
  441. if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) {
  442. tmp = readw(s3c_rtc_base + S3C2410_RTCCON);
  443. tmp |= S3C2443_RTCCON_TICSEL;
  444. writew(tmp, s3c_rtc_base + S3C2410_RTCCON);
  445. }
  446. platform_set_drvdata(pdev, rtc);
  447. s3c_rtc_setfreq(&pdev->dev, 1);
  448. ret = request_irq(s3c_rtc_alarmno, s3c_rtc_alarmirq,
  449. 0, "s3c2410-rtc alarm", rtc);
  450. if (ret) {
  451. dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_alarmno, ret);
  452. goto err_alarm_irq;
  453. }
  454. ret = request_irq(s3c_rtc_tickno, s3c_rtc_tickirq,
  455. 0, "s3c2410-rtc tick", rtc);
  456. if (ret) {
  457. dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_tickno, ret);
  458. free_irq(s3c_rtc_alarmno, rtc);
  459. goto err_tick_irq;
  460. }
  461. clk_disable(rtc_clk);
  462. return 0;
  463. err_tick_irq:
  464. free_irq(s3c_rtc_alarmno, rtc);
  465. err_alarm_irq:
  466. platform_set_drvdata(pdev, NULL);
  467. rtc_device_unregister(rtc);
  468. err_nortc:
  469. s3c_rtc_enable(pdev, 0);
  470. clk_disable(rtc_clk);
  471. clk_put(rtc_clk);
  472. err_clk:
  473. iounmap(s3c_rtc_base);
  474. err_nomap:
  475. release_resource(s3c_rtc_mem);
  476. err_nores:
  477. return ret;
  478. }
  479. #ifdef CONFIG_PM
  480. /* RTC Power management control */
  481. static int ticnt_save, ticnt_en_save;
  482. static int s3c_rtc_suspend(struct platform_device *pdev, pm_message_t state)
  483. {
  484. clk_enable(rtc_clk);
  485. /* save TICNT for anyone using periodic interrupts */
  486. ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT);
  487. if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
  488. ticnt_en_save = readw(s3c_rtc_base + S3C2410_RTCCON);
  489. ticnt_en_save &= S3C64XX_RTCCON_TICEN;
  490. }
  491. s3c_rtc_enable(pdev, 0);
  492. if (device_may_wakeup(&pdev->dev) && !wake_en) {
  493. if (enable_irq_wake(s3c_rtc_alarmno) == 0)
  494. wake_en = true;
  495. else
  496. dev_err(&pdev->dev, "enable_irq_wake failed\n");
  497. }
  498. clk_disable(rtc_clk);
  499. return 0;
  500. }
  501. static int s3c_rtc_resume(struct platform_device *pdev)
  502. {
  503. unsigned int tmp;
  504. clk_enable(rtc_clk);
  505. s3c_rtc_enable(pdev, 1);
  506. writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT);
  507. if (s3c_rtc_cpu_type == TYPE_S3C64XX && ticnt_en_save) {
  508. tmp = readw(s3c_rtc_base + S3C2410_RTCCON);
  509. writew(tmp | ticnt_en_save, s3c_rtc_base + S3C2410_RTCCON);
  510. }
  511. if (device_may_wakeup(&pdev->dev) && wake_en) {
  512. disable_irq_wake(s3c_rtc_alarmno);
  513. wake_en = false;
  514. }
  515. clk_disable(rtc_clk);
  516. return 0;
  517. }
  518. #else
  519. #define s3c_rtc_suspend NULL
  520. #define s3c_rtc_resume NULL
  521. #endif
  522. static struct s3c_rtc_drv_data s3c_rtc_drv_data_array[] = {
  523. [TYPE_S3C2410] = { TYPE_S3C2410 },
  524. [TYPE_S3C2416] = { TYPE_S3C2416 },
  525. [TYPE_S3C2443] = { TYPE_S3C2443 },
  526. [TYPE_S3C64XX] = { TYPE_S3C64XX },
  527. };
  528. #ifdef CONFIG_OF
  529. static const struct of_device_id s3c_rtc_dt_match[] = {
  530. {
  531. .compatible = "samsung,s3c2410-rtc",
  532. .data = &s3c_rtc_drv_data_array[TYPE_S3C2410],
  533. }, {
  534. .compatible = "samsung,s3c2416-rtc",
  535. .data = &s3c_rtc_drv_data_array[TYPE_S3C2416],
  536. }, {
  537. .compatible = "samsung,s3c2443-rtc",
  538. .data = &s3c_rtc_drv_data_array[TYPE_S3C2443],
  539. }, {
  540. .compatible = "samsung,s3c6410-rtc",
  541. .data = &s3c_rtc_drv_data_array[TYPE_S3C64XX],
  542. },
  543. {},
  544. };
  545. MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match);
  546. #else
  547. #define s3c_rtc_dt_match NULL
  548. #endif
  549. static struct platform_device_id s3c_rtc_driver_ids[] = {
  550. {
  551. .name = "s3c2410-rtc",
  552. .driver_data = TYPE_S3C2410,
  553. }, {
  554. .name = "s3c2416-rtc",
  555. .driver_data = TYPE_S3C2416,
  556. }, {
  557. .name = "s3c2443-rtc",
  558. .driver_data = TYPE_S3C2443,
  559. }, {
  560. .name = "s3c64xx-rtc",
  561. .driver_data = TYPE_S3C64XX,
  562. },
  563. { }
  564. };
  565. MODULE_DEVICE_TABLE(platform, s3c_rtc_driver_ids);
  566. static struct platform_driver s3c_rtc_driver = {
  567. .probe = s3c_rtc_probe,
  568. .remove = __devexit_p(s3c_rtc_remove),
  569. .suspend = s3c_rtc_suspend,
  570. .resume = s3c_rtc_resume,
  571. .id_table = s3c_rtc_driver_ids,
  572. .driver = {
  573. .name = "s3c-rtc",
  574. .owner = THIS_MODULE,
  575. .of_match_table = s3c_rtc_dt_match,
  576. },
  577. };
  578. module_platform_driver(s3c_rtc_driver);
  579. MODULE_DESCRIPTION("Samsung S3C RTC Driver");
  580. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
  581. MODULE_LICENSE("GPL");
  582. MODULE_ALIAS("platform:s3c2410-rtc");