rtc-jz4740.c 8.4 KB

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  1. /*
  2. * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  3. * Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
  4. * JZ4740 SoC RTC driver
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. *
  11. * You should have received a copy of the GNU General Public License along
  12. * with this program; if not, write to the Free Software Foundation, Inc.,
  13. * 675 Mass Ave, Cambridge, MA 02139, USA.
  14. *
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/rtc.h>
  20. #include <linux/slab.h>
  21. #include <linux/spinlock.h>
  22. #define JZ_REG_RTC_CTRL 0x00
  23. #define JZ_REG_RTC_SEC 0x04
  24. #define JZ_REG_RTC_SEC_ALARM 0x08
  25. #define JZ_REG_RTC_REGULATOR 0x0C
  26. #define JZ_REG_RTC_HIBERNATE 0x20
  27. #define JZ_REG_RTC_SCRATCHPAD 0x34
  28. #define JZ_RTC_CTRL_WRDY BIT(7)
  29. #define JZ_RTC_CTRL_1HZ BIT(6)
  30. #define JZ_RTC_CTRL_1HZ_IRQ BIT(5)
  31. #define JZ_RTC_CTRL_AF BIT(4)
  32. #define JZ_RTC_CTRL_AF_IRQ BIT(3)
  33. #define JZ_RTC_CTRL_AE BIT(2)
  34. #define JZ_RTC_CTRL_ENABLE BIT(0)
  35. struct jz4740_rtc {
  36. struct resource *mem;
  37. void __iomem *base;
  38. struct rtc_device *rtc;
  39. unsigned int irq;
  40. spinlock_t lock;
  41. };
  42. static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
  43. {
  44. return readl(rtc->base + reg);
  45. }
  46. static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
  47. {
  48. uint32_t ctrl;
  49. int timeout = 1000;
  50. do {
  51. ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
  52. } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
  53. return timeout ? 0 : -EIO;
  54. }
  55. static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
  56. uint32_t val)
  57. {
  58. int ret;
  59. ret = jz4740_rtc_wait_write_ready(rtc);
  60. if (ret == 0)
  61. writel(val, rtc->base + reg);
  62. return ret;
  63. }
  64. static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
  65. bool set)
  66. {
  67. int ret;
  68. unsigned long flags;
  69. uint32_t ctrl;
  70. spin_lock_irqsave(&rtc->lock, flags);
  71. ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
  72. /* Don't clear interrupt flags by accident */
  73. ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
  74. if (set)
  75. ctrl |= mask;
  76. else
  77. ctrl &= ~mask;
  78. ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
  79. spin_unlock_irqrestore(&rtc->lock, flags);
  80. return ret;
  81. }
  82. static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
  83. {
  84. struct jz4740_rtc *rtc = dev_get_drvdata(dev);
  85. uint32_t secs, secs2;
  86. int timeout = 5;
  87. /* If the seconds register is read while it is updated, it can contain a
  88. * bogus value. This can be avoided by making sure that two consecutive
  89. * reads have the same value.
  90. */
  91. secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
  92. secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
  93. while (secs != secs2 && --timeout) {
  94. secs = secs2;
  95. secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
  96. }
  97. if (timeout == 0)
  98. return -EIO;
  99. rtc_time_to_tm(secs, time);
  100. return rtc_valid_tm(time);
  101. }
  102. static int jz4740_rtc_set_mmss(struct device *dev, unsigned long secs)
  103. {
  104. struct jz4740_rtc *rtc = dev_get_drvdata(dev);
  105. return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, secs);
  106. }
  107. static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  108. {
  109. struct jz4740_rtc *rtc = dev_get_drvdata(dev);
  110. uint32_t secs;
  111. uint32_t ctrl;
  112. secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
  113. ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
  114. alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
  115. alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
  116. rtc_time_to_tm(secs, &alrm->time);
  117. return rtc_valid_tm(&alrm->time);
  118. }
  119. static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  120. {
  121. int ret;
  122. struct jz4740_rtc *rtc = dev_get_drvdata(dev);
  123. unsigned long secs;
  124. rtc_tm_to_time(&alrm->time, &secs);
  125. ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
  126. if (!ret)
  127. ret = jz4740_rtc_ctrl_set_bits(rtc,
  128. JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);
  129. return ret;
  130. }
  131. static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
  132. {
  133. struct jz4740_rtc *rtc = dev_get_drvdata(dev);
  134. return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
  135. }
  136. static struct rtc_class_ops jz4740_rtc_ops = {
  137. .read_time = jz4740_rtc_read_time,
  138. .set_mmss = jz4740_rtc_set_mmss,
  139. .read_alarm = jz4740_rtc_read_alarm,
  140. .set_alarm = jz4740_rtc_set_alarm,
  141. .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
  142. };
  143. static irqreturn_t jz4740_rtc_irq(int irq, void *data)
  144. {
  145. struct jz4740_rtc *rtc = data;
  146. uint32_t ctrl;
  147. unsigned long events = 0;
  148. ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
  149. if (ctrl & JZ_RTC_CTRL_1HZ)
  150. events |= (RTC_UF | RTC_IRQF);
  151. if (ctrl & JZ_RTC_CTRL_AF)
  152. events |= (RTC_AF | RTC_IRQF);
  153. rtc_update_irq(rtc->rtc, 1, events);
  154. jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
  155. return IRQ_HANDLED;
  156. }
  157. void jz4740_rtc_poweroff(struct device *dev)
  158. {
  159. struct jz4740_rtc *rtc = dev_get_drvdata(dev);
  160. jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
  161. }
  162. EXPORT_SYMBOL_GPL(jz4740_rtc_poweroff);
  163. static int __devinit jz4740_rtc_probe(struct platform_device *pdev)
  164. {
  165. int ret;
  166. struct jz4740_rtc *rtc;
  167. uint32_t scratchpad;
  168. rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
  169. if (!rtc)
  170. return -ENOMEM;
  171. rtc->irq = platform_get_irq(pdev, 0);
  172. if (rtc->irq < 0) {
  173. ret = -ENOENT;
  174. dev_err(&pdev->dev, "Failed to get platform irq\n");
  175. goto err_free;
  176. }
  177. rtc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  178. if (!rtc->mem) {
  179. ret = -ENOENT;
  180. dev_err(&pdev->dev, "Failed to get platform mmio memory\n");
  181. goto err_free;
  182. }
  183. rtc->mem = request_mem_region(rtc->mem->start, resource_size(rtc->mem),
  184. pdev->name);
  185. if (!rtc->mem) {
  186. ret = -EBUSY;
  187. dev_err(&pdev->dev, "Failed to request mmio memory region\n");
  188. goto err_free;
  189. }
  190. rtc->base = ioremap_nocache(rtc->mem->start, resource_size(rtc->mem));
  191. if (!rtc->base) {
  192. ret = -EBUSY;
  193. dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
  194. goto err_release_mem_region;
  195. }
  196. spin_lock_init(&rtc->lock);
  197. platform_set_drvdata(pdev, rtc);
  198. device_init_wakeup(&pdev->dev, 1);
  199. rtc->rtc = rtc_device_register(pdev->name, &pdev->dev, &jz4740_rtc_ops,
  200. THIS_MODULE);
  201. if (IS_ERR(rtc->rtc)) {
  202. ret = PTR_ERR(rtc->rtc);
  203. dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
  204. goto err_iounmap;
  205. }
  206. ret = request_irq(rtc->irq, jz4740_rtc_irq, 0,
  207. pdev->name, rtc);
  208. if (ret) {
  209. dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
  210. goto err_unregister_rtc;
  211. }
  212. scratchpad = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD);
  213. if (scratchpad != 0x12345678) {
  214. ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
  215. ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, 0);
  216. if (ret) {
  217. dev_err(&pdev->dev, "Could not write write to RTC registers\n");
  218. goto err_free_irq;
  219. }
  220. }
  221. return 0;
  222. err_free_irq:
  223. free_irq(rtc->irq, rtc);
  224. err_unregister_rtc:
  225. rtc_device_unregister(rtc->rtc);
  226. err_iounmap:
  227. platform_set_drvdata(pdev, NULL);
  228. iounmap(rtc->base);
  229. err_release_mem_region:
  230. release_mem_region(rtc->mem->start, resource_size(rtc->mem));
  231. err_free:
  232. kfree(rtc);
  233. return ret;
  234. }
  235. static int __devexit jz4740_rtc_remove(struct platform_device *pdev)
  236. {
  237. struct jz4740_rtc *rtc = platform_get_drvdata(pdev);
  238. free_irq(rtc->irq, rtc);
  239. rtc_device_unregister(rtc->rtc);
  240. iounmap(rtc->base);
  241. release_mem_region(rtc->mem->start, resource_size(rtc->mem));
  242. kfree(rtc);
  243. platform_set_drvdata(pdev, NULL);
  244. return 0;
  245. }
  246. #ifdef CONFIG_PM
  247. static int jz4740_rtc_suspend(struct device *dev)
  248. {
  249. struct jz4740_rtc *rtc = dev_get_drvdata(dev);
  250. if (device_may_wakeup(dev))
  251. enable_irq_wake(rtc->irq);
  252. return 0;
  253. }
  254. static int jz4740_rtc_resume(struct device *dev)
  255. {
  256. struct jz4740_rtc *rtc = dev_get_drvdata(dev);
  257. if (device_may_wakeup(dev))
  258. disable_irq_wake(rtc->irq);
  259. return 0;
  260. }
  261. static const struct dev_pm_ops jz4740_pm_ops = {
  262. .suspend = jz4740_rtc_suspend,
  263. .resume = jz4740_rtc_resume,
  264. };
  265. #define JZ4740_RTC_PM_OPS (&jz4740_pm_ops)
  266. #else
  267. #define JZ4740_RTC_PM_OPS NULL
  268. #endif /* CONFIG_PM */
  269. static struct platform_driver jz4740_rtc_driver = {
  270. .probe = jz4740_rtc_probe,
  271. .remove = __devexit_p(jz4740_rtc_remove),
  272. .driver = {
  273. .name = "jz4740-rtc",
  274. .owner = THIS_MODULE,
  275. .pm = JZ4740_RTC_PM_OPS,
  276. },
  277. };
  278. module_platform_driver(jz4740_rtc_driver);
  279. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  280. MODULE_LICENSE("GPL");
  281. MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
  282. MODULE_ALIAS("platform:jz4740-rtc");