pmic8901-regulator.c 28 KB

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  1. /* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/err.h>
  13. #include <linux/string.h>
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/mfd/pmic8901.h>
  17. #include <linux/regulator/driver.h>
  18. #include <linux/mfd/pm8xxx/core.h>
  19. #include <linux/regulator/pmic8901-regulator.h>
  20. #include <linux/module.h>
  21. /* Regulator types */
  22. #define REGULATOR_TYPE_LDO 0
  23. #define REGULATOR_TYPE_SMPS 1
  24. #define REGULATOR_TYPE_VS 2
  25. /* Bank select/write macros */
  26. #define REGULATOR_BANK_SEL(n) ((n) << 4)
  27. #define REGULATOR_BANK_WRITE 0x80
  28. #define LDO_TEST_BANKS 7
  29. #define REGULATOR_BANK_MASK 0xF0
  30. /* Pin mask resource register programming */
  31. #define VREG_PMR_STATE_MASK 0x60
  32. #define VREG_PMR_STATE_HPM 0x60
  33. #define VREG_PMR_STATE_LPM 0x40
  34. #define VREG_PMR_STATE_OFF 0x20
  35. #define VREG_PMR_STATE_PIN_CTRL 0x20
  36. #define VREG_PMR_MODE_ACTION_MASK 0x10
  37. #define VREG_PMR_MODE_ACTION_SLEEP 0x10
  38. #define VREG_PMR_MODE_ACTION_OFF 0x00
  39. #define VREG_PMR_MODE_PIN_MASK 0x08
  40. #define VREG_PMR_MODE_PIN_MASKED 0x08
  41. #define VREG_PMR_CTRL_PIN2_MASK 0x04
  42. #define VREG_PMR_CTRL_PIN2_MASKED 0x04
  43. #define VREG_PMR_CTRL_PIN1_MASK 0x02
  44. #define VREG_PMR_CTRL_PIN1_MASKED 0x02
  45. #define VREG_PMR_CTRL_PIN0_MASK 0x01
  46. #define VREG_PMR_CTRL_PIN0_MASKED 0x01
  47. #define VREG_PMR_PIN_CTRL_ALL_MASK 0x1F
  48. #define VREG_PMR_PIN_CTRL_ALL_MASKED 0x1F
  49. #define REGULATOR_IS_EN(pmr_reg) \
  50. ((pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_HPM || \
  51. (pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_LPM)
  52. /* FTSMPS programming */
  53. /* CTRL register */
  54. #define SMPS_VCTRL_BAND_MASK 0xC0
  55. #define SMPS_VCTRL_BAND_OFF 0x00
  56. #define SMPS_VCTRL_BAND_1 0x40
  57. #define SMPS_VCTRL_BAND_2 0x80
  58. #define SMPS_VCTRL_BAND_3 0xC0
  59. #define SMPS_VCTRL_VPROG_MASK 0x3F
  60. #define SMPS_BAND_1_UV_MIN 350000
  61. #define SMPS_BAND_1_UV_MAX 650000
  62. #define SMPS_BAND_1_UV_STEP 6250
  63. #define SMPS_BAND_2_UV_MIN 700000
  64. #define SMPS_BAND_2_UV_MAX 1400000
  65. #define SMPS_BAND_2_UV_STEP 12500
  66. #define SMPS_BAND_3_UV_SETPOINT_MIN 1500000
  67. #define SMPS_BAND_3_UV_MIN 1400000
  68. #define SMPS_BAND_3_UV_MAX 3300000
  69. #define SMPS_BAND_3_UV_STEP 50000
  70. #define SMPS_UV_MIN SMPS_BAND_1_UV_MIN
  71. #define SMPS_UV_MAX SMPS_BAND_3_UV_MAX
  72. /* PWR_CNFG register */
  73. #define SMPS_PULL_DOWN_ENABLE_MASK 0x40
  74. #define SMPS_PULL_DOWN_ENABLE 0x40
  75. /* LDO programming */
  76. /* CTRL register */
  77. #define LDO_LOCAL_ENABLE_MASK 0x80
  78. #define LDO_LOCAL_ENABLE 0x80
  79. #define LDO_PULL_DOWN_ENABLE_MASK 0x40
  80. #define LDO_PULL_DOWN_ENABLE 0x40
  81. #define LDO_CTRL_VPROG_MASK 0x1F
  82. /* TEST register bank 2 */
  83. #define LDO_TEST_VPROG_UPDATE_MASK 0x08
  84. #define LDO_TEST_RANGE_SEL_MASK 0x04
  85. #define LDO_TEST_FINE_STEP_MASK 0x02
  86. #define LDO_TEST_FINE_STEP_SHIFT 1
  87. /* TEST register bank 4 */
  88. #define LDO_TEST_RANGE_EXT_MASK 0x01
  89. /* Allowable voltage ranges */
  90. #define PLDO_LOW_UV_MIN 750000
  91. #define PLDO_LOW_UV_MAX 1537500
  92. #define PLDO_LOW_FINE_STEP_UV 12500
  93. #define PLDO_NORM_UV_MIN 1500000
  94. #define PLDO_NORM_UV_MAX 3075000
  95. #define PLDO_NORM_FINE_STEP_UV 25000
  96. #define PLDO_HIGH_UV_MIN 1750000
  97. #define PLDO_HIGH_UV_MAX 4900000
  98. #define PLDO_HIGH_FINE_STEP_UV 50000
  99. #define NLDO_UV_MIN 750000
  100. #define NLDO_UV_MAX 1537500
  101. #define NLDO_FINE_STEP_UV 12500
  102. /* VS programming */
  103. /* CTRL register */
  104. #define VS_CTRL_ENABLE_MASK 0xC0
  105. #define VS_CTRL_DISABLE 0x00
  106. #define VS_CTRL_ENABLE 0x40
  107. #define VS_CTRL_USE_PMR 0xC0
  108. #define VS_PULL_DOWN_ENABLE_MASK 0x20
  109. #define VS_PULL_DOWN_ENABLE 0x20
  110. struct pm8901_vreg {
  111. struct device *dev;
  112. struct pm8901_vreg_pdata *pdata;
  113. struct regulator_dev *rdev;
  114. int hpm_min_load;
  115. unsigned pc_vote;
  116. unsigned optimum;
  117. unsigned mode_initialized;
  118. u16 ctrl_addr;
  119. u16 pmr_addr;
  120. u16 test_addr;
  121. u16 pfm_ctrl_addr;
  122. u16 pwr_cnfg_addr;
  123. u8 type;
  124. u8 ctrl_reg;
  125. u8 pmr_reg;
  126. u8 test_reg[LDO_TEST_BANKS];
  127. u8 pfm_ctrl_reg;
  128. u8 pwr_cnfg_reg;
  129. u8 is_nmos;
  130. u8 state;
  131. };
  132. /*
  133. * These are used to compensate for the PMIC 8901 v1 FTS regulators which
  134. * output ~10% higher than the programmed set point.
  135. */
  136. #define IS_PMIC_8901_V1(rev) ((rev) == PM8XXX_REVISION_8901_1p0 || \
  137. (rev) == PM8XXX_REVISION_8901_1p1)
  138. #define PMIC_8901_V1_SCALE(uV) ((((uV) - 62100) * 23) / 25)
  139. #define PMIC_8901_V1_SCALE_INV(uV) (((uV) * 25) / 23 + 62100)
  140. /*
  141. * Band 1 of PMIC 8901 SMPS regulators only supports set points with the 3 LSB's
  142. * equal to 0. This is accomplished in the macro by truncating the bits.
  143. */
  144. #define PM8901_SMPS_BAND_1_COMPENSATE(vprog) ((vprog) & 0xF8)
  145. #define LDO(_id, _ctrl_addr, _pmr_addr, _test_addr, _is_nmos) \
  146. [_id] = { \
  147. .ctrl_addr = _ctrl_addr, \
  148. .pmr_addr = _pmr_addr, \
  149. .test_addr = _test_addr, \
  150. .type = REGULATOR_TYPE_LDO, \
  151. .is_nmos = _is_nmos, \
  152. .hpm_min_load = PM8901_VREG_LDO_300_HPM_MIN_LOAD, \
  153. }
  154. #define SMPS(_id, _ctrl_addr, _pmr_addr, _pfm_ctrl_addr, _pwr_cnfg_addr) \
  155. [_id] = { \
  156. .ctrl_addr = _ctrl_addr, \
  157. .pmr_addr = _pmr_addr, \
  158. .pfm_ctrl_addr = _pfm_ctrl_addr, \
  159. .pwr_cnfg_addr = _pwr_cnfg_addr, \
  160. .type = REGULATOR_TYPE_SMPS, \
  161. .hpm_min_load = PM8901_VREG_FTSMPS_HPM_MIN_LOAD, \
  162. }
  163. #define VS(_id, _ctrl_addr, _pmr_addr) \
  164. [_id] = { \
  165. .ctrl_addr = _ctrl_addr, \
  166. .pmr_addr = _pmr_addr, \
  167. .type = REGULATOR_TYPE_VS, \
  168. }
  169. static struct pm8901_vreg pm8901_vreg[] = {
  170. /* id ctrl pmr tst n/p */
  171. LDO(PM8901_VREG_ID_L0, 0x02F, 0x0AB, 0x030, 1),
  172. LDO(PM8901_VREG_ID_L1, 0x031, 0x0AC, 0x032, 0),
  173. LDO(PM8901_VREG_ID_L2, 0x033, 0x0AD, 0x034, 0),
  174. LDO(PM8901_VREG_ID_L3, 0x035, 0x0AE, 0x036, 0),
  175. LDO(PM8901_VREG_ID_L4, 0x037, 0x0AF, 0x038, 0),
  176. LDO(PM8901_VREG_ID_L5, 0x039, 0x0B0, 0x03A, 0),
  177. LDO(PM8901_VREG_ID_L6, 0x03B, 0x0B1, 0x03C, 0),
  178. /* id ctrl pmr pfm pwr */
  179. SMPS(PM8901_VREG_ID_S0, 0x05B, 0x0A6, 0x05C, 0x0E3),
  180. SMPS(PM8901_VREG_ID_S1, 0x06A, 0x0A7, 0x06B, 0x0EC),
  181. SMPS(PM8901_VREG_ID_S2, 0x079, 0x0A8, 0x07A, 0x0F1),
  182. SMPS(PM8901_VREG_ID_S3, 0x088, 0x0A9, 0x089, 0x0F6),
  183. SMPS(PM8901_VREG_ID_S4, 0x097, 0x0AA, 0x098, 0x0FB),
  184. /* id ctrl pmr */
  185. VS(PM8901_VREG_ID_LVS0, 0x046, 0x0B2),
  186. VS(PM8901_VREG_ID_LVS1, 0x048, 0x0B3),
  187. VS(PM8901_VREG_ID_LVS2, 0x04A, 0x0B4),
  188. VS(PM8901_VREG_ID_LVS3, 0x04C, 0x0B5),
  189. VS(PM8901_VREG_ID_MVS0, 0x052, 0x0B6),
  190. VS(PM8901_VREG_ID_USB_OTG, 0x055, 0x0B7),
  191. VS(PM8901_VREG_ID_HDMI_MVS, 0x058, 0x0B8),
  192. };
  193. static void print_write_error(struct pm8901_vreg *vreg, int rc,
  194. const char *func);
  195. static int pm8901_vreg_write(struct pm8901_vreg *vreg,
  196. u16 addr, u8 val, u8 mask, u8 *reg_save)
  197. {
  198. int rc = 0;
  199. u8 reg;
  200. reg = (*reg_save & ~mask) | (val & mask);
  201. if (reg != *reg_save)
  202. rc = pm8xxx_writeb(vreg->dev->parent, addr, reg);
  203. if (!rc)
  204. *reg_save = reg;
  205. return rc;
  206. }
  207. /* Set pin control bits based on new mode. */
  208. static int pm8901_vreg_select_pin_ctrl(struct pm8901_vreg *vreg, u8 *pmr_reg)
  209. {
  210. *pmr_reg |= VREG_PMR_PIN_CTRL_ALL_MASKED;
  211. if ((*pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_PIN_CTRL) {
  212. if (vreg->pdata->pin_fn == PM8901_VREG_PIN_FN_MODE)
  213. *pmr_reg = (*pmr_reg & ~VREG_PMR_STATE_MASK)
  214. | VREG_PMR_STATE_LPM;
  215. if (vreg->pdata->pin_ctrl & PM8901_VREG_PIN_CTRL_A0)
  216. *pmr_reg &= ~VREG_PMR_CTRL_PIN0_MASKED;
  217. if (vreg->pdata->pin_ctrl & PM8901_VREG_PIN_CTRL_A1)
  218. *pmr_reg &= ~VREG_PMR_CTRL_PIN1_MASKED;
  219. if (vreg->pdata->pin_ctrl & PM8901_VREG_PIN_CTRL_D0)
  220. *pmr_reg &= ~VREG_PMR_CTRL_PIN2_MASKED;
  221. }
  222. return 0;
  223. }
  224. static int pm8901_vreg_enable(struct regulator_dev *dev)
  225. {
  226. struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
  227. u8 val = VREG_PMR_STATE_HPM;
  228. int rc;
  229. if (!vreg->mode_initialized && vreg->pc_vote)
  230. val = VREG_PMR_STATE_PIN_CTRL;
  231. else if (vreg->optimum == REGULATOR_MODE_FAST)
  232. val = VREG_PMR_STATE_HPM;
  233. else if (vreg->pc_vote)
  234. val = VREG_PMR_STATE_PIN_CTRL;
  235. else if (vreg->optimum == REGULATOR_MODE_STANDBY)
  236. val = VREG_PMR_STATE_LPM;
  237. pm8901_vreg_select_pin_ctrl(vreg, &val);
  238. rc = pm8901_vreg_write(vreg, vreg->pmr_addr,
  239. val,
  240. VREG_PMR_STATE_MASK | VREG_PMR_PIN_CTRL_ALL_MASK,
  241. &vreg->pmr_reg);
  242. if (rc)
  243. print_write_error(vreg, rc, __func__);
  244. return rc;
  245. }
  246. static int pm8901_vreg_disable(struct regulator_dev *dev)
  247. {
  248. struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
  249. int rc;
  250. rc = pm8901_vreg_write(vreg, vreg->pmr_addr,
  251. VREG_PMR_STATE_OFF | VREG_PMR_PIN_CTRL_ALL_MASKED,
  252. VREG_PMR_STATE_MASK | VREG_PMR_PIN_CTRL_ALL_MASK,
  253. &vreg->pmr_reg);
  254. if (rc)
  255. print_write_error(vreg, rc, __func__);
  256. return rc;
  257. }
  258. /*
  259. * Cases that count as enabled:
  260. *
  261. * 1. PMR register has mode == HPM or LPM.
  262. * 2. Any pin control bits are unmasked.
  263. * 3. The regulator is an LDO and its local enable bit is set.
  264. */
  265. static int _pm8901_vreg_is_enabled(struct pm8901_vreg *vreg)
  266. {
  267. if ((vreg->type == REGULATOR_TYPE_LDO)
  268. && (vreg->ctrl_reg & LDO_LOCAL_ENABLE_MASK))
  269. return 1;
  270. else if (vreg->type == REGULATOR_TYPE_VS) {
  271. if ((vreg->ctrl_reg & VS_CTRL_ENABLE_MASK) == VS_CTRL_ENABLE)
  272. return 1;
  273. else if ((vreg->ctrl_reg & VS_CTRL_ENABLE_MASK)
  274. == VS_CTRL_DISABLE)
  275. return 0;
  276. }
  277. return REGULATOR_IS_EN(vreg->pmr_reg)
  278. || ((vreg->pmr_reg & VREG_PMR_PIN_CTRL_ALL_MASK)
  279. != VREG_PMR_PIN_CTRL_ALL_MASKED);
  280. }
  281. static int pm8901_vreg_is_enabled(struct regulator_dev *dev)
  282. {
  283. struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
  284. return _pm8901_vreg_is_enabled(vreg);
  285. }
  286. static int pm8901_ldo_disable(struct regulator_dev *dev)
  287. {
  288. struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
  289. int rc;
  290. /* Disassert local enable bit in CTRL register. */
  291. rc = pm8901_vreg_write(vreg, vreg->ctrl_addr, 0, LDO_LOCAL_ENABLE_MASK,
  292. &vreg->ctrl_reg);
  293. if (rc)
  294. print_write_error(vreg, rc, __func__);
  295. /* Disassert enable bit in PMR register. */
  296. rc = pm8901_vreg_disable(dev);
  297. return rc;
  298. }
  299. static int pm8901_pldo_set_voltage(struct pm8901_vreg *vreg, int uV)
  300. {
  301. int vmin, rc = 0;
  302. unsigned vprog, fine_step;
  303. u8 range_ext, range_sel, fine_step_reg;
  304. if (uV < PLDO_LOW_UV_MIN || uV > PLDO_HIGH_UV_MAX)
  305. return -EINVAL;
  306. if (uV < PLDO_LOW_UV_MAX + PLDO_LOW_FINE_STEP_UV) {
  307. vmin = PLDO_LOW_UV_MIN;
  308. fine_step = PLDO_LOW_FINE_STEP_UV;
  309. range_ext = 0;
  310. range_sel = LDO_TEST_RANGE_SEL_MASK;
  311. } else if (uV < PLDO_NORM_UV_MAX + PLDO_NORM_FINE_STEP_UV) {
  312. vmin = PLDO_NORM_UV_MIN;
  313. fine_step = PLDO_NORM_FINE_STEP_UV;
  314. range_ext = 0;
  315. range_sel = 0;
  316. } else {
  317. vmin = PLDO_HIGH_UV_MIN;
  318. fine_step = PLDO_HIGH_FINE_STEP_UV;
  319. range_ext = LDO_TEST_RANGE_EXT_MASK;
  320. range_sel = 0;
  321. }
  322. vprog = (uV - vmin) / fine_step;
  323. fine_step_reg = (vprog & 1) << LDO_TEST_FINE_STEP_SHIFT;
  324. vprog >>= 1;
  325. /*
  326. * Disable program voltage update if range extension, range select,
  327. * or fine step have changed and the regulator is enabled.
  328. */
  329. if (_pm8901_vreg_is_enabled(vreg) &&
  330. (((range_ext ^ vreg->test_reg[4]) & LDO_TEST_RANGE_EXT_MASK)
  331. || ((range_sel ^ vreg->test_reg[2]) & LDO_TEST_RANGE_SEL_MASK)
  332. || ((fine_step_reg ^ vreg->test_reg[2])
  333. & LDO_TEST_FINE_STEP_MASK))) {
  334. rc = pm8901_vreg_write(vreg, vreg->test_addr,
  335. REGULATOR_BANK_SEL(2) | REGULATOR_BANK_WRITE,
  336. REGULATOR_BANK_MASK | LDO_TEST_VPROG_UPDATE_MASK,
  337. &vreg->test_reg[2]);
  338. if (rc)
  339. goto bail;
  340. }
  341. /* Write new voltage. */
  342. rc = pm8901_vreg_write(vreg, vreg->ctrl_addr, vprog,
  343. LDO_CTRL_VPROG_MASK, &vreg->ctrl_reg);
  344. if (rc)
  345. goto bail;
  346. /* Write range extension. */
  347. rc = pm8901_vreg_write(vreg, vreg->test_addr,
  348. range_ext | REGULATOR_BANK_SEL(4)
  349. | REGULATOR_BANK_WRITE,
  350. LDO_TEST_RANGE_EXT_MASK | REGULATOR_BANK_MASK,
  351. &vreg->test_reg[4]);
  352. if (rc)
  353. goto bail;
  354. /* Write fine step, range select and program voltage update. */
  355. rc = pm8901_vreg_write(vreg, vreg->test_addr,
  356. fine_step_reg | range_sel | REGULATOR_BANK_SEL(2)
  357. | REGULATOR_BANK_WRITE | LDO_TEST_VPROG_UPDATE_MASK,
  358. LDO_TEST_FINE_STEP_MASK | LDO_TEST_RANGE_SEL_MASK
  359. | REGULATOR_BANK_MASK | LDO_TEST_VPROG_UPDATE_MASK,
  360. &vreg->test_reg[2]);
  361. bail:
  362. if (rc)
  363. print_write_error(vreg, rc, __func__);
  364. return rc;
  365. }
  366. static int pm8901_nldo_set_voltage(struct pm8901_vreg *vreg, int uV)
  367. {
  368. unsigned vprog, fine_step_reg;
  369. int rc;
  370. if (uV < NLDO_UV_MIN || uV > NLDO_UV_MAX)
  371. return -EINVAL;
  372. vprog = (uV - NLDO_UV_MIN) / NLDO_FINE_STEP_UV;
  373. fine_step_reg = (vprog & 1) << LDO_TEST_FINE_STEP_SHIFT;
  374. vprog >>= 1;
  375. /* Write new voltage. */
  376. rc = pm8901_vreg_write(vreg, vreg->ctrl_addr, vprog,
  377. LDO_CTRL_VPROG_MASK, &vreg->ctrl_reg);
  378. if (rc)
  379. print_write_error(vreg, rc, __func__);
  380. /* Write fine step. */
  381. rc = pm8901_vreg_write(vreg, vreg->test_addr,
  382. fine_step_reg | REGULATOR_BANK_SEL(2)
  383. | REGULATOR_BANK_WRITE | LDO_TEST_VPROG_UPDATE_MASK,
  384. LDO_TEST_FINE_STEP_MASK | REGULATOR_BANK_MASK
  385. | LDO_TEST_VPROG_UPDATE_MASK,
  386. &vreg->test_reg[2]);
  387. if (rc)
  388. print_write_error(vreg, rc, __func__);
  389. return rc;
  390. }
  391. static int pm8901_ldo_set_voltage(struct regulator_dev *dev,
  392. int min_uV, int max_uV, unsigned *selector)
  393. {
  394. struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
  395. if (vreg->is_nmos)
  396. return pm8901_nldo_set_voltage(vreg, min_uV);
  397. else
  398. return pm8901_pldo_set_voltage(vreg, min_uV);
  399. }
  400. static int pm8901_pldo_get_voltage(struct pm8901_vreg *vreg)
  401. {
  402. int vmin, fine_step;
  403. u8 range_ext, range_sel, vprog, fine_step_reg;
  404. fine_step_reg = vreg->test_reg[2] & LDO_TEST_FINE_STEP_MASK;
  405. range_sel = vreg->test_reg[2] & LDO_TEST_RANGE_SEL_MASK;
  406. range_ext = vreg->test_reg[4] & LDO_TEST_RANGE_EXT_MASK;
  407. vprog = vreg->ctrl_reg & LDO_CTRL_VPROG_MASK;
  408. vprog = (vprog << 1) | (fine_step_reg >> LDO_TEST_FINE_STEP_SHIFT);
  409. if (range_sel) {
  410. /* low range mode */
  411. fine_step = PLDO_LOW_FINE_STEP_UV;
  412. vmin = PLDO_LOW_UV_MIN;
  413. } else if (!range_ext) {
  414. /* normal mode */
  415. fine_step = PLDO_NORM_FINE_STEP_UV;
  416. vmin = PLDO_NORM_UV_MIN;
  417. } else {
  418. /* high range mode */
  419. fine_step = PLDO_HIGH_FINE_STEP_UV;
  420. vmin = PLDO_HIGH_UV_MIN;
  421. }
  422. return fine_step * vprog + vmin;
  423. }
  424. static int pm8901_nldo_get_voltage(struct pm8901_vreg *vreg)
  425. {
  426. u8 vprog, fine_step_reg;
  427. fine_step_reg = vreg->test_reg[2] & LDO_TEST_FINE_STEP_MASK;
  428. vprog = vreg->ctrl_reg & LDO_CTRL_VPROG_MASK;
  429. vprog = (vprog << 1) | (fine_step_reg >> LDO_TEST_FINE_STEP_SHIFT);
  430. return NLDO_FINE_STEP_UV * vprog + NLDO_UV_MIN;
  431. }
  432. static int pm8901_ldo_get_voltage(struct regulator_dev *dev)
  433. {
  434. struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
  435. if (vreg->is_nmos)
  436. return pm8901_nldo_get_voltage(vreg);
  437. else
  438. return pm8901_pldo_get_voltage(vreg);
  439. }
  440. /*
  441. * Optimum mode programming:
  442. * REGULATOR_MODE_FAST: Go to HPM (highest priority)
  443. * REGULATOR_MODE_STANDBY: Go to pin ctrl mode if there are any pin ctrl
  444. * votes, else go to LPM
  445. *
  446. * Pin ctrl mode voting via regulator set_mode:
  447. * REGULATOR_MODE_IDLE: Go to pin ctrl mode if the optimum mode is LPM, else
  448. * go to HPM
  449. * REGULATOR_MODE_NORMAL: Go to LPM if it is the optimum mode, else go to HPM
  450. */
  451. static int pm8901_vreg_set_mode(struct regulator_dev *dev, unsigned int mode)
  452. {
  453. struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
  454. unsigned optimum = vreg->optimum;
  455. unsigned pc_vote = vreg->pc_vote;
  456. unsigned mode_initialized = vreg->mode_initialized;
  457. u8 val = 0;
  458. int rc = 0;
  459. /* Determine new mode to go into. */
  460. switch (mode) {
  461. case REGULATOR_MODE_FAST:
  462. val = VREG_PMR_STATE_HPM;
  463. optimum = mode;
  464. mode_initialized = 1;
  465. break;
  466. case REGULATOR_MODE_STANDBY:
  467. if (pc_vote)
  468. val = VREG_PMR_STATE_PIN_CTRL;
  469. else
  470. val = VREG_PMR_STATE_LPM;
  471. optimum = mode;
  472. mode_initialized = 1;
  473. break;
  474. case REGULATOR_MODE_IDLE:
  475. if (pc_vote++)
  476. goto done; /* already taken care of */
  477. if (mode_initialized && optimum == REGULATOR_MODE_FAST)
  478. val = VREG_PMR_STATE_HPM;
  479. else
  480. val = VREG_PMR_STATE_PIN_CTRL;
  481. break;
  482. case REGULATOR_MODE_NORMAL:
  483. if (pc_vote && --pc_vote)
  484. goto done; /* already taken care of */
  485. if (optimum == REGULATOR_MODE_STANDBY)
  486. val = VREG_PMR_STATE_LPM;
  487. else
  488. val = VREG_PMR_STATE_HPM;
  489. break;
  490. default:
  491. pr_err("%s: unknown mode, mode=%u\n", __func__, mode);
  492. return -EINVAL;
  493. }
  494. /* Set pin control bits based on new mode. */
  495. pm8901_vreg_select_pin_ctrl(vreg, &val);
  496. /* Only apply mode setting to hardware if currently enabled. */
  497. if (pm8901_vreg_is_enabled(dev))
  498. rc = pm8901_vreg_write(vreg, vreg->pmr_addr, val,
  499. VREG_PMR_STATE_MASK | VREG_PMR_PIN_CTRL_ALL_MASK,
  500. &vreg->pmr_reg);
  501. if (rc) {
  502. print_write_error(vreg, rc, __func__);
  503. return rc;
  504. }
  505. done:
  506. vreg->mode_initialized = mode_initialized;
  507. vreg->optimum = optimum;
  508. vreg->pc_vote = pc_vote;
  509. return 0;
  510. }
  511. static unsigned int pm8901_vreg_get_mode(struct regulator_dev *dev)
  512. {
  513. struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
  514. int pin_mask = VREG_PMR_CTRL_PIN0_MASK | VREG_PMR_CTRL_PIN1_MASK
  515. | VREG_PMR_CTRL_PIN2_MASK;
  516. if (!vreg->mode_initialized && vreg->pc_vote)
  517. return REGULATOR_MODE_IDLE;
  518. else if (((vreg->pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_OFF)
  519. && ((vreg->pmr_reg & pin_mask) != pin_mask))
  520. return REGULATOR_MODE_IDLE;
  521. else if (((vreg->pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_LPM)
  522. && ((vreg->pmr_reg & pin_mask) != pin_mask))
  523. return REGULATOR_MODE_IDLE;
  524. else if (vreg->optimum == REGULATOR_MODE_FAST)
  525. return REGULATOR_MODE_FAST;
  526. else if (vreg->pc_vote)
  527. return REGULATOR_MODE_IDLE;
  528. else if (vreg->optimum == REGULATOR_MODE_STANDBY)
  529. return REGULATOR_MODE_STANDBY;
  530. return REGULATOR_MODE_FAST;
  531. }
  532. unsigned int pm8901_vreg_get_optimum_mode(struct regulator_dev *dev,
  533. int input_uV, int output_uV, int load_uA)
  534. {
  535. struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
  536. if (load_uA <= 0) {
  537. /*
  538. * pm8901_vreg_get_optimum_mode is being called before consumers
  539. * have specified their load currents via
  540. * regulator_set_optimum_mode. Return whatever the existing mode
  541. * is.
  542. */
  543. return pm8901_vreg_get_mode(dev);
  544. }
  545. if (load_uA >= vreg->hpm_min_load)
  546. return REGULATOR_MODE_FAST;
  547. return REGULATOR_MODE_STANDBY;
  548. }
  549. static int pm8901_smps_set_voltage(struct regulator_dev *dev,
  550. int min_uV, int max_uV, unsigned *selector)
  551. {
  552. struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
  553. int rc;
  554. u8 val, band;
  555. if (IS_PMIC_8901_V1(pm8xxx_get_revision(vreg->dev->parent)))
  556. min_uV = PMIC_8901_V1_SCALE(min_uV);
  557. if (min_uV < SMPS_BAND_1_UV_MIN || min_uV > SMPS_BAND_3_UV_MAX)
  558. return -EINVAL;
  559. /* Round down for set points in the gaps between bands. */
  560. if (min_uV > SMPS_BAND_1_UV_MAX && min_uV < SMPS_BAND_2_UV_MIN)
  561. min_uV = SMPS_BAND_1_UV_MAX;
  562. else if (min_uV > SMPS_BAND_2_UV_MAX
  563. && min_uV < SMPS_BAND_3_UV_SETPOINT_MIN)
  564. min_uV = SMPS_BAND_2_UV_MAX;
  565. if (min_uV < SMPS_BAND_2_UV_MIN) {
  566. val = ((min_uV - SMPS_BAND_1_UV_MIN) / SMPS_BAND_1_UV_STEP);
  567. val = PM8901_SMPS_BAND_1_COMPENSATE(val);
  568. band = SMPS_VCTRL_BAND_1;
  569. } else if (min_uV < SMPS_BAND_3_UV_SETPOINT_MIN) {
  570. val = ((min_uV - SMPS_BAND_2_UV_MIN) / SMPS_BAND_2_UV_STEP);
  571. band = SMPS_VCTRL_BAND_2;
  572. } else {
  573. val = ((min_uV - SMPS_BAND_3_UV_MIN) / SMPS_BAND_3_UV_STEP);
  574. band = SMPS_VCTRL_BAND_3;
  575. }
  576. rc = pm8901_vreg_write(vreg, vreg->ctrl_addr, band | val,
  577. SMPS_VCTRL_BAND_MASK | SMPS_VCTRL_VPROG_MASK,
  578. &vreg->ctrl_reg);
  579. if (rc)
  580. goto bail;
  581. rc = pm8901_vreg_write(vreg, vreg->pfm_ctrl_addr, band | val,
  582. SMPS_VCTRL_BAND_MASK | SMPS_VCTRL_VPROG_MASK,
  583. &vreg->pfm_ctrl_reg);
  584. bail:
  585. if (rc)
  586. print_write_error(vreg, rc, __func__);
  587. return rc;
  588. }
  589. static int pm8901_smps_get_voltage(struct regulator_dev *dev)
  590. {
  591. struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
  592. u8 vprog, band;
  593. int ret = 0;
  594. if ((vreg->pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_LPM) {
  595. vprog = vreg->pfm_ctrl_reg & SMPS_VCTRL_VPROG_MASK;
  596. band = vreg->pfm_ctrl_reg & SMPS_VCTRL_BAND_MASK;
  597. } else {
  598. vprog = vreg->ctrl_reg & SMPS_VCTRL_VPROG_MASK;
  599. band = vreg->ctrl_reg & SMPS_VCTRL_BAND_MASK;
  600. }
  601. if (band == SMPS_VCTRL_BAND_1)
  602. ret = vprog * SMPS_BAND_1_UV_STEP + SMPS_BAND_1_UV_MIN;
  603. else if (band == SMPS_VCTRL_BAND_2)
  604. ret = vprog * SMPS_BAND_2_UV_STEP + SMPS_BAND_2_UV_MIN;
  605. else
  606. ret = vprog * SMPS_BAND_3_UV_STEP + SMPS_BAND_3_UV_MIN;
  607. if (IS_PMIC_8901_V1(pm8xxx_get_revision(vreg->dev->parent)))
  608. ret = PMIC_8901_V1_SCALE_INV(ret);
  609. return ret;
  610. }
  611. static int pm8901_vs_enable(struct regulator_dev *dev)
  612. {
  613. struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
  614. int rc;
  615. /* Assert enable bit in PMR register. */
  616. rc = pm8901_vreg_enable(dev);
  617. /* Make sure that switch is controlled via PMR register */
  618. rc = pm8901_vreg_write(vreg, vreg->ctrl_addr, VS_CTRL_USE_PMR,
  619. VS_CTRL_ENABLE_MASK, &vreg->ctrl_reg);
  620. if (rc)
  621. print_write_error(vreg, rc, __func__);
  622. return rc;
  623. }
  624. static int pm8901_vs_disable(struct regulator_dev *dev)
  625. {
  626. struct pm8901_vreg *vreg = rdev_get_drvdata(dev);
  627. int rc;
  628. /* Disassert enable bit in PMR register. */
  629. rc = pm8901_vreg_disable(dev);
  630. /* Make sure that switch is controlled via PMR register */
  631. rc = pm8901_vreg_write(vreg, vreg->ctrl_addr, VS_CTRL_USE_PMR,
  632. VS_CTRL_ENABLE_MASK, &vreg->ctrl_reg);
  633. if (rc)
  634. print_write_error(vreg, rc, __func__);
  635. return rc;
  636. }
  637. static struct regulator_ops pm8901_ldo_ops = {
  638. .enable = pm8901_vreg_enable,
  639. .disable = pm8901_ldo_disable,
  640. .is_enabled = pm8901_vreg_is_enabled,
  641. .set_voltage = pm8901_ldo_set_voltage,
  642. .get_voltage = pm8901_ldo_get_voltage,
  643. .set_mode = pm8901_vreg_set_mode,
  644. .get_mode = pm8901_vreg_get_mode,
  645. .get_optimum_mode = pm8901_vreg_get_optimum_mode,
  646. };
  647. static struct regulator_ops pm8901_smps_ops = {
  648. .enable = pm8901_vreg_enable,
  649. .disable = pm8901_vreg_disable,
  650. .is_enabled = pm8901_vreg_is_enabled,
  651. .set_voltage = pm8901_smps_set_voltage,
  652. .get_voltage = pm8901_smps_get_voltage,
  653. .set_mode = pm8901_vreg_set_mode,
  654. .get_mode = pm8901_vreg_get_mode,
  655. .get_optimum_mode = pm8901_vreg_get_optimum_mode,
  656. };
  657. static struct regulator_ops pm8901_vs_ops = {
  658. .enable = pm8901_vs_enable,
  659. .disable = pm8901_vs_disable,
  660. .is_enabled = pm8901_vreg_is_enabled,
  661. .set_mode = pm8901_vreg_set_mode,
  662. .get_mode = pm8901_vreg_get_mode,
  663. };
  664. #define VREG_DESCRIP(_id, _name, _ops) \
  665. [_id] = { \
  666. .name = _name, \
  667. .id = _id, \
  668. .ops = _ops, \
  669. .type = REGULATOR_VOLTAGE, \
  670. .owner = THIS_MODULE, \
  671. }
  672. static struct regulator_desc pm8901_vreg_descrip[] = {
  673. VREG_DESCRIP(PM8901_VREG_ID_L0, "8901_l0", &pm8901_ldo_ops),
  674. VREG_DESCRIP(PM8901_VREG_ID_L1, "8901_l1", &pm8901_ldo_ops),
  675. VREG_DESCRIP(PM8901_VREG_ID_L2, "8901_l2", &pm8901_ldo_ops),
  676. VREG_DESCRIP(PM8901_VREG_ID_L3, "8901_l3", &pm8901_ldo_ops),
  677. VREG_DESCRIP(PM8901_VREG_ID_L4, "8901_l4", &pm8901_ldo_ops),
  678. VREG_DESCRIP(PM8901_VREG_ID_L5, "8901_l5", &pm8901_ldo_ops),
  679. VREG_DESCRIP(PM8901_VREG_ID_L6, "8901_l6", &pm8901_ldo_ops),
  680. VREG_DESCRIP(PM8901_VREG_ID_S0, "8901_s0", &pm8901_smps_ops),
  681. VREG_DESCRIP(PM8901_VREG_ID_S1, "8901_s1", &pm8901_smps_ops),
  682. VREG_DESCRIP(PM8901_VREG_ID_S2, "8901_s2", &pm8901_smps_ops),
  683. VREG_DESCRIP(PM8901_VREG_ID_S3, "8901_s3", &pm8901_smps_ops),
  684. VREG_DESCRIP(PM8901_VREG_ID_S4, "8901_s4", &pm8901_smps_ops),
  685. VREG_DESCRIP(PM8901_VREG_ID_LVS0, "8901_lvs0", &pm8901_vs_ops),
  686. VREG_DESCRIP(PM8901_VREG_ID_LVS1, "8901_lvs1", &pm8901_vs_ops),
  687. VREG_DESCRIP(PM8901_VREG_ID_LVS2, "8901_lvs2", &pm8901_vs_ops),
  688. VREG_DESCRIP(PM8901_VREG_ID_LVS3, "8901_lvs3", &pm8901_vs_ops),
  689. VREG_DESCRIP(PM8901_VREG_ID_MVS0, "8901_mvs0", &pm8901_vs_ops),
  690. VREG_DESCRIP(PM8901_VREG_ID_USB_OTG, "8901_usb_otg", &pm8901_vs_ops),
  691. VREG_DESCRIP(PM8901_VREG_ID_HDMI_MVS, "8901_hdmi_mvs", &pm8901_vs_ops),
  692. };
  693. static int pm8901_init_ldo(struct pm8901_vreg *vreg)
  694. {
  695. int rc = 0, i;
  696. u8 bank;
  697. /* Store current regulator register values. */
  698. for (i = 0; i < LDO_TEST_BANKS; i++) {
  699. bank = REGULATOR_BANK_SEL(i);
  700. rc = pm8xxx_writeb(vreg->dev->parent, vreg->test_addr, bank);
  701. if (rc)
  702. goto bail;
  703. rc = pm8xxx_readb(vreg->dev->parent, vreg->test_addr,
  704. &vreg->test_reg[i]);
  705. if (rc)
  706. goto bail;
  707. vreg->test_reg[i] |= REGULATOR_BANK_WRITE;
  708. }
  709. /* Set pull down enable based on platform data. */
  710. rc = pm8901_vreg_write(vreg, vreg->ctrl_addr,
  711. (vreg->pdata->pull_down_enable ? LDO_PULL_DOWN_ENABLE : 0),
  712. LDO_PULL_DOWN_ENABLE_MASK, &vreg->ctrl_reg);
  713. bail:
  714. return rc;
  715. }
  716. static int pm8901_init_smps(struct pm8901_vreg *vreg)
  717. {
  718. int rc;
  719. /* Store current regulator register values. */
  720. rc = pm8xxx_readb(vreg->dev->parent, vreg->pfm_ctrl_addr,
  721. &vreg->pfm_ctrl_reg);
  722. if (rc)
  723. goto bail;
  724. rc = pm8xxx_readb(vreg->dev->parent, vreg->pwr_cnfg_addr,
  725. &vreg->pwr_cnfg_reg);
  726. if (rc)
  727. goto bail;
  728. /* Set pull down enable based on platform data. */
  729. rc = pm8901_vreg_write(vreg, vreg->pwr_cnfg_addr,
  730. (vreg->pdata->pull_down_enable ? SMPS_PULL_DOWN_ENABLE : 0),
  731. SMPS_PULL_DOWN_ENABLE_MASK, &vreg->pwr_cnfg_reg);
  732. bail:
  733. return rc;
  734. }
  735. static int pm8901_init_vs(struct pm8901_vreg *vreg)
  736. {
  737. int rc = 0;
  738. /* Set pull down enable based on platform data. */
  739. rc = pm8901_vreg_write(vreg, vreg->ctrl_addr,
  740. (vreg->pdata->pull_down_enable ? VS_PULL_DOWN_ENABLE : 0),
  741. VS_PULL_DOWN_ENABLE_MASK, &vreg->ctrl_reg);
  742. return rc;
  743. }
  744. static int pm8901_init_regulator(struct pm8901_vreg *vreg)
  745. {
  746. int rc;
  747. /* Store current regulator register values. */
  748. rc = pm8xxx_readb(vreg->dev->parent, vreg->ctrl_addr, &vreg->ctrl_reg);
  749. if (rc)
  750. goto bail;
  751. rc = pm8xxx_readb(vreg->dev->parent, vreg->pmr_addr, &vreg->pmr_reg);
  752. if (rc)
  753. goto bail;
  754. /* Set initial mode based on hardware state. */
  755. if ((vreg->pmr_reg & VREG_PMR_STATE_MASK) == VREG_PMR_STATE_LPM)
  756. vreg->optimum = REGULATOR_MODE_STANDBY;
  757. else
  758. vreg->optimum = REGULATOR_MODE_FAST;
  759. vreg->mode_initialized = 0;
  760. if (vreg->type == REGULATOR_TYPE_LDO)
  761. rc = pm8901_init_ldo(vreg);
  762. else if (vreg->type == REGULATOR_TYPE_SMPS)
  763. rc = pm8901_init_smps(vreg);
  764. else if (vreg->type == REGULATOR_TYPE_VS)
  765. rc = pm8901_init_vs(vreg);
  766. bail:
  767. if (rc)
  768. pr_err("%s: pm8901_read/write failed; initial register states "
  769. "unknown, rc=%d\n", __func__, rc);
  770. return rc;
  771. }
  772. static int __devinit pm8901_vreg_probe(struct platform_device *pdev)
  773. {
  774. struct regulator_desc *rdesc;
  775. struct pm8901_vreg *vreg;
  776. const char *reg_name = NULL;
  777. int rc = 0;
  778. if (pdev == NULL)
  779. return -EINVAL;
  780. if (pdev->id >= 0 && pdev->id < PM8901_VREG_MAX) {
  781. rdesc = &pm8901_vreg_descrip[pdev->id];
  782. vreg = &pm8901_vreg[pdev->id];
  783. vreg->pdata = pdev->dev.platform_data;
  784. reg_name = pm8901_vreg_descrip[pdev->id].name;
  785. vreg->dev = &pdev->dev;
  786. rc = pm8901_init_regulator(vreg);
  787. if (rc)
  788. goto bail;
  789. /* Disallow idle and normal modes if pin control isn't set. */
  790. if (vreg->pdata->pin_ctrl == 0)
  791. vreg->pdata->init_data.constraints.valid_modes_mask
  792. &= ~(REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE);
  793. vreg->rdev = regulator_register(rdesc, &pdev->dev,
  794. &vreg->pdata->init_data, vreg, NULL);
  795. if (IS_ERR(vreg->rdev)) {
  796. rc = PTR_ERR(vreg->rdev);
  797. pr_err("%s: regulator_register failed for %s, rc=%d\n",
  798. __func__, reg_name, rc);
  799. }
  800. } else {
  801. rc = -ENODEV;
  802. }
  803. bail:
  804. if (rc)
  805. pr_err("%s: error for %s, rc=%d\n", __func__, reg_name, rc);
  806. return rc;
  807. }
  808. static int __devexit pm8901_vreg_remove(struct platform_device *pdev)
  809. {
  810. regulator_unregister(pm8901_vreg[pdev->id].rdev);
  811. return 0;
  812. }
  813. static struct platform_driver pm8901_vreg_driver = {
  814. .probe = pm8901_vreg_probe,
  815. .remove = __devexit_p(pm8901_vreg_remove),
  816. .driver = {
  817. .name = "pm8901-regulator",
  818. .owner = THIS_MODULE,
  819. },
  820. };
  821. static int __init pm8901_vreg_init(void)
  822. {
  823. return platform_driver_register(&pm8901_vreg_driver);
  824. }
  825. static void __exit pm8901_vreg_exit(void)
  826. {
  827. platform_driver_unregister(&pm8901_vreg_driver);
  828. }
  829. static void print_write_error(struct pm8901_vreg *vreg, int rc,
  830. const char *func)
  831. {
  832. const char *reg_name = NULL;
  833. ptrdiff_t id = vreg - pm8901_vreg;
  834. if (id >= 0 && id < PM8901_VREG_MAX)
  835. reg_name = pm8901_vreg_descrip[id].name;
  836. pr_err("%s: pm8901_vreg_write failed for %s, rc=%d\n",
  837. func, reg_name, rc);
  838. }
  839. subsys_initcall(pm8901_vreg_init);
  840. module_exit(pm8901_vreg_exit);
  841. MODULE_LICENSE("GPL v2");
  842. MODULE_DESCRIPTION("PMIC8901 regulator driver");
  843. MODULE_VERSION("1.0");
  844. MODULE_ALIAS("platform:pm8901-regulator");