pinctrl-pxa3xx.h 3.8 KB

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  1. /*
  2. * linux/drivers/pinctrl/pinctrl-pxa3xx.h
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * publishhed by the Free Software Foundation.
  7. *
  8. * Copyright (C) 2011, Marvell Technology Group Ltd.
  9. *
  10. * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
  11. *
  12. */
  13. #ifndef __PINCTRL_PXA3XX_H
  14. #include <linux/pinctrl/pinctrl.h>
  15. #include <linux/pinctrl/pinmux.h>
  16. #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
  17. #define PXA3xx_MUX_GPIO 0
  18. #define PXA3xx_MAX_MUX 8
  19. #define MFPR_FUNC_MASK 0x7
  20. enum pxa_cpu_type {
  21. PINCTRL_INVALID = 0,
  22. PINCTRL_PXA300,
  23. PINCTRL_PXA310,
  24. PINCTRL_PXA320,
  25. PINCTRL_PXA168,
  26. PINCTRL_PXA910,
  27. PINCTRL_PXA930,
  28. PINCTRL_PXA955,
  29. PINCTRL_MMP2,
  30. PINCTRL_MAX,
  31. };
  32. struct pxa3xx_mfp_pin {
  33. const char *name;
  34. const unsigned int pin;
  35. const unsigned int mfpr; /* register offset */
  36. const unsigned short func[8];
  37. };
  38. struct pxa3xx_pin_group {
  39. const char *name;
  40. const unsigned mux;
  41. const unsigned *pins;
  42. const unsigned npins;
  43. };
  44. struct pxa3xx_pmx_func {
  45. const char *name;
  46. const char * const * groups;
  47. const unsigned num_groups;
  48. };
  49. struct pxa3xx_pinmux_info {
  50. struct device *dev;
  51. struct pinctrl_dev *pctrl;
  52. enum pxa_cpu_type cputype;
  53. unsigned int phy_base;
  54. unsigned int phy_size;
  55. void __iomem *virt_base;
  56. struct pxa3xx_mfp_pin *mfp;
  57. unsigned int num_mfp;
  58. struct pxa3xx_pin_group *grps;
  59. unsigned int num_grps;
  60. struct pxa3xx_pmx_func *funcs;
  61. unsigned int num_funcs;
  62. unsigned int num_gpio;
  63. struct pinctrl_desc *desc;
  64. struct pinctrl_pin_desc *pads;
  65. unsigned int num_pads;
  66. unsigned ds_mask; /* drive strength mask */
  67. unsigned ds_shift; /* drive strength shift */
  68. unsigned slp_mask; /* sleep mask */
  69. unsigned slp_input_low;
  70. unsigned slp_input_high;
  71. unsigned slp_output_low;
  72. unsigned slp_output_high;
  73. unsigned slp_float;
  74. };
  75. enum pxa3xx_pin_list {
  76. GPIO0 = 0,
  77. GPIO1,
  78. GPIO2,
  79. GPIO3,
  80. GPIO4,
  81. GPIO5,
  82. GPIO6,
  83. GPIO7,
  84. GPIO8,
  85. GPIO9,
  86. GPIO10, /* 10 */
  87. GPIO11,
  88. GPIO12,
  89. GPIO13,
  90. GPIO14,
  91. GPIO15,
  92. GPIO16,
  93. GPIO17,
  94. GPIO18,
  95. GPIO19,
  96. GPIO20, /* 20 */
  97. GPIO21,
  98. GPIO22,
  99. GPIO23,
  100. GPIO24,
  101. GPIO25,
  102. GPIO26,
  103. GPIO27,
  104. GPIO28,
  105. GPIO29,
  106. GPIO30, /* 30 */
  107. GPIO31,
  108. GPIO32,
  109. GPIO33,
  110. GPIO34,
  111. GPIO35,
  112. GPIO36,
  113. GPIO37,
  114. GPIO38,
  115. GPIO39,
  116. GPIO40, /* 40 */
  117. GPIO41,
  118. GPIO42,
  119. GPIO43,
  120. GPIO44,
  121. GPIO45,
  122. GPIO46,
  123. GPIO47,
  124. GPIO48,
  125. GPIO49,
  126. GPIO50, /* 50 */
  127. GPIO51,
  128. GPIO52,
  129. GPIO53,
  130. GPIO54,
  131. GPIO55,
  132. GPIO56,
  133. GPIO57,
  134. GPIO58,
  135. GPIO59,
  136. GPIO60, /* 60 */
  137. GPIO61,
  138. GPIO62,
  139. GPIO63,
  140. GPIO64,
  141. GPIO65,
  142. GPIO66,
  143. GPIO67,
  144. GPIO68,
  145. GPIO69,
  146. GPIO70, /* 70 */
  147. GPIO71,
  148. GPIO72,
  149. GPIO73,
  150. GPIO74,
  151. GPIO75,
  152. GPIO76,
  153. GPIO77,
  154. GPIO78,
  155. GPIO79,
  156. GPIO80, /* 80 */
  157. GPIO81,
  158. GPIO82,
  159. GPIO83,
  160. GPIO84,
  161. GPIO85,
  162. GPIO86,
  163. GPIO87,
  164. GPIO88,
  165. GPIO89,
  166. GPIO90, /* 90 */
  167. GPIO91,
  168. GPIO92,
  169. GPIO93,
  170. GPIO94,
  171. GPIO95,
  172. GPIO96,
  173. GPIO97,
  174. GPIO98,
  175. GPIO99,
  176. GPIO100, /* 100 */
  177. GPIO101,
  178. GPIO102,
  179. GPIO103,
  180. GPIO104,
  181. GPIO105,
  182. GPIO106,
  183. GPIO107,
  184. GPIO108,
  185. GPIO109,
  186. GPIO110, /* 110 */
  187. GPIO111,
  188. GPIO112,
  189. GPIO113,
  190. GPIO114,
  191. GPIO115,
  192. GPIO116,
  193. GPIO117,
  194. GPIO118,
  195. GPIO119,
  196. GPIO120, /* 120 */
  197. GPIO121,
  198. GPIO122,
  199. GPIO123,
  200. GPIO124,
  201. GPIO125,
  202. GPIO126,
  203. GPIO127,
  204. GPIO128,
  205. GPIO129,
  206. GPIO130, /* 130 */
  207. GPIO131,
  208. GPIO132,
  209. GPIO133,
  210. GPIO134,
  211. GPIO135,
  212. GPIO136,
  213. GPIO137,
  214. GPIO138,
  215. GPIO139,
  216. GPIO140, /* 140 */
  217. GPIO141,
  218. GPIO142,
  219. GPIO143,
  220. GPIO144,
  221. GPIO145,
  222. GPIO146,
  223. GPIO147,
  224. GPIO148,
  225. GPIO149,
  226. GPIO150, /* 150 */
  227. GPIO151,
  228. GPIO152,
  229. GPIO153,
  230. GPIO154,
  231. GPIO155,
  232. GPIO156,
  233. GPIO157,
  234. GPIO158,
  235. GPIO159,
  236. GPIO160, /* 160 */
  237. GPIO161,
  238. GPIO162,
  239. GPIO163,
  240. GPIO164,
  241. GPIO165,
  242. GPIO166,
  243. GPIO167,
  244. GPIO168,
  245. GPIO169,
  246. };
  247. extern int pxa3xx_pinctrl_register(struct platform_device *pdev,
  248. struct pxa3xx_pinmux_info *info);
  249. extern int pxa3xx_pinctrl_unregister(struct platform_device *pdev);
  250. #endif /* __PINCTRL_PXA3XX_H */