main.c 60 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242
  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
  5. * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * OpenIB.org BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or
  14. * without modification, are permitted provided that the following
  15. * conditions are met:
  16. *
  17. * - Redistributions of source code must retain the above
  18. * copyright notice, this list of conditions and the following
  19. * disclaimer.
  20. *
  21. * - Redistributions in binary form must reproduce the above
  22. * copyright notice, this list of conditions and the following
  23. * disclaimer in the documentation and/or other materials
  24. * provided with the distribution.
  25. *
  26. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33. * SOFTWARE.
  34. */
  35. #include <linux/module.h>
  36. #include <linux/init.h>
  37. #include <linux/errno.h>
  38. #include <linux/pci.h>
  39. #include <linux/dma-mapping.h>
  40. #include <linux/slab.h>
  41. #include <linux/io-mapping.h>
  42. #include <linux/delay.h>
  43. #include <linux/mlx4/device.h>
  44. #include <linux/mlx4/doorbell.h>
  45. #include "mlx4.h"
  46. #include "fw.h"
  47. #include "icm.h"
  48. MODULE_AUTHOR("Roland Dreier");
  49. MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
  50. MODULE_LICENSE("Dual BSD/GPL");
  51. MODULE_VERSION(DRV_VERSION);
  52. struct workqueue_struct *mlx4_wq;
  53. #ifdef CONFIG_MLX4_DEBUG
  54. int mlx4_debug_level = 0;
  55. module_param_named(debug_level, mlx4_debug_level, int, 0644);
  56. MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  57. #endif /* CONFIG_MLX4_DEBUG */
  58. #ifdef CONFIG_PCI_MSI
  59. static int msi_x = 1;
  60. module_param(msi_x, int, 0444);
  61. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  62. #else /* CONFIG_PCI_MSI */
  63. #define msi_x (0)
  64. #endif /* CONFIG_PCI_MSI */
  65. static int num_vfs;
  66. module_param(num_vfs, int, 0444);
  67. MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
  68. static int probe_vf;
  69. module_param(probe_vf, int, 0644);
  70. MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
  71. int mlx4_log_num_mgm_entry_size = 10;
  72. module_param_named(log_num_mgm_entry_size,
  73. mlx4_log_num_mgm_entry_size, int, 0444);
  74. MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
  75. " of qp per mcg, for example:"
  76. " 10 gives 248.range: 9<="
  77. " log_num_mgm_entry_size <= 12");
  78. #define HCA_GLOBAL_CAP_MASK 0
  79. #define PF_CONTEXT_BEHAVIOUR_MASK 0
  80. static char mlx4_version[] __devinitdata =
  81. DRV_NAME ": Mellanox ConnectX core driver v"
  82. DRV_VERSION " (" DRV_RELDATE ")\n";
  83. static struct mlx4_profile default_profile = {
  84. .num_qp = 1 << 18,
  85. .num_srq = 1 << 16,
  86. .rdmarc_per_qp = 1 << 4,
  87. .num_cq = 1 << 16,
  88. .num_mcg = 1 << 13,
  89. .num_mpt = 1 << 19,
  90. .num_mtt = 1 << 20, /* It is really num mtt segements */
  91. };
  92. static int log_num_mac = 7;
  93. module_param_named(log_num_mac, log_num_mac, int, 0444);
  94. MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
  95. static int log_num_vlan;
  96. module_param_named(log_num_vlan, log_num_vlan, int, 0444);
  97. MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
  98. /* Log2 max number of VLANs per ETH port (0-7) */
  99. #define MLX4_LOG_NUM_VLANS 7
  100. static bool use_prio;
  101. module_param_named(use_prio, use_prio, bool, 0444);
  102. MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
  103. "(0/1, default 0)");
  104. int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
  105. module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
  106. MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
  107. static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
  108. static int arr_argc = 2;
  109. module_param_array(port_type_array, int, &arr_argc, 0444);
  110. MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
  111. "1 for IB, 2 for Ethernet");
  112. struct mlx4_port_config {
  113. struct list_head list;
  114. enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
  115. struct pci_dev *pdev;
  116. };
  117. static inline int mlx4_master_get_num_eqs(struct mlx4_dev *dev)
  118. {
  119. return dev->caps.reserved_eqs +
  120. MLX4_MFUNC_EQ_NUM * (dev->num_slaves + 1);
  121. }
  122. int mlx4_check_port_params(struct mlx4_dev *dev,
  123. enum mlx4_port_type *port_type)
  124. {
  125. int i;
  126. for (i = 0; i < dev->caps.num_ports - 1; i++) {
  127. if (port_type[i] != port_type[i + 1]) {
  128. if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
  129. mlx4_err(dev, "Only same port types supported "
  130. "on this HCA, aborting.\n");
  131. return -EINVAL;
  132. }
  133. if (port_type[i] == MLX4_PORT_TYPE_ETH &&
  134. port_type[i + 1] == MLX4_PORT_TYPE_IB)
  135. return -EINVAL;
  136. }
  137. }
  138. for (i = 0; i < dev->caps.num_ports; i++) {
  139. if (!(port_type[i] & dev->caps.supported_type[i+1])) {
  140. mlx4_err(dev, "Requested port type for port %d is not "
  141. "supported on this HCA\n", i + 1);
  142. return -EINVAL;
  143. }
  144. }
  145. return 0;
  146. }
  147. static void mlx4_set_port_mask(struct mlx4_dev *dev)
  148. {
  149. int i;
  150. for (i = 1; i <= dev->caps.num_ports; ++i)
  151. dev->caps.port_mask[i] = dev->caps.port_type[i];
  152. }
  153. static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
  154. {
  155. int err;
  156. int i;
  157. err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
  158. if (err) {
  159. mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
  160. return err;
  161. }
  162. if (dev_cap->min_page_sz > PAGE_SIZE) {
  163. mlx4_err(dev, "HCA minimum page size of %d bigger than "
  164. "kernel PAGE_SIZE of %ld, aborting.\n",
  165. dev_cap->min_page_sz, PAGE_SIZE);
  166. return -ENODEV;
  167. }
  168. if (dev_cap->num_ports > MLX4_MAX_PORTS) {
  169. mlx4_err(dev, "HCA has %d ports, but we only support %d, "
  170. "aborting.\n",
  171. dev_cap->num_ports, MLX4_MAX_PORTS);
  172. return -ENODEV;
  173. }
  174. if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
  175. mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
  176. "PCI resource 2 size of 0x%llx, aborting.\n",
  177. dev_cap->uar_size,
  178. (unsigned long long) pci_resource_len(dev->pdev, 2));
  179. return -ENODEV;
  180. }
  181. dev->caps.num_ports = dev_cap->num_ports;
  182. for (i = 1; i <= dev->caps.num_ports; ++i) {
  183. dev->caps.vl_cap[i] = dev_cap->max_vl[i];
  184. dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
  185. dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
  186. dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
  187. dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
  188. dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
  189. dev->caps.def_mac[i] = dev_cap->def_mac[i];
  190. dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
  191. dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
  192. dev->caps.default_sense[i] = dev_cap->default_sense[i];
  193. dev->caps.trans_type[i] = dev_cap->trans_type[i];
  194. dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
  195. dev->caps.wavelength[i] = dev_cap->wavelength[i];
  196. dev->caps.trans_code[i] = dev_cap->trans_code[i];
  197. }
  198. dev->caps.uar_page_size = PAGE_SIZE;
  199. dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
  200. dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
  201. dev->caps.bf_reg_size = dev_cap->bf_reg_size;
  202. dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
  203. dev->caps.max_sq_sg = dev_cap->max_sq_sg;
  204. dev->caps.max_rq_sg = dev_cap->max_rq_sg;
  205. dev->caps.max_wqes = dev_cap->max_qp_sz;
  206. dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
  207. dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
  208. dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
  209. dev->caps.reserved_srqs = dev_cap->reserved_srqs;
  210. dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
  211. dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
  212. dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
  213. /*
  214. * Subtract 1 from the limit because we need to allocate a
  215. * spare CQE so the HCA HW can tell the difference between an
  216. * empty CQ and a full CQ.
  217. */
  218. dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
  219. dev->caps.reserved_cqs = dev_cap->reserved_cqs;
  220. dev->caps.reserved_eqs = dev_cap->reserved_eqs;
  221. dev->caps.reserved_mtts = dev_cap->reserved_mtts;
  222. dev->caps.reserved_mrws = dev_cap->reserved_mrws;
  223. /* The first 128 UARs are used for EQ doorbells */
  224. dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
  225. dev->caps.reserved_pds = dev_cap->reserved_pds;
  226. dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
  227. dev_cap->reserved_xrcds : 0;
  228. dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
  229. dev_cap->max_xrcds : 0;
  230. dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
  231. dev->caps.max_msg_sz = dev_cap->max_msg_sz;
  232. dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
  233. dev->caps.flags = dev_cap->flags;
  234. dev->caps.bmme_flags = dev_cap->bmme_flags;
  235. dev->caps.reserved_lkey = dev_cap->reserved_lkey;
  236. dev->caps.stat_rate_support = dev_cap->stat_rate_support;
  237. dev->caps.max_gso_sz = dev_cap->max_gso_sz;
  238. /* Sense port always allowed on supported devices for ConnectX1 and 2 */
  239. if (dev->pdev->device != 0x1003)
  240. dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
  241. dev->caps.log_num_macs = log_num_mac;
  242. dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
  243. dev->caps.log_num_prios = use_prio ? 3 : 0;
  244. for (i = 1; i <= dev->caps.num_ports; ++i) {
  245. dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
  246. if (dev->caps.supported_type[i]) {
  247. /* if only ETH is supported - assign ETH */
  248. if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
  249. dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
  250. /* if only IB is supported,
  251. * assign IB only if SRIOV is off*/
  252. else if (dev->caps.supported_type[i] ==
  253. MLX4_PORT_TYPE_IB) {
  254. if (dev->flags & MLX4_FLAG_SRIOV)
  255. dev->caps.port_type[i] =
  256. MLX4_PORT_TYPE_NONE;
  257. else
  258. dev->caps.port_type[i] =
  259. MLX4_PORT_TYPE_IB;
  260. /* if IB and ETH are supported,
  261. * first of all check if SRIOV is on */
  262. } else if (dev->flags & MLX4_FLAG_SRIOV)
  263. dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
  264. else {
  265. /* In non-SRIOV mode, we set the port type
  266. * according to user selection of port type,
  267. * if usere selected none, take the FW hint */
  268. if (port_type_array[i-1] == MLX4_PORT_TYPE_NONE)
  269. dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
  270. MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
  271. else
  272. dev->caps.port_type[i] = port_type_array[i-1];
  273. }
  274. }
  275. /*
  276. * Link sensing is allowed on the port if 3 conditions are true:
  277. * 1. Both protocols are supported on the port.
  278. * 2. Different types are supported on the port
  279. * 3. FW declared that it supports link sensing
  280. */
  281. mlx4_priv(dev)->sense.sense_allowed[i] =
  282. ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
  283. (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
  284. (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
  285. /*
  286. * If "default_sense" bit is set, we move the port to "AUTO" mode
  287. * and perform sense_port FW command to try and set the correct
  288. * port type from beginning
  289. */
  290. if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
  291. enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
  292. dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
  293. mlx4_SENSE_PORT(dev, i, &sensed_port);
  294. if (sensed_port != MLX4_PORT_TYPE_NONE)
  295. dev->caps.port_type[i] = sensed_port;
  296. } else {
  297. dev->caps.possible_type[i] = dev->caps.port_type[i];
  298. }
  299. if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
  300. dev->caps.log_num_macs = dev_cap->log_max_macs[i];
  301. mlx4_warn(dev, "Requested number of MACs is too much "
  302. "for port %d, reducing to %d.\n",
  303. i, 1 << dev->caps.log_num_macs);
  304. }
  305. if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
  306. dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
  307. mlx4_warn(dev, "Requested number of VLANs is too much "
  308. "for port %d, reducing to %d.\n",
  309. i, 1 << dev->caps.log_num_vlans);
  310. }
  311. }
  312. dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
  313. dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
  314. dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
  315. dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
  316. (1 << dev->caps.log_num_macs) *
  317. (1 << dev->caps.log_num_vlans) *
  318. (1 << dev->caps.log_num_prios) *
  319. dev->caps.num_ports;
  320. dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
  321. dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
  322. dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
  323. dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
  324. dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
  325. return 0;
  326. }
  327. /*The function checks if there are live vf, return the num of them*/
  328. static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
  329. {
  330. struct mlx4_priv *priv = mlx4_priv(dev);
  331. struct mlx4_slave_state *s_state;
  332. int i;
  333. int ret = 0;
  334. for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
  335. s_state = &priv->mfunc.master.slave_state[i];
  336. if (s_state->active && s_state->last_cmd !=
  337. MLX4_COMM_CMD_RESET) {
  338. mlx4_warn(dev, "%s: slave: %d is still active\n",
  339. __func__, i);
  340. ret++;
  341. }
  342. }
  343. return ret;
  344. }
  345. int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
  346. {
  347. struct mlx4_priv *priv = mlx4_priv(dev);
  348. struct mlx4_slave_state *s_slave;
  349. if (!mlx4_is_master(dev))
  350. return 0;
  351. s_slave = &priv->mfunc.master.slave_state[slave];
  352. return !!s_slave->active;
  353. }
  354. EXPORT_SYMBOL(mlx4_is_slave_active);
  355. static int mlx4_slave_cap(struct mlx4_dev *dev)
  356. {
  357. int err;
  358. u32 page_size;
  359. struct mlx4_dev_cap dev_cap;
  360. struct mlx4_func_cap func_cap;
  361. struct mlx4_init_hca_param hca_param;
  362. int i;
  363. memset(&hca_param, 0, sizeof(hca_param));
  364. err = mlx4_QUERY_HCA(dev, &hca_param);
  365. if (err) {
  366. mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
  367. return err;
  368. }
  369. /*fail if the hca has an unknown capability */
  370. if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
  371. HCA_GLOBAL_CAP_MASK) {
  372. mlx4_err(dev, "Unknown hca global capabilities\n");
  373. return -ENOSYS;
  374. }
  375. mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
  376. memset(&dev_cap, 0, sizeof(dev_cap));
  377. err = mlx4_dev_cap(dev, &dev_cap);
  378. if (err) {
  379. mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
  380. return err;
  381. }
  382. page_size = ~dev->caps.page_size_cap + 1;
  383. mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
  384. if (page_size > PAGE_SIZE) {
  385. mlx4_err(dev, "HCA minimum page size of %d bigger than "
  386. "kernel PAGE_SIZE of %ld, aborting.\n",
  387. page_size, PAGE_SIZE);
  388. return -ENODEV;
  389. }
  390. /* slave gets uar page size from QUERY_HCA fw command */
  391. dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
  392. /* TODO: relax this assumption */
  393. if (dev->caps.uar_page_size != PAGE_SIZE) {
  394. mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
  395. dev->caps.uar_page_size, PAGE_SIZE);
  396. return -ENODEV;
  397. }
  398. memset(&func_cap, 0, sizeof(func_cap));
  399. err = mlx4_QUERY_FUNC_CAP(dev, &func_cap);
  400. if (err) {
  401. mlx4_err(dev, "QUERY_FUNC_CAP command failed, aborting.\n");
  402. return err;
  403. }
  404. if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
  405. PF_CONTEXT_BEHAVIOUR_MASK) {
  406. mlx4_err(dev, "Unknown pf context behaviour\n");
  407. return -ENOSYS;
  408. }
  409. dev->caps.num_ports = func_cap.num_ports;
  410. dev->caps.num_qps = func_cap.qp_quota;
  411. dev->caps.num_srqs = func_cap.srq_quota;
  412. dev->caps.num_cqs = func_cap.cq_quota;
  413. dev->caps.num_eqs = func_cap.max_eq;
  414. dev->caps.reserved_eqs = func_cap.reserved_eq;
  415. dev->caps.num_mpts = func_cap.mpt_quota;
  416. dev->caps.num_mtts = func_cap.mtt_quota;
  417. dev->caps.num_pds = MLX4_NUM_PDS;
  418. dev->caps.num_mgms = 0;
  419. dev->caps.num_amgms = 0;
  420. for (i = 1; i <= dev->caps.num_ports; ++i)
  421. dev->caps.port_mask[i] = dev->caps.port_type[i];
  422. if (dev->caps.num_ports > MLX4_MAX_PORTS) {
  423. mlx4_err(dev, "HCA has %d ports, but we only support %d, "
  424. "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
  425. return -ENODEV;
  426. }
  427. if (dev->caps.uar_page_size * (dev->caps.num_uars -
  428. dev->caps.reserved_uars) >
  429. pci_resource_len(dev->pdev, 2)) {
  430. mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
  431. "PCI resource 2 size of 0x%llx, aborting.\n",
  432. dev->caps.uar_page_size * dev->caps.num_uars,
  433. (unsigned long long) pci_resource_len(dev->pdev, 2));
  434. return -ENODEV;
  435. }
  436. #if 0
  437. mlx4_warn(dev, "sqp_demux:%d\n", dev->caps.sqp_demux);
  438. mlx4_warn(dev, "num_uars:%d reserved_uars:%d uar region:0x%x bar2:0x%llx\n",
  439. dev->caps.num_uars, dev->caps.reserved_uars,
  440. dev->caps.uar_page_size * dev->caps.num_uars,
  441. pci_resource_len(dev->pdev, 2));
  442. mlx4_warn(dev, "num_eqs:%d reserved_eqs:%d\n", dev->caps.num_eqs,
  443. dev->caps.reserved_eqs);
  444. mlx4_warn(dev, "num_pds:%d reserved_pds:%d slave_pd_shift:%d pd_base:%d\n",
  445. dev->caps.num_pds, dev->caps.reserved_pds,
  446. dev->caps.slave_pd_shift, dev->caps.pd_base);
  447. #endif
  448. return 0;
  449. }
  450. /*
  451. * Change the port configuration of the device.
  452. * Every user of this function must hold the port mutex.
  453. */
  454. int mlx4_change_port_types(struct mlx4_dev *dev,
  455. enum mlx4_port_type *port_types)
  456. {
  457. int err = 0;
  458. int change = 0;
  459. int port;
  460. for (port = 0; port < dev->caps.num_ports; port++) {
  461. /* Change the port type only if the new type is different
  462. * from the current, and not set to Auto */
  463. if (port_types[port] != dev->caps.port_type[port + 1])
  464. change = 1;
  465. }
  466. if (change) {
  467. mlx4_unregister_device(dev);
  468. for (port = 1; port <= dev->caps.num_ports; port++) {
  469. mlx4_CLOSE_PORT(dev, port);
  470. dev->caps.port_type[port] = port_types[port - 1];
  471. err = mlx4_SET_PORT(dev, port);
  472. if (err) {
  473. mlx4_err(dev, "Failed to set port %d, "
  474. "aborting\n", port);
  475. goto out;
  476. }
  477. }
  478. mlx4_set_port_mask(dev);
  479. err = mlx4_register_device(dev);
  480. }
  481. out:
  482. return err;
  483. }
  484. static ssize_t show_port_type(struct device *dev,
  485. struct device_attribute *attr,
  486. char *buf)
  487. {
  488. struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
  489. port_attr);
  490. struct mlx4_dev *mdev = info->dev;
  491. char type[8];
  492. sprintf(type, "%s",
  493. (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
  494. "ib" : "eth");
  495. if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
  496. sprintf(buf, "auto (%s)\n", type);
  497. else
  498. sprintf(buf, "%s\n", type);
  499. return strlen(buf);
  500. }
  501. static ssize_t set_port_type(struct device *dev,
  502. struct device_attribute *attr,
  503. const char *buf, size_t count)
  504. {
  505. struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
  506. port_attr);
  507. struct mlx4_dev *mdev = info->dev;
  508. struct mlx4_priv *priv = mlx4_priv(mdev);
  509. enum mlx4_port_type types[MLX4_MAX_PORTS];
  510. enum mlx4_port_type new_types[MLX4_MAX_PORTS];
  511. int i;
  512. int err = 0;
  513. if (!strcmp(buf, "ib\n"))
  514. info->tmp_type = MLX4_PORT_TYPE_IB;
  515. else if (!strcmp(buf, "eth\n"))
  516. info->tmp_type = MLX4_PORT_TYPE_ETH;
  517. else if (!strcmp(buf, "auto\n"))
  518. info->tmp_type = MLX4_PORT_TYPE_AUTO;
  519. else {
  520. mlx4_err(mdev, "%s is not supported port type\n", buf);
  521. return -EINVAL;
  522. }
  523. mlx4_stop_sense(mdev);
  524. mutex_lock(&priv->port_mutex);
  525. /* Possible type is always the one that was delivered */
  526. mdev->caps.possible_type[info->port] = info->tmp_type;
  527. for (i = 0; i < mdev->caps.num_ports; i++) {
  528. types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
  529. mdev->caps.possible_type[i+1];
  530. if (types[i] == MLX4_PORT_TYPE_AUTO)
  531. types[i] = mdev->caps.port_type[i+1];
  532. }
  533. if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
  534. !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
  535. for (i = 1; i <= mdev->caps.num_ports; i++) {
  536. if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
  537. mdev->caps.possible_type[i] = mdev->caps.port_type[i];
  538. err = -EINVAL;
  539. }
  540. }
  541. }
  542. if (err) {
  543. mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
  544. "Set only 'eth' or 'ib' for both ports "
  545. "(should be the same)\n");
  546. goto out;
  547. }
  548. mlx4_do_sense_ports(mdev, new_types, types);
  549. err = mlx4_check_port_params(mdev, new_types);
  550. if (err)
  551. goto out;
  552. /* We are about to apply the changes after the configuration
  553. * was verified, no need to remember the temporary types
  554. * any more */
  555. for (i = 0; i < mdev->caps.num_ports; i++)
  556. priv->port[i + 1].tmp_type = 0;
  557. err = mlx4_change_port_types(mdev, new_types);
  558. out:
  559. mlx4_start_sense(mdev);
  560. mutex_unlock(&priv->port_mutex);
  561. return err ? err : count;
  562. }
  563. enum ibta_mtu {
  564. IB_MTU_256 = 1,
  565. IB_MTU_512 = 2,
  566. IB_MTU_1024 = 3,
  567. IB_MTU_2048 = 4,
  568. IB_MTU_4096 = 5
  569. };
  570. static inline int int_to_ibta_mtu(int mtu)
  571. {
  572. switch (mtu) {
  573. case 256: return IB_MTU_256;
  574. case 512: return IB_MTU_512;
  575. case 1024: return IB_MTU_1024;
  576. case 2048: return IB_MTU_2048;
  577. case 4096: return IB_MTU_4096;
  578. default: return -1;
  579. }
  580. }
  581. static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
  582. {
  583. switch (mtu) {
  584. case IB_MTU_256: return 256;
  585. case IB_MTU_512: return 512;
  586. case IB_MTU_1024: return 1024;
  587. case IB_MTU_2048: return 2048;
  588. case IB_MTU_4096: return 4096;
  589. default: return -1;
  590. }
  591. }
  592. static ssize_t show_port_ib_mtu(struct device *dev,
  593. struct device_attribute *attr,
  594. char *buf)
  595. {
  596. struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
  597. port_mtu_attr);
  598. struct mlx4_dev *mdev = info->dev;
  599. if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
  600. mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
  601. sprintf(buf, "%d\n",
  602. ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
  603. return strlen(buf);
  604. }
  605. static ssize_t set_port_ib_mtu(struct device *dev,
  606. struct device_attribute *attr,
  607. const char *buf, size_t count)
  608. {
  609. struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
  610. port_mtu_attr);
  611. struct mlx4_dev *mdev = info->dev;
  612. struct mlx4_priv *priv = mlx4_priv(mdev);
  613. int err, port, mtu, ibta_mtu = -1;
  614. if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
  615. mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
  616. return -EINVAL;
  617. }
  618. err = sscanf(buf, "%d", &mtu);
  619. if (err > 0)
  620. ibta_mtu = int_to_ibta_mtu(mtu);
  621. if (err <= 0 || ibta_mtu < 0) {
  622. mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
  623. return -EINVAL;
  624. }
  625. mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
  626. mlx4_stop_sense(mdev);
  627. mutex_lock(&priv->port_mutex);
  628. mlx4_unregister_device(mdev);
  629. for (port = 1; port <= mdev->caps.num_ports; port++) {
  630. mlx4_CLOSE_PORT(mdev, port);
  631. err = mlx4_SET_PORT(mdev, port);
  632. if (err) {
  633. mlx4_err(mdev, "Failed to set port %d, "
  634. "aborting\n", port);
  635. goto err_set_port;
  636. }
  637. }
  638. err = mlx4_register_device(mdev);
  639. err_set_port:
  640. mutex_unlock(&priv->port_mutex);
  641. mlx4_start_sense(mdev);
  642. return err ? err : count;
  643. }
  644. static int mlx4_load_fw(struct mlx4_dev *dev)
  645. {
  646. struct mlx4_priv *priv = mlx4_priv(dev);
  647. int err;
  648. priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
  649. GFP_HIGHUSER | __GFP_NOWARN, 0);
  650. if (!priv->fw.fw_icm) {
  651. mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
  652. return -ENOMEM;
  653. }
  654. err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
  655. if (err) {
  656. mlx4_err(dev, "MAP_FA command failed, aborting.\n");
  657. goto err_free;
  658. }
  659. err = mlx4_RUN_FW(dev);
  660. if (err) {
  661. mlx4_err(dev, "RUN_FW command failed, aborting.\n");
  662. goto err_unmap_fa;
  663. }
  664. return 0;
  665. err_unmap_fa:
  666. mlx4_UNMAP_FA(dev);
  667. err_free:
  668. mlx4_free_icm(dev, priv->fw.fw_icm, 0);
  669. return err;
  670. }
  671. static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
  672. int cmpt_entry_sz)
  673. {
  674. struct mlx4_priv *priv = mlx4_priv(dev);
  675. int err;
  676. int num_eqs;
  677. err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
  678. cmpt_base +
  679. ((u64) (MLX4_CMPT_TYPE_QP *
  680. cmpt_entry_sz) << MLX4_CMPT_SHIFT),
  681. cmpt_entry_sz, dev->caps.num_qps,
  682. dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
  683. 0, 0);
  684. if (err)
  685. goto err;
  686. err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
  687. cmpt_base +
  688. ((u64) (MLX4_CMPT_TYPE_SRQ *
  689. cmpt_entry_sz) << MLX4_CMPT_SHIFT),
  690. cmpt_entry_sz, dev->caps.num_srqs,
  691. dev->caps.reserved_srqs, 0, 0);
  692. if (err)
  693. goto err_qp;
  694. err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
  695. cmpt_base +
  696. ((u64) (MLX4_CMPT_TYPE_CQ *
  697. cmpt_entry_sz) << MLX4_CMPT_SHIFT),
  698. cmpt_entry_sz, dev->caps.num_cqs,
  699. dev->caps.reserved_cqs, 0, 0);
  700. if (err)
  701. goto err_srq;
  702. num_eqs = (mlx4_is_master(dev)) ?
  703. roundup_pow_of_two(mlx4_master_get_num_eqs(dev)) :
  704. dev->caps.num_eqs;
  705. err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
  706. cmpt_base +
  707. ((u64) (MLX4_CMPT_TYPE_EQ *
  708. cmpt_entry_sz) << MLX4_CMPT_SHIFT),
  709. cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
  710. if (err)
  711. goto err_cq;
  712. return 0;
  713. err_cq:
  714. mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
  715. err_srq:
  716. mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
  717. err_qp:
  718. mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
  719. err:
  720. return err;
  721. }
  722. static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
  723. struct mlx4_init_hca_param *init_hca, u64 icm_size)
  724. {
  725. struct mlx4_priv *priv = mlx4_priv(dev);
  726. u64 aux_pages;
  727. int num_eqs;
  728. int err;
  729. err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
  730. if (err) {
  731. mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
  732. return err;
  733. }
  734. mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  735. (unsigned long long) icm_size >> 10,
  736. (unsigned long long) aux_pages << 2);
  737. priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
  738. GFP_HIGHUSER | __GFP_NOWARN, 0);
  739. if (!priv->fw.aux_icm) {
  740. mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
  741. return -ENOMEM;
  742. }
  743. err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
  744. if (err) {
  745. mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
  746. goto err_free_aux;
  747. }
  748. err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
  749. if (err) {
  750. mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
  751. goto err_unmap_aux;
  752. }
  753. num_eqs = (mlx4_is_master(dev)) ?
  754. roundup_pow_of_two(mlx4_master_get_num_eqs(dev)) :
  755. dev->caps.num_eqs;
  756. err = mlx4_init_icm_table(dev, &priv->eq_table.table,
  757. init_hca->eqc_base, dev_cap->eqc_entry_sz,
  758. num_eqs, num_eqs, 0, 0);
  759. if (err) {
  760. mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
  761. goto err_unmap_cmpt;
  762. }
  763. /*
  764. * Reserved MTT entries must be aligned up to a cacheline
  765. * boundary, since the FW will write to them, while the driver
  766. * writes to all other MTT entries. (The variable
  767. * dev->caps.mtt_entry_sz below is really the MTT segment
  768. * size, not the raw entry size)
  769. */
  770. dev->caps.reserved_mtts =
  771. ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
  772. dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
  773. err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
  774. init_hca->mtt_base,
  775. dev->caps.mtt_entry_sz,
  776. dev->caps.num_mtts,
  777. dev->caps.reserved_mtts, 1, 0);
  778. if (err) {
  779. mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
  780. goto err_unmap_eq;
  781. }
  782. err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
  783. init_hca->dmpt_base,
  784. dev_cap->dmpt_entry_sz,
  785. dev->caps.num_mpts,
  786. dev->caps.reserved_mrws, 1, 1);
  787. if (err) {
  788. mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
  789. goto err_unmap_mtt;
  790. }
  791. err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
  792. init_hca->qpc_base,
  793. dev_cap->qpc_entry_sz,
  794. dev->caps.num_qps,
  795. dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
  796. 0, 0);
  797. if (err) {
  798. mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
  799. goto err_unmap_dmpt;
  800. }
  801. err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
  802. init_hca->auxc_base,
  803. dev_cap->aux_entry_sz,
  804. dev->caps.num_qps,
  805. dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
  806. 0, 0);
  807. if (err) {
  808. mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
  809. goto err_unmap_qp;
  810. }
  811. err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
  812. init_hca->altc_base,
  813. dev_cap->altc_entry_sz,
  814. dev->caps.num_qps,
  815. dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
  816. 0, 0);
  817. if (err) {
  818. mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
  819. goto err_unmap_auxc;
  820. }
  821. err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
  822. init_hca->rdmarc_base,
  823. dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
  824. dev->caps.num_qps,
  825. dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
  826. 0, 0);
  827. if (err) {
  828. mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
  829. goto err_unmap_altc;
  830. }
  831. err = mlx4_init_icm_table(dev, &priv->cq_table.table,
  832. init_hca->cqc_base,
  833. dev_cap->cqc_entry_sz,
  834. dev->caps.num_cqs,
  835. dev->caps.reserved_cqs, 0, 0);
  836. if (err) {
  837. mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
  838. goto err_unmap_rdmarc;
  839. }
  840. err = mlx4_init_icm_table(dev, &priv->srq_table.table,
  841. init_hca->srqc_base,
  842. dev_cap->srq_entry_sz,
  843. dev->caps.num_srqs,
  844. dev->caps.reserved_srqs, 0, 0);
  845. if (err) {
  846. mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
  847. goto err_unmap_cq;
  848. }
  849. /*
  850. * It's not strictly required, but for simplicity just map the
  851. * whole multicast group table now. The table isn't very big
  852. * and it's a lot easier than trying to track ref counts.
  853. */
  854. err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
  855. init_hca->mc_base,
  856. mlx4_get_mgm_entry_size(dev),
  857. dev->caps.num_mgms + dev->caps.num_amgms,
  858. dev->caps.num_mgms + dev->caps.num_amgms,
  859. 0, 0);
  860. if (err) {
  861. mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
  862. goto err_unmap_srq;
  863. }
  864. return 0;
  865. err_unmap_srq:
  866. mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
  867. err_unmap_cq:
  868. mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
  869. err_unmap_rdmarc:
  870. mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
  871. err_unmap_altc:
  872. mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
  873. err_unmap_auxc:
  874. mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
  875. err_unmap_qp:
  876. mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
  877. err_unmap_dmpt:
  878. mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
  879. err_unmap_mtt:
  880. mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
  881. err_unmap_eq:
  882. mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
  883. err_unmap_cmpt:
  884. mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
  885. mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
  886. mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
  887. mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
  888. err_unmap_aux:
  889. mlx4_UNMAP_ICM_AUX(dev);
  890. err_free_aux:
  891. mlx4_free_icm(dev, priv->fw.aux_icm, 0);
  892. return err;
  893. }
  894. static void mlx4_free_icms(struct mlx4_dev *dev)
  895. {
  896. struct mlx4_priv *priv = mlx4_priv(dev);
  897. mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
  898. mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
  899. mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
  900. mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
  901. mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
  902. mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
  903. mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
  904. mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
  905. mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
  906. mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
  907. mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
  908. mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
  909. mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
  910. mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
  911. mlx4_UNMAP_ICM_AUX(dev);
  912. mlx4_free_icm(dev, priv->fw.aux_icm, 0);
  913. }
  914. static void mlx4_slave_exit(struct mlx4_dev *dev)
  915. {
  916. struct mlx4_priv *priv = mlx4_priv(dev);
  917. down(&priv->cmd.slave_sem);
  918. if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
  919. mlx4_warn(dev, "Failed to close slave function.\n");
  920. up(&priv->cmd.slave_sem);
  921. }
  922. static int map_bf_area(struct mlx4_dev *dev)
  923. {
  924. struct mlx4_priv *priv = mlx4_priv(dev);
  925. resource_size_t bf_start;
  926. resource_size_t bf_len;
  927. int err = 0;
  928. if (!dev->caps.bf_reg_size)
  929. return -ENXIO;
  930. bf_start = pci_resource_start(dev->pdev, 2) +
  931. (dev->caps.num_uars << PAGE_SHIFT);
  932. bf_len = pci_resource_len(dev->pdev, 2) -
  933. (dev->caps.num_uars << PAGE_SHIFT);
  934. priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
  935. if (!priv->bf_mapping)
  936. err = -ENOMEM;
  937. return err;
  938. }
  939. static void unmap_bf_area(struct mlx4_dev *dev)
  940. {
  941. if (mlx4_priv(dev)->bf_mapping)
  942. io_mapping_free(mlx4_priv(dev)->bf_mapping);
  943. }
  944. static void mlx4_close_hca(struct mlx4_dev *dev)
  945. {
  946. unmap_bf_area(dev);
  947. if (mlx4_is_slave(dev))
  948. mlx4_slave_exit(dev);
  949. else {
  950. mlx4_CLOSE_HCA(dev, 0);
  951. mlx4_free_icms(dev);
  952. mlx4_UNMAP_FA(dev);
  953. mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
  954. }
  955. }
  956. static int mlx4_init_slave(struct mlx4_dev *dev)
  957. {
  958. struct mlx4_priv *priv = mlx4_priv(dev);
  959. u64 dma = (u64) priv->mfunc.vhcr_dma;
  960. int num_of_reset_retries = NUM_OF_RESET_RETRIES;
  961. int ret_from_reset = 0;
  962. u32 slave_read;
  963. u32 cmd_channel_ver;
  964. down(&priv->cmd.slave_sem);
  965. priv->cmd.max_cmds = 1;
  966. mlx4_warn(dev, "Sending reset\n");
  967. ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
  968. MLX4_COMM_TIME);
  969. /* if we are in the middle of flr the slave will try
  970. * NUM_OF_RESET_RETRIES times before leaving.*/
  971. if (ret_from_reset) {
  972. if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
  973. msleep(SLEEP_TIME_IN_RESET);
  974. while (ret_from_reset && num_of_reset_retries) {
  975. mlx4_warn(dev, "slave is currently in the"
  976. "middle of FLR. retrying..."
  977. "(try num:%d)\n",
  978. (NUM_OF_RESET_RETRIES -
  979. num_of_reset_retries + 1));
  980. ret_from_reset =
  981. mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET,
  982. 0, MLX4_COMM_TIME);
  983. num_of_reset_retries = num_of_reset_retries - 1;
  984. }
  985. } else
  986. goto err;
  987. }
  988. /* check the driver version - the slave I/F revision
  989. * must match the master's */
  990. slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
  991. cmd_channel_ver = mlx4_comm_get_version();
  992. if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
  993. MLX4_COMM_GET_IF_REV(slave_read)) {
  994. mlx4_err(dev, "slave driver version is not supported"
  995. " by the master\n");
  996. goto err;
  997. }
  998. mlx4_warn(dev, "Sending vhcr0\n");
  999. if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
  1000. MLX4_COMM_TIME))
  1001. goto err;
  1002. if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
  1003. MLX4_COMM_TIME))
  1004. goto err;
  1005. if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
  1006. MLX4_COMM_TIME))
  1007. goto err;
  1008. if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
  1009. goto err;
  1010. up(&priv->cmd.slave_sem);
  1011. return 0;
  1012. err:
  1013. mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
  1014. up(&priv->cmd.slave_sem);
  1015. return -EIO;
  1016. }
  1017. static int mlx4_init_hca(struct mlx4_dev *dev)
  1018. {
  1019. struct mlx4_priv *priv = mlx4_priv(dev);
  1020. struct mlx4_adapter adapter;
  1021. struct mlx4_dev_cap dev_cap;
  1022. struct mlx4_mod_stat_cfg mlx4_cfg;
  1023. struct mlx4_profile profile;
  1024. struct mlx4_init_hca_param init_hca;
  1025. u64 icm_size;
  1026. int err;
  1027. if (!mlx4_is_slave(dev)) {
  1028. err = mlx4_QUERY_FW(dev);
  1029. if (err) {
  1030. if (err == -EACCES)
  1031. mlx4_info(dev, "non-primary physical function, skipping.\n");
  1032. else
  1033. mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
  1034. goto unmap_bf;
  1035. }
  1036. err = mlx4_load_fw(dev);
  1037. if (err) {
  1038. mlx4_err(dev, "Failed to start FW, aborting.\n");
  1039. goto unmap_bf;
  1040. }
  1041. mlx4_cfg.log_pg_sz_m = 1;
  1042. mlx4_cfg.log_pg_sz = 0;
  1043. err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
  1044. if (err)
  1045. mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
  1046. err = mlx4_dev_cap(dev, &dev_cap);
  1047. if (err) {
  1048. mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
  1049. goto err_stop_fw;
  1050. }
  1051. profile = default_profile;
  1052. icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
  1053. &init_hca);
  1054. if ((long long) icm_size < 0) {
  1055. err = icm_size;
  1056. goto err_stop_fw;
  1057. }
  1058. dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
  1059. init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
  1060. init_hca.uar_page_sz = PAGE_SHIFT - 12;
  1061. err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
  1062. if (err)
  1063. goto err_stop_fw;
  1064. err = mlx4_INIT_HCA(dev, &init_hca);
  1065. if (err) {
  1066. mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
  1067. goto err_free_icm;
  1068. }
  1069. } else {
  1070. err = mlx4_init_slave(dev);
  1071. if (err) {
  1072. mlx4_err(dev, "Failed to initialize slave\n");
  1073. goto unmap_bf;
  1074. }
  1075. err = mlx4_slave_cap(dev);
  1076. if (err) {
  1077. mlx4_err(dev, "Failed to obtain slave caps\n");
  1078. goto err_close;
  1079. }
  1080. }
  1081. if (map_bf_area(dev))
  1082. mlx4_dbg(dev, "Failed to map blue flame area\n");
  1083. /*Only the master set the ports, all the rest got it from it.*/
  1084. if (!mlx4_is_slave(dev))
  1085. mlx4_set_port_mask(dev);
  1086. err = mlx4_QUERY_ADAPTER(dev, &adapter);
  1087. if (err) {
  1088. mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
  1089. goto err_close;
  1090. }
  1091. priv->eq_table.inta_pin = adapter.inta_pin;
  1092. memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
  1093. return 0;
  1094. err_close:
  1095. mlx4_close_hca(dev);
  1096. err_free_icm:
  1097. if (!mlx4_is_slave(dev))
  1098. mlx4_free_icms(dev);
  1099. err_stop_fw:
  1100. if (!mlx4_is_slave(dev)) {
  1101. mlx4_UNMAP_FA(dev);
  1102. mlx4_free_icm(dev, priv->fw.fw_icm, 0);
  1103. }
  1104. unmap_bf:
  1105. unmap_bf_area(dev);
  1106. return err;
  1107. }
  1108. static int mlx4_init_counters_table(struct mlx4_dev *dev)
  1109. {
  1110. struct mlx4_priv *priv = mlx4_priv(dev);
  1111. int nent;
  1112. if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
  1113. return -ENOENT;
  1114. nent = dev->caps.max_counters;
  1115. return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
  1116. }
  1117. static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
  1118. {
  1119. mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
  1120. }
  1121. int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
  1122. {
  1123. struct mlx4_priv *priv = mlx4_priv(dev);
  1124. if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
  1125. return -ENOENT;
  1126. *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
  1127. if (*idx == -1)
  1128. return -ENOMEM;
  1129. return 0;
  1130. }
  1131. EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
  1132. void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
  1133. {
  1134. mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx);
  1135. return;
  1136. }
  1137. EXPORT_SYMBOL_GPL(mlx4_counter_free);
  1138. static int mlx4_setup_hca(struct mlx4_dev *dev)
  1139. {
  1140. struct mlx4_priv *priv = mlx4_priv(dev);
  1141. int err;
  1142. int port;
  1143. __be32 ib_port_default_caps;
  1144. err = mlx4_init_uar_table(dev);
  1145. if (err) {
  1146. mlx4_err(dev, "Failed to initialize "
  1147. "user access region table, aborting.\n");
  1148. return err;
  1149. }
  1150. err = mlx4_uar_alloc(dev, &priv->driver_uar);
  1151. if (err) {
  1152. mlx4_err(dev, "Failed to allocate driver access region, "
  1153. "aborting.\n");
  1154. goto err_uar_table_free;
  1155. }
  1156. priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  1157. if (!priv->kar) {
  1158. mlx4_err(dev, "Couldn't map kernel access region, "
  1159. "aborting.\n");
  1160. err = -ENOMEM;
  1161. goto err_uar_free;
  1162. }
  1163. err = mlx4_init_pd_table(dev);
  1164. if (err) {
  1165. mlx4_err(dev, "Failed to initialize "
  1166. "protection domain table, aborting.\n");
  1167. goto err_kar_unmap;
  1168. }
  1169. err = mlx4_init_xrcd_table(dev);
  1170. if (err) {
  1171. mlx4_err(dev, "Failed to initialize "
  1172. "reliable connection domain table, aborting.\n");
  1173. goto err_pd_table_free;
  1174. }
  1175. err = mlx4_init_mr_table(dev);
  1176. if (err) {
  1177. mlx4_err(dev, "Failed to initialize "
  1178. "memory region table, aborting.\n");
  1179. goto err_xrcd_table_free;
  1180. }
  1181. err = mlx4_init_eq_table(dev);
  1182. if (err) {
  1183. mlx4_err(dev, "Failed to initialize "
  1184. "event queue table, aborting.\n");
  1185. goto err_mr_table_free;
  1186. }
  1187. err = mlx4_cmd_use_events(dev);
  1188. if (err) {
  1189. mlx4_err(dev, "Failed to switch to event-driven "
  1190. "firmware commands, aborting.\n");
  1191. goto err_eq_table_free;
  1192. }
  1193. err = mlx4_NOP(dev);
  1194. if (err) {
  1195. if (dev->flags & MLX4_FLAG_MSI_X) {
  1196. mlx4_warn(dev, "NOP command failed to generate MSI-X "
  1197. "interrupt IRQ %d).\n",
  1198. priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
  1199. mlx4_warn(dev, "Trying again without MSI-X.\n");
  1200. } else {
  1201. mlx4_err(dev, "NOP command failed to generate interrupt "
  1202. "(IRQ %d), aborting.\n",
  1203. priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
  1204. mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  1205. }
  1206. goto err_cmd_poll;
  1207. }
  1208. mlx4_dbg(dev, "NOP command IRQ test passed\n");
  1209. err = mlx4_init_cq_table(dev);
  1210. if (err) {
  1211. mlx4_err(dev, "Failed to initialize "
  1212. "completion queue table, aborting.\n");
  1213. goto err_cmd_poll;
  1214. }
  1215. err = mlx4_init_srq_table(dev);
  1216. if (err) {
  1217. mlx4_err(dev, "Failed to initialize "
  1218. "shared receive queue table, aborting.\n");
  1219. goto err_cq_table_free;
  1220. }
  1221. err = mlx4_init_qp_table(dev);
  1222. if (err) {
  1223. mlx4_err(dev, "Failed to initialize "
  1224. "queue pair table, aborting.\n");
  1225. goto err_srq_table_free;
  1226. }
  1227. if (!mlx4_is_slave(dev)) {
  1228. err = mlx4_init_mcg_table(dev);
  1229. if (err) {
  1230. mlx4_err(dev, "Failed to initialize "
  1231. "multicast group table, aborting.\n");
  1232. goto err_qp_table_free;
  1233. }
  1234. }
  1235. err = mlx4_init_counters_table(dev);
  1236. if (err && err != -ENOENT) {
  1237. mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
  1238. goto err_mcg_table_free;
  1239. }
  1240. if (!mlx4_is_slave(dev)) {
  1241. for (port = 1; port <= dev->caps.num_ports; port++) {
  1242. ib_port_default_caps = 0;
  1243. err = mlx4_get_port_ib_caps(dev, port,
  1244. &ib_port_default_caps);
  1245. if (err)
  1246. mlx4_warn(dev, "failed to get port %d default "
  1247. "ib capabilities (%d). Continuing "
  1248. "with caps = 0\n", port, err);
  1249. dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
  1250. if (mlx4_is_mfunc(dev))
  1251. dev->caps.port_ib_mtu[port] = IB_MTU_2048;
  1252. else
  1253. dev->caps.port_ib_mtu[port] = IB_MTU_4096;
  1254. err = mlx4_SET_PORT(dev, port);
  1255. if (err) {
  1256. mlx4_err(dev, "Failed to set port %d, aborting\n",
  1257. port);
  1258. goto err_counters_table_free;
  1259. }
  1260. }
  1261. }
  1262. return 0;
  1263. err_counters_table_free:
  1264. mlx4_cleanup_counters_table(dev);
  1265. err_mcg_table_free:
  1266. mlx4_cleanup_mcg_table(dev);
  1267. err_qp_table_free:
  1268. mlx4_cleanup_qp_table(dev);
  1269. err_srq_table_free:
  1270. mlx4_cleanup_srq_table(dev);
  1271. err_cq_table_free:
  1272. mlx4_cleanup_cq_table(dev);
  1273. err_cmd_poll:
  1274. mlx4_cmd_use_polling(dev);
  1275. err_eq_table_free:
  1276. mlx4_cleanup_eq_table(dev);
  1277. err_mr_table_free:
  1278. mlx4_cleanup_mr_table(dev);
  1279. err_xrcd_table_free:
  1280. mlx4_cleanup_xrcd_table(dev);
  1281. err_pd_table_free:
  1282. mlx4_cleanup_pd_table(dev);
  1283. err_kar_unmap:
  1284. iounmap(priv->kar);
  1285. err_uar_free:
  1286. mlx4_uar_free(dev, &priv->driver_uar);
  1287. err_uar_table_free:
  1288. mlx4_cleanup_uar_table(dev);
  1289. return err;
  1290. }
  1291. static void mlx4_enable_msi_x(struct mlx4_dev *dev)
  1292. {
  1293. struct mlx4_priv *priv = mlx4_priv(dev);
  1294. struct msix_entry *entries;
  1295. int nreq = min_t(int, dev->caps.num_ports *
  1296. min_t(int, num_online_cpus() + 1, MAX_MSIX_P_PORT)
  1297. + MSIX_LEGACY_SZ, MAX_MSIX);
  1298. int err;
  1299. int i;
  1300. if (msi_x) {
  1301. nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
  1302. nreq);
  1303. entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
  1304. if (!entries)
  1305. goto no_msi;
  1306. for (i = 0; i < nreq; ++i)
  1307. entries[i].entry = i;
  1308. retry:
  1309. err = pci_enable_msix(dev->pdev, entries, nreq);
  1310. if (err) {
  1311. /* Try again if at least 2 vectors are available */
  1312. if (err > 1) {
  1313. mlx4_info(dev, "Requested %d vectors, "
  1314. "but only %d MSI-X vectors available, "
  1315. "trying again\n", nreq, err);
  1316. nreq = err;
  1317. goto retry;
  1318. }
  1319. kfree(entries);
  1320. goto no_msi;
  1321. }
  1322. if (nreq <
  1323. MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
  1324. /*Working in legacy mode , all EQ's shared*/
  1325. dev->caps.comp_pool = 0;
  1326. dev->caps.num_comp_vectors = nreq - 1;
  1327. } else {
  1328. dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
  1329. dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
  1330. }
  1331. for (i = 0; i < nreq; ++i)
  1332. priv->eq_table.eq[i].irq = entries[i].vector;
  1333. dev->flags |= MLX4_FLAG_MSI_X;
  1334. kfree(entries);
  1335. return;
  1336. }
  1337. no_msi:
  1338. dev->caps.num_comp_vectors = 1;
  1339. dev->caps.comp_pool = 0;
  1340. for (i = 0; i < 2; ++i)
  1341. priv->eq_table.eq[i].irq = dev->pdev->irq;
  1342. }
  1343. static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
  1344. {
  1345. struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
  1346. int err = 0;
  1347. info->dev = dev;
  1348. info->port = port;
  1349. if (!mlx4_is_slave(dev)) {
  1350. INIT_RADIX_TREE(&info->mac_tree, GFP_KERNEL);
  1351. mlx4_init_mac_table(dev, &info->mac_table);
  1352. mlx4_init_vlan_table(dev, &info->vlan_table);
  1353. info->base_qpn =
  1354. dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
  1355. (port - 1) * (1 << log_num_mac);
  1356. }
  1357. sprintf(info->dev_name, "mlx4_port%d", port);
  1358. info->port_attr.attr.name = info->dev_name;
  1359. if (mlx4_is_mfunc(dev))
  1360. info->port_attr.attr.mode = S_IRUGO;
  1361. else {
  1362. info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
  1363. info->port_attr.store = set_port_type;
  1364. }
  1365. info->port_attr.show = show_port_type;
  1366. sysfs_attr_init(&info->port_attr.attr);
  1367. err = device_create_file(&dev->pdev->dev, &info->port_attr);
  1368. if (err) {
  1369. mlx4_err(dev, "Failed to create file for port %d\n", port);
  1370. info->port = -1;
  1371. }
  1372. sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
  1373. info->port_mtu_attr.attr.name = info->dev_mtu_name;
  1374. if (mlx4_is_mfunc(dev))
  1375. info->port_mtu_attr.attr.mode = S_IRUGO;
  1376. else {
  1377. info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
  1378. info->port_mtu_attr.store = set_port_ib_mtu;
  1379. }
  1380. info->port_mtu_attr.show = show_port_ib_mtu;
  1381. sysfs_attr_init(&info->port_mtu_attr.attr);
  1382. err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
  1383. if (err) {
  1384. mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
  1385. device_remove_file(&info->dev->pdev->dev, &info->port_attr);
  1386. info->port = -1;
  1387. }
  1388. return err;
  1389. }
  1390. static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
  1391. {
  1392. if (info->port < 0)
  1393. return;
  1394. device_remove_file(&info->dev->pdev->dev, &info->port_attr);
  1395. device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
  1396. }
  1397. static int mlx4_init_steering(struct mlx4_dev *dev)
  1398. {
  1399. struct mlx4_priv *priv = mlx4_priv(dev);
  1400. int num_entries = dev->caps.num_ports;
  1401. int i, j;
  1402. priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
  1403. if (!priv->steer)
  1404. return -ENOMEM;
  1405. for (i = 0; i < num_entries; i++)
  1406. for (j = 0; j < MLX4_NUM_STEERS; j++) {
  1407. INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
  1408. INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
  1409. }
  1410. return 0;
  1411. }
  1412. static void mlx4_clear_steering(struct mlx4_dev *dev)
  1413. {
  1414. struct mlx4_priv *priv = mlx4_priv(dev);
  1415. struct mlx4_steer_index *entry, *tmp_entry;
  1416. struct mlx4_promisc_qp *pqp, *tmp_pqp;
  1417. int num_entries = dev->caps.num_ports;
  1418. int i, j;
  1419. for (i = 0; i < num_entries; i++) {
  1420. for (j = 0; j < MLX4_NUM_STEERS; j++) {
  1421. list_for_each_entry_safe(pqp, tmp_pqp,
  1422. &priv->steer[i].promisc_qps[j],
  1423. list) {
  1424. list_del(&pqp->list);
  1425. kfree(pqp);
  1426. }
  1427. list_for_each_entry_safe(entry, tmp_entry,
  1428. &priv->steer[i].steer_entries[j],
  1429. list) {
  1430. list_del(&entry->list);
  1431. list_for_each_entry_safe(pqp, tmp_pqp,
  1432. &entry->duplicates,
  1433. list) {
  1434. list_del(&pqp->list);
  1435. kfree(pqp);
  1436. }
  1437. kfree(entry);
  1438. }
  1439. }
  1440. }
  1441. kfree(priv->steer);
  1442. }
  1443. static int extended_func_num(struct pci_dev *pdev)
  1444. {
  1445. return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
  1446. }
  1447. #define MLX4_OWNER_BASE 0x8069c
  1448. #define MLX4_OWNER_SIZE 4
  1449. static int mlx4_get_ownership(struct mlx4_dev *dev)
  1450. {
  1451. void __iomem *owner;
  1452. u32 ret;
  1453. owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
  1454. MLX4_OWNER_SIZE);
  1455. if (!owner) {
  1456. mlx4_err(dev, "Failed to obtain ownership bit\n");
  1457. return -ENOMEM;
  1458. }
  1459. ret = readl(owner);
  1460. iounmap(owner);
  1461. return (int) !!ret;
  1462. }
  1463. static void mlx4_free_ownership(struct mlx4_dev *dev)
  1464. {
  1465. void __iomem *owner;
  1466. owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
  1467. MLX4_OWNER_SIZE);
  1468. if (!owner) {
  1469. mlx4_err(dev, "Failed to obtain ownership bit\n");
  1470. return;
  1471. }
  1472. writel(0, owner);
  1473. msleep(1000);
  1474. iounmap(owner);
  1475. }
  1476. static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
  1477. {
  1478. struct mlx4_priv *priv;
  1479. struct mlx4_dev *dev;
  1480. int err;
  1481. int port;
  1482. pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
  1483. err = pci_enable_device(pdev);
  1484. if (err) {
  1485. dev_err(&pdev->dev, "Cannot enable PCI device, "
  1486. "aborting.\n");
  1487. return err;
  1488. }
  1489. if (num_vfs > MLX4_MAX_NUM_VF) {
  1490. printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n",
  1491. num_vfs, MLX4_MAX_NUM_VF);
  1492. return -EINVAL;
  1493. }
  1494. /*
  1495. * Check for BARs.
  1496. */
  1497. if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
  1498. !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
  1499. dev_err(&pdev->dev, "Missing DCS, aborting."
  1500. "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
  1501. pci_dev_data, pci_resource_flags(pdev, 0));
  1502. err = -ENODEV;
  1503. goto err_disable_pdev;
  1504. }
  1505. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  1506. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  1507. err = -ENODEV;
  1508. goto err_disable_pdev;
  1509. }
  1510. err = pci_request_regions(pdev, DRV_NAME);
  1511. if (err) {
  1512. dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
  1513. goto err_disable_pdev;
  1514. }
  1515. pci_set_master(pdev);
  1516. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  1517. if (err) {
  1518. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  1519. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  1520. if (err) {
  1521. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  1522. goto err_release_regions;
  1523. }
  1524. }
  1525. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
  1526. if (err) {
  1527. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  1528. "consistent PCI DMA mask.\n");
  1529. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  1530. if (err) {
  1531. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  1532. "aborting.\n");
  1533. goto err_release_regions;
  1534. }
  1535. }
  1536. /* Allow large DMA segments, up to the firmware limit of 1 GB */
  1537. dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
  1538. dev = pci_get_drvdata(pdev);
  1539. priv = mlx4_priv(dev);
  1540. dev->pdev = pdev;
  1541. INIT_LIST_HEAD(&priv->ctx_list);
  1542. spin_lock_init(&priv->ctx_lock);
  1543. mutex_init(&priv->port_mutex);
  1544. INIT_LIST_HEAD(&priv->pgdir_list);
  1545. mutex_init(&priv->pgdir_mutex);
  1546. INIT_LIST_HEAD(&priv->bf_list);
  1547. mutex_init(&priv->bf_mutex);
  1548. dev->rev_id = pdev->revision;
  1549. /* Detect if this device is a virtual function */
  1550. if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
  1551. /* When acting as pf, we normally skip vfs unless explicitly
  1552. * requested to probe them. */
  1553. if (num_vfs && extended_func_num(pdev) > probe_vf) {
  1554. mlx4_warn(dev, "Skipping virtual function:%d\n",
  1555. extended_func_num(pdev));
  1556. err = -ENODEV;
  1557. goto err_free_dev;
  1558. }
  1559. mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
  1560. dev->flags |= MLX4_FLAG_SLAVE;
  1561. } else {
  1562. /* We reset the device and enable SRIOV only for physical
  1563. * devices. Try to claim ownership on the device;
  1564. * if already taken, skip -- do not allow multiple PFs */
  1565. err = mlx4_get_ownership(dev);
  1566. if (err) {
  1567. if (err < 0)
  1568. goto err_free_dev;
  1569. else {
  1570. mlx4_warn(dev, "Multiple PFs not yet supported."
  1571. " Skipping PF.\n");
  1572. err = -EINVAL;
  1573. goto err_free_dev;
  1574. }
  1575. }
  1576. if (num_vfs) {
  1577. mlx4_warn(dev, "Enabling sriov with:%d vfs\n", num_vfs);
  1578. err = pci_enable_sriov(pdev, num_vfs);
  1579. if (err) {
  1580. mlx4_err(dev, "Failed to enable sriov,"
  1581. "continuing without sriov enabled"
  1582. " (err = %d).\n", err);
  1583. num_vfs = 0;
  1584. err = 0;
  1585. } else {
  1586. mlx4_warn(dev, "Running in master mode\n");
  1587. dev->flags |= MLX4_FLAG_SRIOV |
  1588. MLX4_FLAG_MASTER;
  1589. dev->num_vfs = num_vfs;
  1590. }
  1591. }
  1592. /*
  1593. * Now reset the HCA before we touch the PCI capabilities or
  1594. * attempt a firmware command, since a boot ROM may have left
  1595. * the HCA in an undefined state.
  1596. */
  1597. err = mlx4_reset(dev);
  1598. if (err) {
  1599. mlx4_err(dev, "Failed to reset HCA, aborting.\n");
  1600. goto err_rel_own;
  1601. }
  1602. }
  1603. slave_start:
  1604. if (mlx4_cmd_init(dev)) {
  1605. mlx4_err(dev, "Failed to init command interface, aborting.\n");
  1606. goto err_sriov;
  1607. }
  1608. /* In slave functions, the communication channel must be initialized
  1609. * before posting commands. Also, init num_slaves before calling
  1610. * mlx4_init_hca */
  1611. if (mlx4_is_mfunc(dev)) {
  1612. if (mlx4_is_master(dev))
  1613. dev->num_slaves = MLX4_MAX_NUM_SLAVES;
  1614. else {
  1615. dev->num_slaves = 0;
  1616. if (mlx4_multi_func_init(dev)) {
  1617. mlx4_err(dev, "Failed to init slave mfunc"
  1618. " interface, aborting.\n");
  1619. goto err_cmd;
  1620. }
  1621. }
  1622. }
  1623. err = mlx4_init_hca(dev);
  1624. if (err) {
  1625. if (err == -EACCES) {
  1626. /* Not primary Physical function
  1627. * Running in slave mode */
  1628. mlx4_cmd_cleanup(dev);
  1629. dev->flags |= MLX4_FLAG_SLAVE;
  1630. dev->flags &= ~MLX4_FLAG_MASTER;
  1631. goto slave_start;
  1632. } else
  1633. goto err_mfunc;
  1634. }
  1635. /* In master functions, the communication channel must be initialized
  1636. * after obtaining its address from fw */
  1637. if (mlx4_is_master(dev)) {
  1638. if (mlx4_multi_func_init(dev)) {
  1639. mlx4_err(dev, "Failed to init master mfunc"
  1640. "interface, aborting.\n");
  1641. goto err_close;
  1642. }
  1643. }
  1644. err = mlx4_alloc_eq_table(dev);
  1645. if (err)
  1646. goto err_master_mfunc;
  1647. priv->msix_ctl.pool_bm = 0;
  1648. mutex_init(&priv->msix_ctl.pool_lock);
  1649. mlx4_enable_msi_x(dev);
  1650. if ((mlx4_is_mfunc(dev)) &&
  1651. !(dev->flags & MLX4_FLAG_MSI_X)) {
  1652. mlx4_err(dev, "INTx is not supported in multi-function mode."
  1653. " aborting.\n");
  1654. goto err_free_eq;
  1655. }
  1656. if (!mlx4_is_slave(dev)) {
  1657. err = mlx4_init_steering(dev);
  1658. if (err)
  1659. goto err_free_eq;
  1660. }
  1661. err = mlx4_setup_hca(dev);
  1662. if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
  1663. !mlx4_is_mfunc(dev)) {
  1664. dev->flags &= ~MLX4_FLAG_MSI_X;
  1665. pci_disable_msix(pdev);
  1666. err = mlx4_setup_hca(dev);
  1667. }
  1668. if (err)
  1669. goto err_steer;
  1670. for (port = 1; port <= dev->caps.num_ports; port++) {
  1671. err = mlx4_init_port_info(dev, port);
  1672. if (err)
  1673. goto err_port;
  1674. }
  1675. err = mlx4_register_device(dev);
  1676. if (err)
  1677. goto err_port;
  1678. mlx4_sense_init(dev);
  1679. mlx4_start_sense(dev);
  1680. priv->removed = 0;
  1681. return 0;
  1682. err_port:
  1683. for (--port; port >= 1; --port)
  1684. mlx4_cleanup_port_info(&priv->port[port]);
  1685. mlx4_cleanup_counters_table(dev);
  1686. mlx4_cleanup_mcg_table(dev);
  1687. mlx4_cleanup_qp_table(dev);
  1688. mlx4_cleanup_srq_table(dev);
  1689. mlx4_cleanup_cq_table(dev);
  1690. mlx4_cmd_use_polling(dev);
  1691. mlx4_cleanup_eq_table(dev);
  1692. mlx4_cleanup_mr_table(dev);
  1693. mlx4_cleanup_xrcd_table(dev);
  1694. mlx4_cleanup_pd_table(dev);
  1695. mlx4_cleanup_uar_table(dev);
  1696. err_steer:
  1697. if (!mlx4_is_slave(dev))
  1698. mlx4_clear_steering(dev);
  1699. err_free_eq:
  1700. mlx4_free_eq_table(dev);
  1701. err_master_mfunc:
  1702. if (mlx4_is_master(dev))
  1703. mlx4_multi_func_cleanup(dev);
  1704. err_close:
  1705. if (dev->flags & MLX4_FLAG_MSI_X)
  1706. pci_disable_msix(pdev);
  1707. mlx4_close_hca(dev);
  1708. err_mfunc:
  1709. if (mlx4_is_slave(dev))
  1710. mlx4_multi_func_cleanup(dev);
  1711. err_cmd:
  1712. mlx4_cmd_cleanup(dev);
  1713. err_sriov:
  1714. if (num_vfs && (dev->flags & MLX4_FLAG_SRIOV))
  1715. pci_disable_sriov(pdev);
  1716. err_rel_own:
  1717. if (!mlx4_is_slave(dev))
  1718. mlx4_free_ownership(dev);
  1719. err_free_dev:
  1720. kfree(priv);
  1721. err_release_regions:
  1722. pci_release_regions(pdev);
  1723. err_disable_pdev:
  1724. pci_disable_device(pdev);
  1725. pci_set_drvdata(pdev, NULL);
  1726. return err;
  1727. }
  1728. static int __devinit mlx4_init_one(struct pci_dev *pdev,
  1729. const struct pci_device_id *id)
  1730. {
  1731. struct mlx4_priv *priv;
  1732. struct mlx4_dev *dev;
  1733. printk_once(KERN_INFO "%s", mlx4_version);
  1734. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  1735. if (!priv)
  1736. return -ENOMEM;
  1737. dev = &priv->dev;
  1738. pci_set_drvdata(pdev, dev);
  1739. priv->pci_dev_data = id->driver_data;
  1740. return __mlx4_init_one(pdev, id->driver_data);
  1741. }
  1742. static void __mlx4_remove_one(struct pci_dev *pdev)
  1743. {
  1744. struct mlx4_dev *dev = pci_get_drvdata(pdev);
  1745. struct mlx4_priv *priv = mlx4_priv(dev);
  1746. int pci_dev_data;
  1747. int p;
  1748. if (priv->removed)
  1749. return;
  1750. pci_dev_data = priv->pci_dev_data;
  1751. /* in SRIOV it is not allowed to unload the pf's
  1752. * driver while there are alive vf's */
  1753. if (mlx4_is_master(dev)) {
  1754. if (mlx4_how_many_lives_vf(dev))
  1755. printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
  1756. }
  1757. mlx4_stop_sense(dev);
  1758. mlx4_unregister_device(dev);
  1759. for (p = 1; p <= dev->caps.num_ports; p++) {
  1760. mlx4_cleanup_port_info(&priv->port[p]);
  1761. mlx4_CLOSE_PORT(dev, p);
  1762. }
  1763. mlx4_cleanup_counters_table(dev);
  1764. mlx4_cleanup_mcg_table(dev);
  1765. mlx4_cleanup_qp_table(dev);
  1766. mlx4_cleanup_srq_table(dev);
  1767. mlx4_cleanup_cq_table(dev);
  1768. mlx4_cmd_use_polling(dev);
  1769. mlx4_cleanup_eq_table(dev);
  1770. mlx4_cleanup_mr_table(dev);
  1771. mlx4_cleanup_xrcd_table(dev);
  1772. mlx4_cleanup_pd_table(dev);
  1773. if (mlx4_is_master(dev))
  1774. mlx4_free_resource_tracker(dev);
  1775. iounmap(priv->kar);
  1776. mlx4_uar_free(dev, &priv->driver_uar);
  1777. mlx4_cleanup_uar_table(dev);
  1778. if (!mlx4_is_slave(dev))
  1779. mlx4_clear_steering(dev);
  1780. mlx4_free_eq_table(dev);
  1781. if (mlx4_is_master(dev))
  1782. mlx4_multi_func_cleanup(dev);
  1783. mlx4_close_hca(dev);
  1784. if (mlx4_is_slave(dev))
  1785. mlx4_multi_func_cleanup(dev);
  1786. mlx4_cmd_cleanup(dev);
  1787. if (dev->flags & MLX4_FLAG_MSI_X)
  1788. pci_disable_msix(pdev);
  1789. if (num_vfs && (dev->flags & MLX4_FLAG_SRIOV)) {
  1790. mlx4_warn(dev, "Disabling sriov\n");
  1791. pci_disable_sriov(pdev);
  1792. }
  1793. if (!mlx4_is_slave(dev))
  1794. mlx4_free_ownership(dev);
  1795. pci_release_regions(pdev);
  1796. pci_disable_device(pdev);
  1797. memset(priv, 0, sizeof(*priv));
  1798. priv->pci_dev_data = pci_dev_data;
  1799. priv->removed = 1;
  1800. }
  1801. static void mlx4_remove_one(struct pci_dev *pdev)
  1802. {
  1803. struct mlx4_dev *dev = pci_get_drvdata(pdev);
  1804. struct mlx4_priv *priv = mlx4_priv(dev);
  1805. __mlx4_remove_one(pdev);
  1806. kfree(priv);
  1807. pci_set_drvdata(pdev, NULL);
  1808. }
  1809. int mlx4_restart_one(struct pci_dev *pdev)
  1810. {
  1811. struct mlx4_dev *dev = pci_get_drvdata(pdev);
  1812. struct mlx4_priv *priv = mlx4_priv(dev);
  1813. int pci_dev_data;
  1814. pci_dev_data = priv->pci_dev_data;
  1815. __mlx4_remove_one(pdev);
  1816. return __mlx4_init_one(pdev, pci_dev_data);
  1817. }
  1818. static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
  1819. /* MT25408 "Hermon" SDR */
  1820. { PCI_VDEVICE(MELLANOX, 0x6340), 0 },
  1821. /* MT25408 "Hermon" DDR */
  1822. { PCI_VDEVICE(MELLANOX, 0x634a), 0 },
  1823. /* MT25408 "Hermon" QDR */
  1824. { PCI_VDEVICE(MELLANOX, 0x6354), 0 },
  1825. /* MT25408 "Hermon" DDR PCIe gen2 */
  1826. { PCI_VDEVICE(MELLANOX, 0x6732), 0 },
  1827. /* MT25408 "Hermon" QDR PCIe gen2 */
  1828. { PCI_VDEVICE(MELLANOX, 0x673c), 0 },
  1829. /* MT25408 "Hermon" EN 10GigE */
  1830. { PCI_VDEVICE(MELLANOX, 0x6368), 0 },
  1831. /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
  1832. { PCI_VDEVICE(MELLANOX, 0x6750), 0 },
  1833. /* MT25458 ConnectX EN 10GBASE-T 10GigE */
  1834. { PCI_VDEVICE(MELLANOX, 0x6372), 0 },
  1835. /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
  1836. { PCI_VDEVICE(MELLANOX, 0x675a), 0 },
  1837. /* MT26468 ConnectX EN 10GigE PCIe gen2*/
  1838. { PCI_VDEVICE(MELLANOX, 0x6764), 0 },
  1839. /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
  1840. { PCI_VDEVICE(MELLANOX, 0x6746), 0 },
  1841. /* MT26478 ConnectX2 40GigE PCIe gen2 */
  1842. { PCI_VDEVICE(MELLANOX, 0x676e), 0 },
  1843. /* MT25400 Family [ConnectX-2 Virtual Function] */
  1844. { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
  1845. /* MT27500 Family [ConnectX-3] */
  1846. { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
  1847. /* MT27500 Family [ConnectX-3 Virtual Function] */
  1848. { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
  1849. { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
  1850. { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
  1851. { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
  1852. { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
  1853. { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
  1854. { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
  1855. { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
  1856. { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
  1857. { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
  1858. { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
  1859. { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
  1860. { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
  1861. { 0, }
  1862. };
  1863. MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
  1864. static struct pci_driver mlx4_driver = {
  1865. .name = DRV_NAME,
  1866. .id_table = mlx4_pci_table,
  1867. .probe = mlx4_init_one,
  1868. .remove = __devexit_p(mlx4_remove_one)
  1869. };
  1870. static int __init mlx4_verify_params(void)
  1871. {
  1872. if ((log_num_mac < 0) || (log_num_mac > 7)) {
  1873. pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
  1874. return -1;
  1875. }
  1876. if (log_num_vlan != 0)
  1877. pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
  1878. MLX4_LOG_NUM_VLANS);
  1879. if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
  1880. pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
  1881. return -1;
  1882. }
  1883. /* Check if module param for ports type has legal combination */
  1884. if (port_type_array[0] == false && port_type_array[1] == true) {
  1885. printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
  1886. port_type_array[0] = true;
  1887. }
  1888. return 0;
  1889. }
  1890. static int __init mlx4_init(void)
  1891. {
  1892. int ret;
  1893. if (mlx4_verify_params())
  1894. return -EINVAL;
  1895. mlx4_catas_init();
  1896. mlx4_wq = create_singlethread_workqueue("mlx4");
  1897. if (!mlx4_wq)
  1898. return -ENOMEM;
  1899. ret = pci_register_driver(&mlx4_driver);
  1900. return ret < 0 ? ret : 0;
  1901. }
  1902. static void __exit mlx4_cleanup(void)
  1903. {
  1904. pci_unregister_driver(&mlx4_driver);
  1905. destroy_workqueue(mlx4_wq);
  1906. }
  1907. module_init(mlx4_init);
  1908. module_exit(mlx4_cleanup);