cmd.c 44 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
  4. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. */
  34. #include <linux/sched.h>
  35. #include <linux/slab.h>
  36. #include <linux/export.h>
  37. #include <linux/pci.h>
  38. #include <linux/errno.h>
  39. #include <linux/mlx4/cmd.h>
  40. #include <linux/semaphore.h>
  41. #include <asm/io.h>
  42. #include "mlx4.h"
  43. #include "fw.h"
  44. #define CMD_POLL_TOKEN 0xffff
  45. #define INBOX_MASK 0xffffffffffffff00ULL
  46. #define CMD_CHAN_VER 1
  47. #define CMD_CHAN_IF_REV 1
  48. enum {
  49. /* command completed successfully: */
  50. CMD_STAT_OK = 0x00,
  51. /* Internal error (such as a bus error) occurred while processing command: */
  52. CMD_STAT_INTERNAL_ERR = 0x01,
  53. /* Operation/command not supported or opcode modifier not supported: */
  54. CMD_STAT_BAD_OP = 0x02,
  55. /* Parameter not supported or parameter out of range: */
  56. CMD_STAT_BAD_PARAM = 0x03,
  57. /* System not enabled or bad system state: */
  58. CMD_STAT_BAD_SYS_STATE = 0x04,
  59. /* Attempt to access reserved or unallocaterd resource: */
  60. CMD_STAT_BAD_RESOURCE = 0x05,
  61. /* Requested resource is currently executing a command, or is otherwise busy: */
  62. CMD_STAT_RESOURCE_BUSY = 0x06,
  63. /* Required capability exceeds device limits: */
  64. CMD_STAT_EXCEED_LIM = 0x08,
  65. /* Resource is not in the appropriate state or ownership: */
  66. CMD_STAT_BAD_RES_STATE = 0x09,
  67. /* Index out of range: */
  68. CMD_STAT_BAD_INDEX = 0x0a,
  69. /* FW image corrupted: */
  70. CMD_STAT_BAD_NVMEM = 0x0b,
  71. /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
  72. CMD_STAT_ICM_ERROR = 0x0c,
  73. /* Attempt to modify a QP/EE which is not in the presumed state: */
  74. CMD_STAT_BAD_QP_STATE = 0x10,
  75. /* Bad segment parameters (Address/Size): */
  76. CMD_STAT_BAD_SEG_PARAM = 0x20,
  77. /* Memory Region has Memory Windows bound to: */
  78. CMD_STAT_REG_BOUND = 0x21,
  79. /* HCA local attached memory not present: */
  80. CMD_STAT_LAM_NOT_PRE = 0x22,
  81. /* Bad management packet (silently discarded): */
  82. CMD_STAT_BAD_PKT = 0x30,
  83. /* More outstanding CQEs in CQ than new CQ size: */
  84. CMD_STAT_BAD_SIZE = 0x40,
  85. /* Multi Function device support required: */
  86. CMD_STAT_MULTI_FUNC_REQ = 0x50,
  87. };
  88. enum {
  89. HCR_IN_PARAM_OFFSET = 0x00,
  90. HCR_IN_MODIFIER_OFFSET = 0x08,
  91. HCR_OUT_PARAM_OFFSET = 0x0c,
  92. HCR_TOKEN_OFFSET = 0x14,
  93. HCR_STATUS_OFFSET = 0x18,
  94. HCR_OPMOD_SHIFT = 12,
  95. HCR_T_BIT = 21,
  96. HCR_E_BIT = 22,
  97. HCR_GO_BIT = 23
  98. };
  99. enum {
  100. GO_BIT_TIMEOUT_MSECS = 10000
  101. };
  102. struct mlx4_cmd_context {
  103. struct completion done;
  104. int result;
  105. int next;
  106. u64 out_param;
  107. u16 token;
  108. u8 fw_status;
  109. };
  110. static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
  111. struct mlx4_vhcr_cmd *in_vhcr);
  112. static int mlx4_status_to_errno(u8 status)
  113. {
  114. static const int trans_table[] = {
  115. [CMD_STAT_INTERNAL_ERR] = -EIO,
  116. [CMD_STAT_BAD_OP] = -EPERM,
  117. [CMD_STAT_BAD_PARAM] = -EINVAL,
  118. [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
  119. [CMD_STAT_BAD_RESOURCE] = -EBADF,
  120. [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
  121. [CMD_STAT_EXCEED_LIM] = -ENOMEM,
  122. [CMD_STAT_BAD_RES_STATE] = -EBADF,
  123. [CMD_STAT_BAD_INDEX] = -EBADF,
  124. [CMD_STAT_BAD_NVMEM] = -EFAULT,
  125. [CMD_STAT_ICM_ERROR] = -ENFILE,
  126. [CMD_STAT_BAD_QP_STATE] = -EINVAL,
  127. [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
  128. [CMD_STAT_REG_BOUND] = -EBUSY,
  129. [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
  130. [CMD_STAT_BAD_PKT] = -EINVAL,
  131. [CMD_STAT_BAD_SIZE] = -ENOMEM,
  132. [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
  133. };
  134. if (status >= ARRAY_SIZE(trans_table) ||
  135. (status != CMD_STAT_OK && trans_table[status] == 0))
  136. return -EIO;
  137. return trans_table[status];
  138. }
  139. static u8 mlx4_errno_to_status(int errno)
  140. {
  141. switch (errno) {
  142. case -EPERM:
  143. return CMD_STAT_BAD_OP;
  144. case -EINVAL:
  145. return CMD_STAT_BAD_PARAM;
  146. case -ENXIO:
  147. return CMD_STAT_BAD_SYS_STATE;
  148. case -EBUSY:
  149. return CMD_STAT_RESOURCE_BUSY;
  150. case -ENOMEM:
  151. return CMD_STAT_EXCEED_LIM;
  152. case -ENFILE:
  153. return CMD_STAT_ICM_ERROR;
  154. default:
  155. return CMD_STAT_INTERNAL_ERR;
  156. }
  157. }
  158. static int comm_pending(struct mlx4_dev *dev)
  159. {
  160. struct mlx4_priv *priv = mlx4_priv(dev);
  161. u32 status = readl(&priv->mfunc.comm->slave_read);
  162. return (swab32(status) >> 31) != priv->cmd.comm_toggle;
  163. }
  164. static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
  165. {
  166. struct mlx4_priv *priv = mlx4_priv(dev);
  167. u32 val;
  168. priv->cmd.comm_toggle ^= 1;
  169. val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
  170. __raw_writel((__force u32) cpu_to_be32(val),
  171. &priv->mfunc.comm->slave_write);
  172. mmiowb();
  173. }
  174. static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
  175. unsigned long timeout)
  176. {
  177. struct mlx4_priv *priv = mlx4_priv(dev);
  178. unsigned long end;
  179. int err = 0;
  180. int ret_from_pending = 0;
  181. /* First, verify that the master reports correct status */
  182. if (comm_pending(dev)) {
  183. mlx4_warn(dev, "Communication channel is not idle."
  184. "my toggle is %d (cmd:0x%x)\n",
  185. priv->cmd.comm_toggle, cmd);
  186. return -EAGAIN;
  187. }
  188. /* Write command */
  189. down(&priv->cmd.poll_sem);
  190. mlx4_comm_cmd_post(dev, cmd, param);
  191. end = msecs_to_jiffies(timeout) + jiffies;
  192. while (comm_pending(dev) && time_before(jiffies, end))
  193. cond_resched();
  194. ret_from_pending = comm_pending(dev);
  195. if (ret_from_pending) {
  196. /* check if the slave is trying to boot in the middle of
  197. * FLR process. The only non-zero result in the RESET command
  198. * is MLX4_DELAY_RESET_SLAVE*/
  199. if ((MLX4_COMM_CMD_RESET == cmd)) {
  200. mlx4_warn(dev, "Got slave FLRed from Communication"
  201. " channel (ret:0x%x)\n", ret_from_pending);
  202. err = MLX4_DELAY_RESET_SLAVE;
  203. } else {
  204. mlx4_warn(dev, "Communication channel timed out\n");
  205. err = -ETIMEDOUT;
  206. }
  207. }
  208. up(&priv->cmd.poll_sem);
  209. return err;
  210. }
  211. static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
  212. u16 param, unsigned long timeout)
  213. {
  214. struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
  215. struct mlx4_cmd_context *context;
  216. unsigned long end;
  217. int err = 0;
  218. down(&cmd->event_sem);
  219. spin_lock(&cmd->context_lock);
  220. BUG_ON(cmd->free_head < 0);
  221. context = &cmd->context[cmd->free_head];
  222. context->token += cmd->token_mask + 1;
  223. cmd->free_head = context->next;
  224. spin_unlock(&cmd->context_lock);
  225. init_completion(&context->done);
  226. mlx4_comm_cmd_post(dev, op, param);
  227. if (!wait_for_completion_timeout(&context->done,
  228. msecs_to_jiffies(timeout))) {
  229. err = -EBUSY;
  230. goto out;
  231. }
  232. err = context->result;
  233. if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
  234. mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
  235. op, context->fw_status);
  236. goto out;
  237. }
  238. out:
  239. /* wait for comm channel ready
  240. * this is necessary for prevention the race
  241. * when switching between event to polling mode
  242. */
  243. end = msecs_to_jiffies(timeout) + jiffies;
  244. while (comm_pending(dev) && time_before(jiffies, end))
  245. cond_resched();
  246. spin_lock(&cmd->context_lock);
  247. context->next = cmd->free_head;
  248. cmd->free_head = context - cmd->context;
  249. spin_unlock(&cmd->context_lock);
  250. up(&cmd->event_sem);
  251. return err;
  252. }
  253. int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
  254. unsigned long timeout)
  255. {
  256. if (mlx4_priv(dev)->cmd.use_events)
  257. return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
  258. return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
  259. }
  260. static int cmd_pending(struct mlx4_dev *dev)
  261. {
  262. u32 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
  263. return (status & swab32(1 << HCR_GO_BIT)) ||
  264. (mlx4_priv(dev)->cmd.toggle ==
  265. !!(status & swab32(1 << HCR_T_BIT)));
  266. }
  267. static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
  268. u32 in_modifier, u8 op_modifier, u16 op, u16 token,
  269. int event)
  270. {
  271. struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
  272. u32 __iomem *hcr = cmd->hcr;
  273. int ret = -EAGAIN;
  274. unsigned long end;
  275. mutex_lock(&cmd->hcr_mutex);
  276. end = jiffies;
  277. if (event)
  278. end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
  279. while (cmd_pending(dev)) {
  280. if (time_after_eq(jiffies, end)) {
  281. mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
  282. goto out;
  283. }
  284. cond_resched();
  285. }
  286. /*
  287. * We use writel (instead of something like memcpy_toio)
  288. * because writes of less than 32 bits to the HCR don't work
  289. * (and some architectures such as ia64 implement memcpy_toio
  290. * in terms of writeb).
  291. */
  292. __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
  293. __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
  294. __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
  295. __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
  296. __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
  297. __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
  298. /* __raw_writel may not order writes. */
  299. wmb();
  300. __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
  301. (cmd->toggle << HCR_T_BIT) |
  302. (event ? (1 << HCR_E_BIT) : 0) |
  303. (op_modifier << HCR_OPMOD_SHIFT) |
  304. op), hcr + 6);
  305. /*
  306. * Make sure that our HCR writes don't get mixed in with
  307. * writes from another CPU starting a FW command.
  308. */
  309. mmiowb();
  310. cmd->toggle = cmd->toggle ^ 1;
  311. ret = 0;
  312. out:
  313. mutex_unlock(&cmd->hcr_mutex);
  314. return ret;
  315. }
  316. static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
  317. int out_is_imm, u32 in_modifier, u8 op_modifier,
  318. u16 op, unsigned long timeout)
  319. {
  320. struct mlx4_priv *priv = mlx4_priv(dev);
  321. struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
  322. int ret;
  323. down(&priv->cmd.slave_sem);
  324. vhcr->in_param = cpu_to_be64(in_param);
  325. vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
  326. vhcr->in_modifier = cpu_to_be32(in_modifier);
  327. vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
  328. vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
  329. vhcr->status = 0;
  330. vhcr->flags = !!(priv->cmd.use_events) << 6;
  331. if (mlx4_is_master(dev)) {
  332. ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
  333. if (!ret) {
  334. if (out_is_imm) {
  335. if (out_param)
  336. *out_param =
  337. be64_to_cpu(vhcr->out_param);
  338. else {
  339. mlx4_err(dev, "response expected while"
  340. "output mailbox is NULL for "
  341. "command 0x%x\n", op);
  342. vhcr->status = CMD_STAT_BAD_PARAM;
  343. }
  344. }
  345. ret = mlx4_status_to_errno(vhcr->status);
  346. }
  347. } else {
  348. ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
  349. MLX4_COMM_TIME + timeout);
  350. if (!ret) {
  351. if (out_is_imm) {
  352. if (out_param)
  353. *out_param =
  354. be64_to_cpu(vhcr->out_param);
  355. else {
  356. mlx4_err(dev, "response expected while"
  357. "output mailbox is NULL for "
  358. "command 0x%x\n", op);
  359. vhcr->status = CMD_STAT_BAD_PARAM;
  360. }
  361. }
  362. ret = mlx4_status_to_errno(vhcr->status);
  363. } else
  364. mlx4_err(dev, "failed execution of VHCR_POST command"
  365. "opcode 0x%x\n", op);
  366. }
  367. up(&priv->cmd.slave_sem);
  368. return ret;
  369. }
  370. static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
  371. int out_is_imm, u32 in_modifier, u8 op_modifier,
  372. u16 op, unsigned long timeout)
  373. {
  374. struct mlx4_priv *priv = mlx4_priv(dev);
  375. void __iomem *hcr = priv->cmd.hcr;
  376. int err = 0;
  377. unsigned long end;
  378. u32 stat;
  379. down(&priv->cmd.poll_sem);
  380. err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
  381. in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
  382. if (err)
  383. goto out;
  384. end = msecs_to_jiffies(timeout) + jiffies;
  385. while (cmd_pending(dev) && time_before(jiffies, end))
  386. cond_resched();
  387. if (cmd_pending(dev)) {
  388. err = -ETIMEDOUT;
  389. goto out;
  390. }
  391. if (out_is_imm)
  392. *out_param =
  393. (u64) be32_to_cpu((__force __be32)
  394. __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
  395. (u64) be32_to_cpu((__force __be32)
  396. __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
  397. stat = be32_to_cpu((__force __be32)
  398. __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
  399. err = mlx4_status_to_errno(stat);
  400. if (err)
  401. mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
  402. op, stat);
  403. out:
  404. up(&priv->cmd.poll_sem);
  405. return err;
  406. }
  407. void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
  408. {
  409. struct mlx4_priv *priv = mlx4_priv(dev);
  410. struct mlx4_cmd_context *context =
  411. &priv->cmd.context[token & priv->cmd.token_mask];
  412. /* previously timed out command completing at long last */
  413. if (token != context->token)
  414. return;
  415. context->fw_status = status;
  416. context->result = mlx4_status_to_errno(status);
  417. context->out_param = out_param;
  418. complete(&context->done);
  419. }
  420. static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
  421. int out_is_imm, u32 in_modifier, u8 op_modifier,
  422. u16 op, unsigned long timeout)
  423. {
  424. struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
  425. struct mlx4_cmd_context *context;
  426. int err = 0;
  427. down(&cmd->event_sem);
  428. spin_lock(&cmd->context_lock);
  429. BUG_ON(cmd->free_head < 0);
  430. context = &cmd->context[cmd->free_head];
  431. context->token += cmd->token_mask + 1;
  432. cmd->free_head = context->next;
  433. spin_unlock(&cmd->context_lock);
  434. init_completion(&context->done);
  435. mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
  436. in_modifier, op_modifier, op, context->token, 1);
  437. if (!wait_for_completion_timeout(&context->done,
  438. msecs_to_jiffies(timeout))) {
  439. err = -EBUSY;
  440. goto out;
  441. }
  442. err = context->result;
  443. if (err) {
  444. mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
  445. op, context->fw_status);
  446. goto out;
  447. }
  448. if (out_is_imm)
  449. *out_param = context->out_param;
  450. out:
  451. spin_lock(&cmd->context_lock);
  452. context->next = cmd->free_head;
  453. cmd->free_head = context - cmd->context;
  454. spin_unlock(&cmd->context_lock);
  455. up(&cmd->event_sem);
  456. return err;
  457. }
  458. int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
  459. int out_is_imm, u32 in_modifier, u8 op_modifier,
  460. u16 op, unsigned long timeout, int native)
  461. {
  462. if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
  463. if (mlx4_priv(dev)->cmd.use_events)
  464. return mlx4_cmd_wait(dev, in_param, out_param,
  465. out_is_imm, in_modifier,
  466. op_modifier, op, timeout);
  467. else
  468. return mlx4_cmd_poll(dev, in_param, out_param,
  469. out_is_imm, in_modifier,
  470. op_modifier, op, timeout);
  471. }
  472. return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
  473. in_modifier, op_modifier, op, timeout);
  474. }
  475. EXPORT_SYMBOL_GPL(__mlx4_cmd);
  476. static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
  477. {
  478. return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
  479. MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
  480. }
  481. static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
  482. int slave, u64 slave_addr,
  483. int size, int is_read)
  484. {
  485. u64 in_param;
  486. u64 out_param;
  487. if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
  488. (slave & ~0x7f) | (size & 0xff)) {
  489. mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx "
  490. "master_addr:0x%llx slave_id:%d size:%d\n",
  491. slave_addr, master_addr, slave, size);
  492. return -EINVAL;
  493. }
  494. if (is_read) {
  495. in_param = (u64) slave | slave_addr;
  496. out_param = (u64) dev->caps.function | master_addr;
  497. } else {
  498. in_param = (u64) dev->caps.function | master_addr;
  499. out_param = (u64) slave | slave_addr;
  500. }
  501. return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
  502. MLX4_CMD_ACCESS_MEM,
  503. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  504. }
  505. int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
  506. struct mlx4_vhcr *vhcr,
  507. struct mlx4_cmd_mailbox *inbox,
  508. struct mlx4_cmd_mailbox *outbox,
  509. struct mlx4_cmd_info *cmd)
  510. {
  511. u64 in_param;
  512. u64 out_param;
  513. int err;
  514. in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
  515. out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
  516. if (cmd->encode_slave_id) {
  517. in_param &= 0xffffffffffffff00ll;
  518. in_param |= slave;
  519. }
  520. err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
  521. vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
  522. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  523. if (cmd->out_is_imm)
  524. vhcr->out_param = out_param;
  525. return err;
  526. }
  527. static struct mlx4_cmd_info cmd_info[] = {
  528. {
  529. .opcode = MLX4_CMD_QUERY_FW,
  530. .has_inbox = false,
  531. .has_outbox = true,
  532. .out_is_imm = false,
  533. .encode_slave_id = false,
  534. .verify = NULL,
  535. .wrapper = NULL
  536. },
  537. {
  538. .opcode = MLX4_CMD_QUERY_HCA,
  539. .has_inbox = false,
  540. .has_outbox = true,
  541. .out_is_imm = false,
  542. .encode_slave_id = false,
  543. .verify = NULL,
  544. .wrapper = NULL
  545. },
  546. {
  547. .opcode = MLX4_CMD_QUERY_DEV_CAP,
  548. .has_inbox = false,
  549. .has_outbox = true,
  550. .out_is_imm = false,
  551. .encode_slave_id = false,
  552. .verify = NULL,
  553. .wrapper = NULL
  554. },
  555. {
  556. .opcode = MLX4_CMD_QUERY_FUNC_CAP,
  557. .has_inbox = false,
  558. .has_outbox = true,
  559. .out_is_imm = false,
  560. .encode_slave_id = false,
  561. .verify = NULL,
  562. .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
  563. },
  564. {
  565. .opcode = MLX4_CMD_QUERY_ADAPTER,
  566. .has_inbox = false,
  567. .has_outbox = true,
  568. .out_is_imm = false,
  569. .encode_slave_id = false,
  570. .verify = NULL,
  571. .wrapper = NULL
  572. },
  573. {
  574. .opcode = MLX4_CMD_INIT_PORT,
  575. .has_inbox = false,
  576. .has_outbox = false,
  577. .out_is_imm = false,
  578. .encode_slave_id = false,
  579. .verify = NULL,
  580. .wrapper = mlx4_INIT_PORT_wrapper
  581. },
  582. {
  583. .opcode = MLX4_CMD_CLOSE_PORT,
  584. .has_inbox = false,
  585. .has_outbox = false,
  586. .out_is_imm = false,
  587. .encode_slave_id = false,
  588. .verify = NULL,
  589. .wrapper = mlx4_CLOSE_PORT_wrapper
  590. },
  591. {
  592. .opcode = MLX4_CMD_QUERY_PORT,
  593. .has_inbox = false,
  594. .has_outbox = true,
  595. .out_is_imm = false,
  596. .encode_slave_id = false,
  597. .verify = NULL,
  598. .wrapper = mlx4_QUERY_PORT_wrapper
  599. },
  600. {
  601. .opcode = MLX4_CMD_SET_PORT,
  602. .has_inbox = true,
  603. .has_outbox = false,
  604. .out_is_imm = false,
  605. .encode_slave_id = false,
  606. .verify = NULL,
  607. .wrapper = mlx4_SET_PORT_wrapper
  608. },
  609. {
  610. .opcode = MLX4_CMD_MAP_EQ,
  611. .has_inbox = false,
  612. .has_outbox = false,
  613. .out_is_imm = false,
  614. .encode_slave_id = false,
  615. .verify = NULL,
  616. .wrapper = mlx4_MAP_EQ_wrapper
  617. },
  618. {
  619. .opcode = MLX4_CMD_SW2HW_EQ,
  620. .has_inbox = true,
  621. .has_outbox = false,
  622. .out_is_imm = false,
  623. .encode_slave_id = true,
  624. .verify = NULL,
  625. .wrapper = mlx4_SW2HW_EQ_wrapper
  626. },
  627. {
  628. .opcode = MLX4_CMD_HW_HEALTH_CHECK,
  629. .has_inbox = false,
  630. .has_outbox = false,
  631. .out_is_imm = false,
  632. .encode_slave_id = false,
  633. .verify = NULL,
  634. .wrapper = NULL
  635. },
  636. {
  637. .opcode = MLX4_CMD_NOP,
  638. .has_inbox = false,
  639. .has_outbox = false,
  640. .out_is_imm = false,
  641. .encode_slave_id = false,
  642. .verify = NULL,
  643. .wrapper = NULL
  644. },
  645. {
  646. .opcode = MLX4_CMD_ALLOC_RES,
  647. .has_inbox = false,
  648. .has_outbox = false,
  649. .out_is_imm = true,
  650. .encode_slave_id = false,
  651. .verify = NULL,
  652. .wrapper = mlx4_ALLOC_RES_wrapper
  653. },
  654. {
  655. .opcode = MLX4_CMD_FREE_RES,
  656. .has_inbox = false,
  657. .has_outbox = false,
  658. .out_is_imm = false,
  659. .encode_slave_id = false,
  660. .verify = NULL,
  661. .wrapper = mlx4_FREE_RES_wrapper
  662. },
  663. {
  664. .opcode = MLX4_CMD_SW2HW_MPT,
  665. .has_inbox = true,
  666. .has_outbox = false,
  667. .out_is_imm = false,
  668. .encode_slave_id = true,
  669. .verify = NULL,
  670. .wrapper = mlx4_SW2HW_MPT_wrapper
  671. },
  672. {
  673. .opcode = MLX4_CMD_QUERY_MPT,
  674. .has_inbox = false,
  675. .has_outbox = true,
  676. .out_is_imm = false,
  677. .encode_slave_id = false,
  678. .verify = NULL,
  679. .wrapper = mlx4_QUERY_MPT_wrapper
  680. },
  681. {
  682. .opcode = MLX4_CMD_HW2SW_MPT,
  683. .has_inbox = false,
  684. .has_outbox = false,
  685. .out_is_imm = false,
  686. .encode_slave_id = false,
  687. .verify = NULL,
  688. .wrapper = mlx4_HW2SW_MPT_wrapper
  689. },
  690. {
  691. .opcode = MLX4_CMD_READ_MTT,
  692. .has_inbox = false,
  693. .has_outbox = true,
  694. .out_is_imm = false,
  695. .encode_slave_id = false,
  696. .verify = NULL,
  697. .wrapper = NULL
  698. },
  699. {
  700. .opcode = MLX4_CMD_WRITE_MTT,
  701. .has_inbox = true,
  702. .has_outbox = false,
  703. .out_is_imm = false,
  704. .encode_slave_id = false,
  705. .verify = NULL,
  706. .wrapper = mlx4_WRITE_MTT_wrapper
  707. },
  708. {
  709. .opcode = MLX4_CMD_SYNC_TPT,
  710. .has_inbox = true,
  711. .has_outbox = false,
  712. .out_is_imm = false,
  713. .encode_slave_id = false,
  714. .verify = NULL,
  715. .wrapper = NULL
  716. },
  717. {
  718. .opcode = MLX4_CMD_HW2SW_EQ,
  719. .has_inbox = false,
  720. .has_outbox = true,
  721. .out_is_imm = false,
  722. .encode_slave_id = true,
  723. .verify = NULL,
  724. .wrapper = mlx4_HW2SW_EQ_wrapper
  725. },
  726. {
  727. .opcode = MLX4_CMD_QUERY_EQ,
  728. .has_inbox = false,
  729. .has_outbox = true,
  730. .out_is_imm = false,
  731. .encode_slave_id = true,
  732. .verify = NULL,
  733. .wrapper = mlx4_QUERY_EQ_wrapper
  734. },
  735. {
  736. .opcode = MLX4_CMD_SW2HW_CQ,
  737. .has_inbox = true,
  738. .has_outbox = false,
  739. .out_is_imm = false,
  740. .encode_slave_id = true,
  741. .verify = NULL,
  742. .wrapper = mlx4_SW2HW_CQ_wrapper
  743. },
  744. {
  745. .opcode = MLX4_CMD_HW2SW_CQ,
  746. .has_inbox = false,
  747. .has_outbox = false,
  748. .out_is_imm = false,
  749. .encode_slave_id = false,
  750. .verify = NULL,
  751. .wrapper = mlx4_HW2SW_CQ_wrapper
  752. },
  753. {
  754. .opcode = MLX4_CMD_QUERY_CQ,
  755. .has_inbox = false,
  756. .has_outbox = true,
  757. .out_is_imm = false,
  758. .encode_slave_id = false,
  759. .verify = NULL,
  760. .wrapper = mlx4_QUERY_CQ_wrapper
  761. },
  762. {
  763. .opcode = MLX4_CMD_MODIFY_CQ,
  764. .has_inbox = true,
  765. .has_outbox = false,
  766. .out_is_imm = true,
  767. .encode_slave_id = false,
  768. .verify = NULL,
  769. .wrapper = mlx4_MODIFY_CQ_wrapper
  770. },
  771. {
  772. .opcode = MLX4_CMD_SW2HW_SRQ,
  773. .has_inbox = true,
  774. .has_outbox = false,
  775. .out_is_imm = false,
  776. .encode_slave_id = true,
  777. .verify = NULL,
  778. .wrapper = mlx4_SW2HW_SRQ_wrapper
  779. },
  780. {
  781. .opcode = MLX4_CMD_HW2SW_SRQ,
  782. .has_inbox = false,
  783. .has_outbox = false,
  784. .out_is_imm = false,
  785. .encode_slave_id = false,
  786. .verify = NULL,
  787. .wrapper = mlx4_HW2SW_SRQ_wrapper
  788. },
  789. {
  790. .opcode = MLX4_CMD_QUERY_SRQ,
  791. .has_inbox = false,
  792. .has_outbox = true,
  793. .out_is_imm = false,
  794. .encode_slave_id = false,
  795. .verify = NULL,
  796. .wrapper = mlx4_QUERY_SRQ_wrapper
  797. },
  798. {
  799. .opcode = MLX4_CMD_ARM_SRQ,
  800. .has_inbox = false,
  801. .has_outbox = false,
  802. .out_is_imm = false,
  803. .encode_slave_id = false,
  804. .verify = NULL,
  805. .wrapper = mlx4_ARM_SRQ_wrapper
  806. },
  807. {
  808. .opcode = MLX4_CMD_RST2INIT_QP,
  809. .has_inbox = true,
  810. .has_outbox = false,
  811. .out_is_imm = false,
  812. .encode_slave_id = true,
  813. .verify = NULL,
  814. .wrapper = mlx4_RST2INIT_QP_wrapper
  815. },
  816. {
  817. .opcode = MLX4_CMD_INIT2INIT_QP,
  818. .has_inbox = true,
  819. .has_outbox = false,
  820. .out_is_imm = false,
  821. .encode_slave_id = false,
  822. .verify = NULL,
  823. .wrapper = mlx4_GEN_QP_wrapper
  824. },
  825. {
  826. .opcode = MLX4_CMD_INIT2RTR_QP,
  827. .has_inbox = true,
  828. .has_outbox = false,
  829. .out_is_imm = false,
  830. .encode_slave_id = false,
  831. .verify = NULL,
  832. .wrapper = mlx4_INIT2RTR_QP_wrapper
  833. },
  834. {
  835. .opcode = MLX4_CMD_RTR2RTS_QP,
  836. .has_inbox = true,
  837. .has_outbox = false,
  838. .out_is_imm = false,
  839. .encode_slave_id = false,
  840. .verify = NULL,
  841. .wrapper = mlx4_GEN_QP_wrapper
  842. },
  843. {
  844. .opcode = MLX4_CMD_RTS2RTS_QP,
  845. .has_inbox = true,
  846. .has_outbox = false,
  847. .out_is_imm = false,
  848. .encode_slave_id = false,
  849. .verify = NULL,
  850. .wrapper = mlx4_GEN_QP_wrapper
  851. },
  852. {
  853. .opcode = MLX4_CMD_SQERR2RTS_QP,
  854. .has_inbox = true,
  855. .has_outbox = false,
  856. .out_is_imm = false,
  857. .encode_slave_id = false,
  858. .verify = NULL,
  859. .wrapper = mlx4_GEN_QP_wrapper
  860. },
  861. {
  862. .opcode = MLX4_CMD_2ERR_QP,
  863. .has_inbox = false,
  864. .has_outbox = false,
  865. .out_is_imm = false,
  866. .encode_slave_id = false,
  867. .verify = NULL,
  868. .wrapper = mlx4_GEN_QP_wrapper
  869. },
  870. {
  871. .opcode = MLX4_CMD_RTS2SQD_QP,
  872. .has_inbox = false,
  873. .has_outbox = false,
  874. .out_is_imm = false,
  875. .encode_slave_id = false,
  876. .verify = NULL,
  877. .wrapper = mlx4_GEN_QP_wrapper
  878. },
  879. {
  880. .opcode = MLX4_CMD_SQD2SQD_QP,
  881. .has_inbox = true,
  882. .has_outbox = false,
  883. .out_is_imm = false,
  884. .encode_slave_id = false,
  885. .verify = NULL,
  886. .wrapper = mlx4_GEN_QP_wrapper
  887. },
  888. {
  889. .opcode = MLX4_CMD_SQD2RTS_QP,
  890. .has_inbox = true,
  891. .has_outbox = false,
  892. .out_is_imm = false,
  893. .encode_slave_id = false,
  894. .verify = NULL,
  895. .wrapper = mlx4_GEN_QP_wrapper
  896. },
  897. {
  898. .opcode = MLX4_CMD_2RST_QP,
  899. .has_inbox = false,
  900. .has_outbox = false,
  901. .out_is_imm = false,
  902. .encode_slave_id = false,
  903. .verify = NULL,
  904. .wrapper = mlx4_2RST_QP_wrapper
  905. },
  906. {
  907. .opcode = MLX4_CMD_QUERY_QP,
  908. .has_inbox = false,
  909. .has_outbox = true,
  910. .out_is_imm = false,
  911. .encode_slave_id = false,
  912. .verify = NULL,
  913. .wrapper = mlx4_GEN_QP_wrapper
  914. },
  915. {
  916. .opcode = MLX4_CMD_SUSPEND_QP,
  917. .has_inbox = false,
  918. .has_outbox = false,
  919. .out_is_imm = false,
  920. .encode_slave_id = false,
  921. .verify = NULL,
  922. .wrapper = mlx4_GEN_QP_wrapper
  923. },
  924. {
  925. .opcode = MLX4_CMD_UNSUSPEND_QP,
  926. .has_inbox = false,
  927. .has_outbox = false,
  928. .out_is_imm = false,
  929. .encode_slave_id = false,
  930. .verify = NULL,
  931. .wrapper = mlx4_GEN_QP_wrapper
  932. },
  933. {
  934. .opcode = MLX4_CMD_QUERY_IF_STAT,
  935. .has_inbox = false,
  936. .has_outbox = true,
  937. .out_is_imm = false,
  938. .encode_slave_id = false,
  939. .verify = NULL,
  940. .wrapper = mlx4_QUERY_IF_STAT_wrapper
  941. },
  942. /* Native multicast commands are not available for guests */
  943. {
  944. .opcode = MLX4_CMD_QP_ATTACH,
  945. .has_inbox = true,
  946. .has_outbox = false,
  947. .out_is_imm = false,
  948. .encode_slave_id = false,
  949. .verify = NULL,
  950. .wrapper = mlx4_QP_ATTACH_wrapper
  951. },
  952. {
  953. .opcode = MLX4_CMD_PROMISC,
  954. .has_inbox = false,
  955. .has_outbox = false,
  956. .out_is_imm = false,
  957. .encode_slave_id = false,
  958. .verify = NULL,
  959. .wrapper = mlx4_PROMISC_wrapper
  960. },
  961. /* Ethernet specific commands */
  962. {
  963. .opcode = MLX4_CMD_SET_VLAN_FLTR,
  964. .has_inbox = true,
  965. .has_outbox = false,
  966. .out_is_imm = false,
  967. .encode_slave_id = false,
  968. .verify = NULL,
  969. .wrapper = mlx4_SET_VLAN_FLTR_wrapper
  970. },
  971. {
  972. .opcode = MLX4_CMD_SET_MCAST_FLTR,
  973. .has_inbox = false,
  974. .has_outbox = false,
  975. .out_is_imm = false,
  976. .encode_slave_id = false,
  977. .verify = NULL,
  978. .wrapper = mlx4_SET_MCAST_FLTR_wrapper
  979. },
  980. {
  981. .opcode = MLX4_CMD_DUMP_ETH_STATS,
  982. .has_inbox = false,
  983. .has_outbox = true,
  984. .out_is_imm = false,
  985. .encode_slave_id = false,
  986. .verify = NULL,
  987. .wrapper = mlx4_DUMP_ETH_STATS_wrapper
  988. },
  989. {
  990. .opcode = MLX4_CMD_INFORM_FLR_DONE,
  991. .has_inbox = false,
  992. .has_outbox = false,
  993. .out_is_imm = false,
  994. .encode_slave_id = false,
  995. .verify = NULL,
  996. .wrapper = NULL
  997. },
  998. };
  999. static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
  1000. struct mlx4_vhcr_cmd *in_vhcr)
  1001. {
  1002. struct mlx4_priv *priv = mlx4_priv(dev);
  1003. struct mlx4_cmd_info *cmd = NULL;
  1004. struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
  1005. struct mlx4_vhcr *vhcr;
  1006. struct mlx4_cmd_mailbox *inbox = NULL;
  1007. struct mlx4_cmd_mailbox *outbox = NULL;
  1008. u64 in_param;
  1009. u64 out_param;
  1010. int ret = 0;
  1011. int i;
  1012. int err = 0;
  1013. /* Create sw representation of Virtual HCR */
  1014. vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
  1015. if (!vhcr)
  1016. return -ENOMEM;
  1017. /* DMA in the vHCR */
  1018. if (!in_vhcr) {
  1019. ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
  1020. priv->mfunc.master.slave_state[slave].vhcr_dma,
  1021. ALIGN(sizeof(struct mlx4_vhcr_cmd),
  1022. MLX4_ACCESS_MEM_ALIGN), 1);
  1023. if (ret) {
  1024. mlx4_err(dev, "%s:Failed reading vhcr"
  1025. "ret: 0x%x\n", __func__, ret);
  1026. kfree(vhcr);
  1027. return ret;
  1028. }
  1029. }
  1030. /* Fill SW VHCR fields */
  1031. vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
  1032. vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
  1033. vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
  1034. vhcr->token = be16_to_cpu(vhcr_cmd->token);
  1035. vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
  1036. vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
  1037. vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
  1038. /* Lookup command */
  1039. for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
  1040. if (vhcr->op == cmd_info[i].opcode) {
  1041. cmd = &cmd_info[i];
  1042. break;
  1043. }
  1044. }
  1045. if (!cmd) {
  1046. mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
  1047. vhcr->op, slave);
  1048. vhcr_cmd->status = CMD_STAT_BAD_PARAM;
  1049. goto out_status;
  1050. }
  1051. /* Read inbox */
  1052. if (cmd->has_inbox) {
  1053. vhcr->in_param &= INBOX_MASK;
  1054. inbox = mlx4_alloc_cmd_mailbox(dev);
  1055. if (IS_ERR(inbox)) {
  1056. vhcr_cmd->status = CMD_STAT_BAD_SIZE;
  1057. inbox = NULL;
  1058. goto out_status;
  1059. }
  1060. if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
  1061. vhcr->in_param,
  1062. MLX4_MAILBOX_SIZE, 1)) {
  1063. mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
  1064. __func__, cmd->opcode);
  1065. vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
  1066. goto out_status;
  1067. }
  1068. }
  1069. /* Apply permission and bound checks if applicable */
  1070. if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
  1071. mlx4_warn(dev, "Command:0x%x from slave: %d failed protection "
  1072. "checks for resource_id:%d\n", vhcr->op, slave,
  1073. vhcr->in_modifier);
  1074. vhcr_cmd->status = CMD_STAT_BAD_OP;
  1075. goto out_status;
  1076. }
  1077. /* Allocate outbox */
  1078. if (cmd->has_outbox) {
  1079. outbox = mlx4_alloc_cmd_mailbox(dev);
  1080. if (IS_ERR(outbox)) {
  1081. vhcr_cmd->status = CMD_STAT_BAD_SIZE;
  1082. outbox = NULL;
  1083. goto out_status;
  1084. }
  1085. }
  1086. /* Execute the command! */
  1087. if (cmd->wrapper) {
  1088. err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
  1089. cmd);
  1090. if (cmd->out_is_imm)
  1091. vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
  1092. } else {
  1093. in_param = cmd->has_inbox ? (u64) inbox->dma :
  1094. vhcr->in_param;
  1095. out_param = cmd->has_outbox ? (u64) outbox->dma :
  1096. vhcr->out_param;
  1097. err = __mlx4_cmd(dev, in_param, &out_param,
  1098. cmd->out_is_imm, vhcr->in_modifier,
  1099. vhcr->op_modifier, vhcr->op,
  1100. MLX4_CMD_TIME_CLASS_A,
  1101. MLX4_CMD_NATIVE);
  1102. if (cmd->out_is_imm) {
  1103. vhcr->out_param = out_param;
  1104. vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
  1105. }
  1106. }
  1107. if (err) {
  1108. mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with"
  1109. " error:%d, status %d\n",
  1110. vhcr->op, slave, vhcr->errno, err);
  1111. vhcr_cmd->status = mlx4_errno_to_status(err);
  1112. goto out_status;
  1113. }
  1114. /* Write outbox if command completed successfully */
  1115. if (cmd->has_outbox && !vhcr_cmd->status) {
  1116. ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
  1117. vhcr->out_param,
  1118. MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
  1119. if (ret) {
  1120. /* If we failed to write back the outbox after the
  1121. *command was successfully executed, we must fail this
  1122. * slave, as it is now in undefined state */
  1123. mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
  1124. goto out;
  1125. }
  1126. }
  1127. out_status:
  1128. /* DMA back vhcr result */
  1129. if (!in_vhcr) {
  1130. ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
  1131. priv->mfunc.master.slave_state[slave].vhcr_dma,
  1132. ALIGN(sizeof(struct mlx4_vhcr),
  1133. MLX4_ACCESS_MEM_ALIGN),
  1134. MLX4_CMD_WRAPPED);
  1135. if (ret)
  1136. mlx4_err(dev, "%s:Failed writing vhcr result\n",
  1137. __func__);
  1138. else if (vhcr->e_bit &&
  1139. mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
  1140. mlx4_warn(dev, "Failed to generate command completion "
  1141. "eqe for slave %d\n", slave);
  1142. }
  1143. out:
  1144. kfree(vhcr);
  1145. mlx4_free_cmd_mailbox(dev, inbox);
  1146. mlx4_free_cmd_mailbox(dev, outbox);
  1147. return ret;
  1148. }
  1149. static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
  1150. u16 param, u8 toggle)
  1151. {
  1152. struct mlx4_priv *priv = mlx4_priv(dev);
  1153. struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
  1154. u32 reply;
  1155. u32 slave_status = 0;
  1156. u8 is_going_down = 0;
  1157. int i;
  1158. slave_state[slave].comm_toggle ^= 1;
  1159. reply = (u32) slave_state[slave].comm_toggle << 31;
  1160. if (toggle != slave_state[slave].comm_toggle) {
  1161. mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER"
  1162. "STATE COMPROMISIED ***\n", toggle, slave);
  1163. goto reset_slave;
  1164. }
  1165. if (cmd == MLX4_COMM_CMD_RESET) {
  1166. mlx4_warn(dev, "Received reset from slave:%d\n", slave);
  1167. slave_state[slave].active = false;
  1168. for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
  1169. slave_state[slave].event_eq[i].eqn = -1;
  1170. slave_state[slave].event_eq[i].token = 0;
  1171. }
  1172. /*check if we are in the middle of FLR process,
  1173. if so return "retry" status to the slave*/
  1174. if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
  1175. slave_status = MLX4_DELAY_RESET_SLAVE;
  1176. goto inform_slave_state;
  1177. }
  1178. /* write the version in the event field */
  1179. reply |= mlx4_comm_get_version();
  1180. goto reset_slave;
  1181. }
  1182. /*command from slave in the middle of FLR*/
  1183. if (cmd != MLX4_COMM_CMD_RESET &&
  1184. MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
  1185. mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) "
  1186. "in the middle of FLR\n", slave, cmd);
  1187. return;
  1188. }
  1189. switch (cmd) {
  1190. case MLX4_COMM_CMD_VHCR0:
  1191. if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
  1192. goto reset_slave;
  1193. slave_state[slave].vhcr_dma = ((u64) param) << 48;
  1194. priv->mfunc.master.slave_state[slave].cookie = 0;
  1195. mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1196. break;
  1197. case MLX4_COMM_CMD_VHCR1:
  1198. if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
  1199. goto reset_slave;
  1200. slave_state[slave].vhcr_dma |= ((u64) param) << 32;
  1201. break;
  1202. case MLX4_COMM_CMD_VHCR2:
  1203. if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
  1204. goto reset_slave;
  1205. slave_state[slave].vhcr_dma |= ((u64) param) << 16;
  1206. break;
  1207. case MLX4_COMM_CMD_VHCR_EN:
  1208. if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
  1209. goto reset_slave;
  1210. slave_state[slave].vhcr_dma |= param;
  1211. slave_state[slave].active = true;
  1212. break;
  1213. case MLX4_COMM_CMD_VHCR_POST:
  1214. if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
  1215. (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
  1216. goto reset_slave;
  1217. down(&priv->cmd.slave_sem);
  1218. if (mlx4_master_process_vhcr(dev, slave, NULL)) {
  1219. mlx4_err(dev, "Failed processing vhcr for slave:%d,"
  1220. " resetting slave.\n", slave);
  1221. up(&priv->cmd.slave_sem);
  1222. goto reset_slave;
  1223. }
  1224. up(&priv->cmd.slave_sem);
  1225. break;
  1226. default:
  1227. mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
  1228. goto reset_slave;
  1229. }
  1230. spin_lock(&priv->mfunc.master.slave_state_lock);
  1231. if (!slave_state[slave].is_slave_going_down)
  1232. slave_state[slave].last_cmd = cmd;
  1233. else
  1234. is_going_down = 1;
  1235. spin_unlock(&priv->mfunc.master.slave_state_lock);
  1236. if (is_going_down) {
  1237. mlx4_warn(dev, "Slave is going down aborting command(%d)"
  1238. " executing from slave:%d\n",
  1239. cmd, slave);
  1240. return;
  1241. }
  1242. __raw_writel((__force u32) cpu_to_be32(reply),
  1243. &priv->mfunc.comm[slave].slave_read);
  1244. mmiowb();
  1245. return;
  1246. reset_slave:
  1247. /* cleanup any slave resources */
  1248. mlx4_delete_all_resources_for_slave(dev, slave);
  1249. spin_lock(&priv->mfunc.master.slave_state_lock);
  1250. if (!slave_state[slave].is_slave_going_down)
  1251. slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
  1252. spin_unlock(&priv->mfunc.master.slave_state_lock);
  1253. /*with slave in the middle of flr, no need to clean resources again.*/
  1254. inform_slave_state:
  1255. memset(&slave_state[slave].event_eq, 0,
  1256. sizeof(struct mlx4_slave_event_eq_info));
  1257. __raw_writel((__force u32) cpu_to_be32(reply),
  1258. &priv->mfunc.comm[slave].slave_read);
  1259. wmb();
  1260. }
  1261. /* master command processing */
  1262. void mlx4_master_comm_channel(struct work_struct *work)
  1263. {
  1264. struct mlx4_mfunc_master_ctx *master =
  1265. container_of(work,
  1266. struct mlx4_mfunc_master_ctx,
  1267. comm_work);
  1268. struct mlx4_mfunc *mfunc =
  1269. container_of(master, struct mlx4_mfunc, master);
  1270. struct mlx4_priv *priv =
  1271. container_of(mfunc, struct mlx4_priv, mfunc);
  1272. struct mlx4_dev *dev = &priv->dev;
  1273. __be32 *bit_vec;
  1274. u32 comm_cmd;
  1275. u32 vec;
  1276. int i, j, slave;
  1277. int toggle;
  1278. int served = 0;
  1279. int reported = 0;
  1280. u32 slt;
  1281. bit_vec = master->comm_arm_bit_vector;
  1282. for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
  1283. vec = be32_to_cpu(bit_vec[i]);
  1284. for (j = 0; j < 32; j++) {
  1285. if (!(vec & (1 << j)))
  1286. continue;
  1287. ++reported;
  1288. slave = (i * 32) + j;
  1289. comm_cmd = swab32(readl(
  1290. &mfunc->comm[slave].slave_write));
  1291. slt = swab32(readl(&mfunc->comm[slave].slave_read))
  1292. >> 31;
  1293. toggle = comm_cmd >> 31;
  1294. if (toggle != slt) {
  1295. if (master->slave_state[slave].comm_toggle
  1296. != slt) {
  1297. printk(KERN_INFO "slave %d out of sync."
  1298. " read toggle %d, state toggle %d. "
  1299. "Resynching.\n", slave, slt,
  1300. master->slave_state[slave].comm_toggle);
  1301. master->slave_state[slave].comm_toggle =
  1302. slt;
  1303. }
  1304. mlx4_master_do_cmd(dev, slave,
  1305. comm_cmd >> 16 & 0xff,
  1306. comm_cmd & 0xffff, toggle);
  1307. ++served;
  1308. }
  1309. }
  1310. }
  1311. if (reported && reported != served)
  1312. mlx4_warn(dev, "Got command event with bitmask from %d slaves"
  1313. " but %d were served\n",
  1314. reported, served);
  1315. if (mlx4_ARM_COMM_CHANNEL(dev))
  1316. mlx4_warn(dev, "Failed to arm comm channel events\n");
  1317. }
  1318. static int sync_toggles(struct mlx4_dev *dev)
  1319. {
  1320. struct mlx4_priv *priv = mlx4_priv(dev);
  1321. int wr_toggle;
  1322. int rd_toggle;
  1323. unsigned long end;
  1324. wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
  1325. end = jiffies + msecs_to_jiffies(5000);
  1326. while (time_before(jiffies, end)) {
  1327. rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
  1328. if (rd_toggle == wr_toggle) {
  1329. priv->cmd.comm_toggle = rd_toggle;
  1330. return 0;
  1331. }
  1332. cond_resched();
  1333. }
  1334. /*
  1335. * we could reach here if for example the previous VM using this
  1336. * function misbehaved and left the channel with unsynced state. We
  1337. * should fix this here and give this VM a chance to use a properly
  1338. * synced channel
  1339. */
  1340. mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
  1341. __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
  1342. __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
  1343. priv->cmd.comm_toggle = 0;
  1344. return 0;
  1345. }
  1346. int mlx4_multi_func_init(struct mlx4_dev *dev)
  1347. {
  1348. struct mlx4_priv *priv = mlx4_priv(dev);
  1349. struct mlx4_slave_state *s_state;
  1350. int i, j, err, port;
  1351. priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
  1352. &priv->mfunc.vhcr_dma,
  1353. GFP_KERNEL);
  1354. if (!priv->mfunc.vhcr) {
  1355. mlx4_err(dev, "Couldn't allocate vhcr.\n");
  1356. return -ENOMEM;
  1357. }
  1358. if (mlx4_is_master(dev))
  1359. priv->mfunc.comm =
  1360. ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
  1361. priv->fw.comm_base, MLX4_COMM_PAGESIZE);
  1362. else
  1363. priv->mfunc.comm =
  1364. ioremap(pci_resource_start(dev->pdev, 2) +
  1365. MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
  1366. if (!priv->mfunc.comm) {
  1367. mlx4_err(dev, "Couldn't map communication vector.\n");
  1368. goto err_vhcr;
  1369. }
  1370. if (mlx4_is_master(dev)) {
  1371. priv->mfunc.master.slave_state =
  1372. kzalloc(dev->num_slaves *
  1373. sizeof(struct mlx4_slave_state), GFP_KERNEL);
  1374. if (!priv->mfunc.master.slave_state)
  1375. goto err_comm;
  1376. for (i = 0; i < dev->num_slaves; ++i) {
  1377. s_state = &priv->mfunc.master.slave_state[i];
  1378. s_state->last_cmd = MLX4_COMM_CMD_RESET;
  1379. for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
  1380. s_state->event_eq[j].eqn = -1;
  1381. __raw_writel((__force u32) 0,
  1382. &priv->mfunc.comm[i].slave_write);
  1383. __raw_writel((__force u32) 0,
  1384. &priv->mfunc.comm[i].slave_read);
  1385. mmiowb();
  1386. for (port = 1; port <= MLX4_MAX_PORTS; port++) {
  1387. s_state->vlan_filter[port] =
  1388. kzalloc(sizeof(struct mlx4_vlan_fltr),
  1389. GFP_KERNEL);
  1390. if (!s_state->vlan_filter[port]) {
  1391. if (--port)
  1392. kfree(s_state->vlan_filter[port]);
  1393. goto err_slaves;
  1394. }
  1395. INIT_LIST_HEAD(&s_state->mcast_filters[port]);
  1396. }
  1397. spin_lock_init(&s_state->lock);
  1398. }
  1399. memset(&priv->mfunc.master.cmd_eqe, 0, sizeof(struct mlx4_eqe));
  1400. priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
  1401. INIT_WORK(&priv->mfunc.master.comm_work,
  1402. mlx4_master_comm_channel);
  1403. INIT_WORK(&priv->mfunc.master.slave_event_work,
  1404. mlx4_gen_slave_eqe);
  1405. INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
  1406. mlx4_master_handle_slave_flr);
  1407. spin_lock_init(&priv->mfunc.master.slave_state_lock);
  1408. priv->mfunc.master.comm_wq =
  1409. create_singlethread_workqueue("mlx4_comm");
  1410. if (!priv->mfunc.master.comm_wq)
  1411. goto err_slaves;
  1412. if (mlx4_init_resource_tracker(dev))
  1413. goto err_thread;
  1414. sema_init(&priv->cmd.slave_sem, 1);
  1415. err = mlx4_ARM_COMM_CHANNEL(dev);
  1416. if (err) {
  1417. mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
  1418. err);
  1419. goto err_resource;
  1420. }
  1421. } else {
  1422. err = sync_toggles(dev);
  1423. if (err) {
  1424. mlx4_err(dev, "Couldn't sync toggles\n");
  1425. goto err_comm;
  1426. }
  1427. sema_init(&priv->cmd.slave_sem, 1);
  1428. }
  1429. return 0;
  1430. err_resource:
  1431. mlx4_free_resource_tracker(dev);
  1432. err_thread:
  1433. flush_workqueue(priv->mfunc.master.comm_wq);
  1434. destroy_workqueue(priv->mfunc.master.comm_wq);
  1435. err_slaves:
  1436. while (--i) {
  1437. for (port = 1; port <= MLX4_MAX_PORTS; port++)
  1438. kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
  1439. }
  1440. kfree(priv->mfunc.master.slave_state);
  1441. err_comm:
  1442. iounmap(priv->mfunc.comm);
  1443. err_vhcr:
  1444. dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
  1445. priv->mfunc.vhcr,
  1446. priv->mfunc.vhcr_dma);
  1447. priv->mfunc.vhcr = NULL;
  1448. return -ENOMEM;
  1449. }
  1450. int mlx4_cmd_init(struct mlx4_dev *dev)
  1451. {
  1452. struct mlx4_priv *priv = mlx4_priv(dev);
  1453. mutex_init(&priv->cmd.hcr_mutex);
  1454. sema_init(&priv->cmd.poll_sem, 1);
  1455. priv->cmd.use_events = 0;
  1456. priv->cmd.toggle = 1;
  1457. priv->cmd.hcr = NULL;
  1458. priv->mfunc.vhcr = NULL;
  1459. if (!mlx4_is_slave(dev)) {
  1460. priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
  1461. MLX4_HCR_BASE, MLX4_HCR_SIZE);
  1462. if (!priv->cmd.hcr) {
  1463. mlx4_err(dev, "Couldn't map command register.\n");
  1464. return -ENOMEM;
  1465. }
  1466. }
  1467. priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
  1468. MLX4_MAILBOX_SIZE,
  1469. MLX4_MAILBOX_SIZE, 0);
  1470. if (!priv->cmd.pool)
  1471. goto err_hcr;
  1472. return 0;
  1473. err_hcr:
  1474. if (!mlx4_is_slave(dev))
  1475. iounmap(priv->cmd.hcr);
  1476. return -ENOMEM;
  1477. }
  1478. void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
  1479. {
  1480. struct mlx4_priv *priv = mlx4_priv(dev);
  1481. int i, port;
  1482. if (mlx4_is_master(dev)) {
  1483. flush_workqueue(priv->mfunc.master.comm_wq);
  1484. destroy_workqueue(priv->mfunc.master.comm_wq);
  1485. for (i = 0; i < dev->num_slaves; i++) {
  1486. for (port = 1; port <= MLX4_MAX_PORTS; port++)
  1487. kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
  1488. }
  1489. kfree(priv->mfunc.master.slave_state);
  1490. }
  1491. iounmap(priv->mfunc.comm);
  1492. dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
  1493. priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
  1494. priv->mfunc.vhcr = NULL;
  1495. }
  1496. void mlx4_cmd_cleanup(struct mlx4_dev *dev)
  1497. {
  1498. struct mlx4_priv *priv = mlx4_priv(dev);
  1499. pci_pool_destroy(priv->cmd.pool);
  1500. if (!mlx4_is_slave(dev))
  1501. iounmap(priv->cmd.hcr);
  1502. }
  1503. /*
  1504. * Switch to using events to issue FW commands (can only be called
  1505. * after event queue for command events has been initialized).
  1506. */
  1507. int mlx4_cmd_use_events(struct mlx4_dev *dev)
  1508. {
  1509. struct mlx4_priv *priv = mlx4_priv(dev);
  1510. int i;
  1511. int err = 0;
  1512. priv->cmd.context = kmalloc(priv->cmd.max_cmds *
  1513. sizeof (struct mlx4_cmd_context),
  1514. GFP_KERNEL);
  1515. if (!priv->cmd.context)
  1516. return -ENOMEM;
  1517. for (i = 0; i < priv->cmd.max_cmds; ++i) {
  1518. priv->cmd.context[i].token = i;
  1519. priv->cmd.context[i].next = i + 1;
  1520. }
  1521. priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
  1522. priv->cmd.free_head = 0;
  1523. sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
  1524. spin_lock_init(&priv->cmd.context_lock);
  1525. for (priv->cmd.token_mask = 1;
  1526. priv->cmd.token_mask < priv->cmd.max_cmds;
  1527. priv->cmd.token_mask <<= 1)
  1528. ; /* nothing */
  1529. --priv->cmd.token_mask;
  1530. down(&priv->cmd.poll_sem);
  1531. priv->cmd.use_events = 1;
  1532. return err;
  1533. }
  1534. /*
  1535. * Switch back to polling (used when shutting down the device)
  1536. */
  1537. void mlx4_cmd_use_polling(struct mlx4_dev *dev)
  1538. {
  1539. struct mlx4_priv *priv = mlx4_priv(dev);
  1540. int i;
  1541. priv->cmd.use_events = 0;
  1542. for (i = 0; i < priv->cmd.max_cmds; ++i)
  1543. down(&priv->cmd.event_sem);
  1544. kfree(priv->cmd.context);
  1545. up(&priv->cmd.poll_sem);
  1546. }
  1547. struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
  1548. {
  1549. struct mlx4_cmd_mailbox *mailbox;
  1550. mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
  1551. if (!mailbox)
  1552. return ERR_PTR(-ENOMEM);
  1553. mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
  1554. &mailbox->dma);
  1555. if (!mailbox->buf) {
  1556. kfree(mailbox);
  1557. return ERR_PTR(-ENOMEM);
  1558. }
  1559. return mailbox;
  1560. }
  1561. EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
  1562. void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
  1563. struct mlx4_cmd_mailbox *mailbox)
  1564. {
  1565. if (!mailbox)
  1566. return;
  1567. pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
  1568. kfree(mailbox);
  1569. }
  1570. EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
  1571. u32 mlx4_comm_get_version(void)
  1572. {
  1573. return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
  1574. }