bna_tx_rx.c 91 KB

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  1. /*
  2. * Linux network driver for Brocade Converged Network Adapter.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License (GPL) Version 2 as
  6. * published by the Free Software Foundation
  7. *
  8. * This program is distributed in the hope that it will be useful, but
  9. * WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  11. * General Public License for more details.
  12. */
  13. /*
  14. * Copyright (c) 2005-2011 Brocade Communications Systems, Inc.
  15. * All rights reserved
  16. * www.brocade.com
  17. */
  18. #include "bna.h"
  19. #include "bfi.h"
  20. /**
  21. * IB
  22. */
  23. static void
  24. bna_ib_coalescing_timeo_set(struct bna_ib *ib, u8 coalescing_timeo)
  25. {
  26. ib->coalescing_timeo = coalescing_timeo;
  27. ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK(
  28. (u32)ib->coalescing_timeo, 0);
  29. }
  30. /**
  31. * RXF
  32. */
  33. #define bna_rxf_vlan_cfg_soft_reset(rxf) \
  34. do { \
  35. (rxf)->vlan_pending_bitmask = (u8)BFI_VLAN_BMASK_ALL; \
  36. (rxf)->vlan_strip_pending = true; \
  37. } while (0)
  38. #define bna_rxf_rss_cfg_soft_reset(rxf) \
  39. do { \
  40. if ((rxf)->rss_status == BNA_STATUS_T_ENABLED) \
  41. (rxf)->rss_pending = (BNA_RSS_F_RIT_PENDING | \
  42. BNA_RSS_F_CFG_PENDING | \
  43. BNA_RSS_F_STATUS_PENDING); \
  44. } while (0)
  45. static int bna_rxf_cfg_apply(struct bna_rxf *rxf);
  46. static void bna_rxf_cfg_reset(struct bna_rxf *rxf);
  47. static int bna_rxf_fltr_clear(struct bna_rxf *rxf);
  48. static int bna_rxf_ucast_cfg_apply(struct bna_rxf *rxf);
  49. static int bna_rxf_promisc_cfg_apply(struct bna_rxf *rxf);
  50. static int bna_rxf_allmulti_cfg_apply(struct bna_rxf *rxf);
  51. static int bna_rxf_vlan_strip_cfg_apply(struct bna_rxf *rxf);
  52. static int bna_rxf_ucast_cfg_reset(struct bna_rxf *rxf,
  53. enum bna_cleanup_type cleanup);
  54. static int bna_rxf_promisc_cfg_reset(struct bna_rxf *rxf,
  55. enum bna_cleanup_type cleanup);
  56. static int bna_rxf_allmulti_cfg_reset(struct bna_rxf *rxf,
  57. enum bna_cleanup_type cleanup);
  58. bfa_fsm_state_decl(bna_rxf, stopped, struct bna_rxf,
  59. enum bna_rxf_event);
  60. bfa_fsm_state_decl(bna_rxf, paused, struct bna_rxf,
  61. enum bna_rxf_event);
  62. bfa_fsm_state_decl(bna_rxf, cfg_wait, struct bna_rxf,
  63. enum bna_rxf_event);
  64. bfa_fsm_state_decl(bna_rxf, started, struct bna_rxf,
  65. enum bna_rxf_event);
  66. bfa_fsm_state_decl(bna_rxf, fltr_clr_wait, struct bna_rxf,
  67. enum bna_rxf_event);
  68. bfa_fsm_state_decl(bna_rxf, last_resp_wait, struct bna_rxf,
  69. enum bna_rxf_event);
  70. static void
  71. bna_rxf_sm_stopped_entry(struct bna_rxf *rxf)
  72. {
  73. call_rxf_stop_cbfn(rxf);
  74. }
  75. static void
  76. bna_rxf_sm_stopped(struct bna_rxf *rxf, enum bna_rxf_event event)
  77. {
  78. switch (event) {
  79. case RXF_E_START:
  80. if (rxf->flags & BNA_RXF_F_PAUSED) {
  81. bfa_fsm_set_state(rxf, bna_rxf_sm_paused);
  82. call_rxf_start_cbfn(rxf);
  83. } else
  84. bfa_fsm_set_state(rxf, bna_rxf_sm_cfg_wait);
  85. break;
  86. case RXF_E_STOP:
  87. call_rxf_stop_cbfn(rxf);
  88. break;
  89. case RXF_E_FAIL:
  90. /* No-op */
  91. break;
  92. case RXF_E_CONFIG:
  93. call_rxf_cam_fltr_cbfn(rxf);
  94. break;
  95. case RXF_E_PAUSE:
  96. rxf->flags |= BNA_RXF_F_PAUSED;
  97. call_rxf_pause_cbfn(rxf);
  98. break;
  99. case RXF_E_RESUME:
  100. rxf->flags &= ~BNA_RXF_F_PAUSED;
  101. call_rxf_resume_cbfn(rxf);
  102. break;
  103. default:
  104. bfa_sm_fault(event);
  105. }
  106. }
  107. static void
  108. bna_rxf_sm_paused_entry(struct bna_rxf *rxf)
  109. {
  110. call_rxf_pause_cbfn(rxf);
  111. }
  112. static void
  113. bna_rxf_sm_paused(struct bna_rxf *rxf, enum bna_rxf_event event)
  114. {
  115. switch (event) {
  116. case RXF_E_STOP:
  117. case RXF_E_FAIL:
  118. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  119. break;
  120. case RXF_E_CONFIG:
  121. call_rxf_cam_fltr_cbfn(rxf);
  122. break;
  123. case RXF_E_RESUME:
  124. rxf->flags &= ~BNA_RXF_F_PAUSED;
  125. bfa_fsm_set_state(rxf, bna_rxf_sm_cfg_wait);
  126. break;
  127. default:
  128. bfa_sm_fault(event);
  129. }
  130. }
  131. static void
  132. bna_rxf_sm_cfg_wait_entry(struct bna_rxf *rxf)
  133. {
  134. if (!bna_rxf_cfg_apply(rxf)) {
  135. /* No more pending config updates */
  136. bfa_fsm_set_state(rxf, bna_rxf_sm_started);
  137. }
  138. }
  139. static void
  140. bna_rxf_sm_cfg_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  141. {
  142. switch (event) {
  143. case RXF_E_STOP:
  144. bfa_fsm_set_state(rxf, bna_rxf_sm_last_resp_wait);
  145. break;
  146. case RXF_E_FAIL:
  147. bna_rxf_cfg_reset(rxf);
  148. call_rxf_start_cbfn(rxf);
  149. call_rxf_cam_fltr_cbfn(rxf);
  150. call_rxf_resume_cbfn(rxf);
  151. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  152. break;
  153. case RXF_E_CONFIG:
  154. /* No-op */
  155. break;
  156. case RXF_E_PAUSE:
  157. rxf->flags |= BNA_RXF_F_PAUSED;
  158. call_rxf_start_cbfn(rxf);
  159. bfa_fsm_set_state(rxf, bna_rxf_sm_fltr_clr_wait);
  160. break;
  161. case RXF_E_FW_RESP:
  162. if (!bna_rxf_cfg_apply(rxf)) {
  163. /* No more pending config updates */
  164. bfa_fsm_set_state(rxf, bna_rxf_sm_started);
  165. }
  166. break;
  167. default:
  168. bfa_sm_fault(event);
  169. }
  170. }
  171. static void
  172. bna_rxf_sm_started_entry(struct bna_rxf *rxf)
  173. {
  174. call_rxf_start_cbfn(rxf);
  175. call_rxf_cam_fltr_cbfn(rxf);
  176. call_rxf_resume_cbfn(rxf);
  177. }
  178. static void
  179. bna_rxf_sm_started(struct bna_rxf *rxf, enum bna_rxf_event event)
  180. {
  181. switch (event) {
  182. case RXF_E_STOP:
  183. case RXF_E_FAIL:
  184. bna_rxf_cfg_reset(rxf);
  185. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  186. break;
  187. case RXF_E_CONFIG:
  188. bfa_fsm_set_state(rxf, bna_rxf_sm_cfg_wait);
  189. break;
  190. case RXF_E_PAUSE:
  191. rxf->flags |= BNA_RXF_F_PAUSED;
  192. if (!bna_rxf_fltr_clear(rxf))
  193. bfa_fsm_set_state(rxf, bna_rxf_sm_paused);
  194. else
  195. bfa_fsm_set_state(rxf, bna_rxf_sm_fltr_clr_wait);
  196. break;
  197. default:
  198. bfa_sm_fault(event);
  199. }
  200. }
  201. static void
  202. bna_rxf_sm_fltr_clr_wait_entry(struct bna_rxf *rxf)
  203. {
  204. }
  205. static void
  206. bna_rxf_sm_fltr_clr_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  207. {
  208. switch (event) {
  209. case RXF_E_FAIL:
  210. bna_rxf_cfg_reset(rxf);
  211. call_rxf_pause_cbfn(rxf);
  212. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  213. break;
  214. case RXF_E_FW_RESP:
  215. if (!bna_rxf_fltr_clear(rxf)) {
  216. /* No more pending CAM entries to clear */
  217. bfa_fsm_set_state(rxf, bna_rxf_sm_paused);
  218. }
  219. break;
  220. default:
  221. bfa_sm_fault(event);
  222. }
  223. }
  224. static void
  225. bna_rxf_sm_last_resp_wait_entry(struct bna_rxf *rxf)
  226. {
  227. }
  228. static void
  229. bna_rxf_sm_last_resp_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  230. {
  231. switch (event) {
  232. case RXF_E_FAIL:
  233. case RXF_E_FW_RESP:
  234. bna_rxf_cfg_reset(rxf);
  235. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  236. break;
  237. default:
  238. bfa_sm_fault(event);
  239. }
  240. }
  241. static void
  242. bna_bfi_ucast_req(struct bna_rxf *rxf, struct bna_mac *mac,
  243. enum bfi_enet_h2i_msgs req_type)
  244. {
  245. struct bfi_enet_ucast_req *req = &rxf->bfi_enet_cmd.ucast_req;
  246. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET, req_type, 0, rxf->rx->rid);
  247. req->mh.num_entries = htons(
  248. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_ucast_req)));
  249. memcpy(&req->mac_addr, &mac->addr, sizeof(mac_t));
  250. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  251. sizeof(struct bfi_enet_ucast_req), &req->mh);
  252. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  253. }
  254. static void
  255. bna_bfi_mcast_add_req(struct bna_rxf *rxf, struct bna_mac *mac)
  256. {
  257. struct bfi_enet_mcast_add_req *req =
  258. &rxf->bfi_enet_cmd.mcast_add_req;
  259. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET, BFI_ENET_H2I_MAC_MCAST_ADD_REQ,
  260. 0, rxf->rx->rid);
  261. req->mh.num_entries = htons(
  262. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_mcast_add_req)));
  263. memcpy(&req->mac_addr, &mac->addr, sizeof(mac_t));
  264. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  265. sizeof(struct bfi_enet_mcast_add_req), &req->mh);
  266. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  267. }
  268. static void
  269. bna_bfi_mcast_del_req(struct bna_rxf *rxf, u16 handle)
  270. {
  271. struct bfi_enet_mcast_del_req *req =
  272. &rxf->bfi_enet_cmd.mcast_del_req;
  273. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET, BFI_ENET_H2I_MAC_MCAST_DEL_REQ,
  274. 0, rxf->rx->rid);
  275. req->mh.num_entries = htons(
  276. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_mcast_del_req)));
  277. req->handle = htons(handle);
  278. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  279. sizeof(struct bfi_enet_mcast_del_req), &req->mh);
  280. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  281. }
  282. static void
  283. bna_bfi_mcast_filter_req(struct bna_rxf *rxf, enum bna_status status)
  284. {
  285. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  286. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  287. BFI_ENET_H2I_MAC_MCAST_FILTER_REQ, 0, rxf->rx->rid);
  288. req->mh.num_entries = htons(
  289. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  290. req->enable = status;
  291. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  292. sizeof(struct bfi_enet_enable_req), &req->mh);
  293. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  294. }
  295. static void
  296. bna_bfi_rx_promisc_req(struct bna_rxf *rxf, enum bna_status status)
  297. {
  298. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  299. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  300. BFI_ENET_H2I_RX_PROMISCUOUS_REQ, 0, rxf->rx->rid);
  301. req->mh.num_entries = htons(
  302. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  303. req->enable = status;
  304. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  305. sizeof(struct bfi_enet_enable_req), &req->mh);
  306. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  307. }
  308. static void
  309. bna_bfi_rx_vlan_filter_set(struct bna_rxf *rxf, u8 block_idx)
  310. {
  311. struct bfi_enet_rx_vlan_req *req = &rxf->bfi_enet_cmd.vlan_req;
  312. int i;
  313. int j;
  314. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  315. BFI_ENET_H2I_RX_VLAN_SET_REQ, 0, rxf->rx->rid);
  316. req->mh.num_entries = htons(
  317. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rx_vlan_req)));
  318. req->block_idx = block_idx;
  319. for (i = 0; i < (BFI_ENET_VLAN_BLOCK_SIZE / 32); i++) {
  320. j = (block_idx * (BFI_ENET_VLAN_BLOCK_SIZE / 32)) + i;
  321. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED)
  322. req->bit_mask[i] =
  323. htonl(rxf->vlan_filter_table[j]);
  324. else
  325. req->bit_mask[i] = 0xFFFFFFFF;
  326. }
  327. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  328. sizeof(struct bfi_enet_rx_vlan_req), &req->mh);
  329. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  330. }
  331. static void
  332. bna_bfi_vlan_strip_enable(struct bna_rxf *rxf)
  333. {
  334. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  335. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  336. BFI_ENET_H2I_RX_VLAN_STRIP_ENABLE_REQ, 0, rxf->rx->rid);
  337. req->mh.num_entries = htons(
  338. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  339. req->enable = rxf->vlan_strip_status;
  340. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  341. sizeof(struct bfi_enet_enable_req), &req->mh);
  342. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  343. }
  344. static void
  345. bna_bfi_rit_cfg(struct bna_rxf *rxf)
  346. {
  347. struct bfi_enet_rit_req *req = &rxf->bfi_enet_cmd.rit_req;
  348. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  349. BFI_ENET_H2I_RIT_CFG_REQ, 0, rxf->rx->rid);
  350. req->mh.num_entries = htons(
  351. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rit_req)));
  352. req->size = htons(rxf->rit_size);
  353. memcpy(&req->table[0], rxf->rit, rxf->rit_size);
  354. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  355. sizeof(struct bfi_enet_rit_req), &req->mh);
  356. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  357. }
  358. static void
  359. bna_bfi_rss_cfg(struct bna_rxf *rxf)
  360. {
  361. struct bfi_enet_rss_cfg_req *req = &rxf->bfi_enet_cmd.rss_req;
  362. int i;
  363. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  364. BFI_ENET_H2I_RSS_CFG_REQ, 0, rxf->rx->rid);
  365. req->mh.num_entries = htons(
  366. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rss_cfg_req)));
  367. req->cfg.type = rxf->rss_cfg.hash_type;
  368. req->cfg.mask = rxf->rss_cfg.hash_mask;
  369. for (i = 0; i < BFI_ENET_RSS_KEY_LEN; i++)
  370. req->cfg.key[i] =
  371. htonl(rxf->rss_cfg.toeplitz_hash_key[i]);
  372. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  373. sizeof(struct bfi_enet_rss_cfg_req), &req->mh);
  374. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  375. }
  376. static void
  377. bna_bfi_rss_enable(struct bna_rxf *rxf)
  378. {
  379. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  380. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  381. BFI_ENET_H2I_RSS_ENABLE_REQ, 0, rxf->rx->rid);
  382. req->mh.num_entries = htons(
  383. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  384. req->enable = rxf->rss_status;
  385. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  386. sizeof(struct bfi_enet_enable_req), &req->mh);
  387. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  388. }
  389. /* This function gets the multicast MAC that has already been added to CAM */
  390. static struct bna_mac *
  391. bna_rxf_mcmac_get(struct bna_rxf *rxf, u8 *mac_addr)
  392. {
  393. struct bna_mac *mac;
  394. struct list_head *qe;
  395. list_for_each(qe, &rxf->mcast_active_q) {
  396. mac = (struct bna_mac *)qe;
  397. if (BNA_MAC_IS_EQUAL(&mac->addr, mac_addr))
  398. return mac;
  399. }
  400. list_for_each(qe, &rxf->mcast_pending_del_q) {
  401. mac = (struct bna_mac *)qe;
  402. if (BNA_MAC_IS_EQUAL(&mac->addr, mac_addr))
  403. return mac;
  404. }
  405. return NULL;
  406. }
  407. static struct bna_mcam_handle *
  408. bna_rxf_mchandle_get(struct bna_rxf *rxf, int handle)
  409. {
  410. struct bna_mcam_handle *mchandle;
  411. struct list_head *qe;
  412. list_for_each(qe, &rxf->mcast_handle_q) {
  413. mchandle = (struct bna_mcam_handle *)qe;
  414. if (mchandle->handle == handle)
  415. return mchandle;
  416. }
  417. return NULL;
  418. }
  419. static void
  420. bna_rxf_mchandle_attach(struct bna_rxf *rxf, u8 *mac_addr, int handle)
  421. {
  422. struct bna_mac *mcmac;
  423. struct bna_mcam_handle *mchandle;
  424. mcmac = bna_rxf_mcmac_get(rxf, mac_addr);
  425. mchandle = bna_rxf_mchandle_get(rxf, handle);
  426. if (mchandle == NULL) {
  427. mchandle = bna_mcam_mod_handle_get(&rxf->rx->bna->mcam_mod);
  428. mchandle->handle = handle;
  429. mchandle->refcnt = 0;
  430. list_add_tail(&mchandle->qe, &rxf->mcast_handle_q);
  431. }
  432. mchandle->refcnt++;
  433. mcmac->handle = mchandle;
  434. }
  435. static int
  436. bna_rxf_mcast_del(struct bna_rxf *rxf, struct bna_mac *mac,
  437. enum bna_cleanup_type cleanup)
  438. {
  439. struct bna_mcam_handle *mchandle;
  440. int ret = 0;
  441. mchandle = mac->handle;
  442. if (mchandle == NULL)
  443. return ret;
  444. mchandle->refcnt--;
  445. if (mchandle->refcnt == 0) {
  446. if (cleanup == BNA_HARD_CLEANUP) {
  447. bna_bfi_mcast_del_req(rxf, mchandle->handle);
  448. ret = 1;
  449. }
  450. list_del(&mchandle->qe);
  451. bfa_q_qe_init(&mchandle->qe);
  452. bna_mcam_mod_handle_put(&rxf->rx->bna->mcam_mod, mchandle);
  453. }
  454. mac->handle = NULL;
  455. return ret;
  456. }
  457. static int
  458. bna_rxf_mcast_cfg_apply(struct bna_rxf *rxf)
  459. {
  460. struct bna_mac *mac = NULL;
  461. struct list_head *qe;
  462. int ret;
  463. /* Delete multicast entries previousely added */
  464. while (!list_empty(&rxf->mcast_pending_del_q)) {
  465. bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
  466. bfa_q_qe_init(qe);
  467. mac = (struct bna_mac *)qe;
  468. ret = bna_rxf_mcast_del(rxf, mac, BNA_HARD_CLEANUP);
  469. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  470. if (ret)
  471. return ret;
  472. }
  473. /* Add multicast entries */
  474. if (!list_empty(&rxf->mcast_pending_add_q)) {
  475. bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
  476. bfa_q_qe_init(qe);
  477. mac = (struct bna_mac *)qe;
  478. list_add_tail(&mac->qe, &rxf->mcast_active_q);
  479. bna_bfi_mcast_add_req(rxf, mac);
  480. return 1;
  481. }
  482. return 0;
  483. }
  484. static int
  485. bna_rxf_vlan_cfg_apply(struct bna_rxf *rxf)
  486. {
  487. u8 vlan_pending_bitmask;
  488. int block_idx = 0;
  489. if (rxf->vlan_pending_bitmask) {
  490. vlan_pending_bitmask = rxf->vlan_pending_bitmask;
  491. while (!(vlan_pending_bitmask & 0x1)) {
  492. block_idx++;
  493. vlan_pending_bitmask >>= 1;
  494. }
  495. rxf->vlan_pending_bitmask &= ~(1 << block_idx);
  496. bna_bfi_rx_vlan_filter_set(rxf, block_idx);
  497. return 1;
  498. }
  499. return 0;
  500. }
  501. static int
  502. bna_rxf_mcast_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  503. {
  504. struct list_head *qe;
  505. struct bna_mac *mac;
  506. int ret;
  507. /* Throw away delete pending mcast entries */
  508. while (!list_empty(&rxf->mcast_pending_del_q)) {
  509. bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
  510. bfa_q_qe_init(qe);
  511. mac = (struct bna_mac *)qe;
  512. ret = bna_rxf_mcast_del(rxf, mac, cleanup);
  513. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  514. if (ret)
  515. return ret;
  516. }
  517. /* Move active mcast entries to pending_add_q */
  518. while (!list_empty(&rxf->mcast_active_q)) {
  519. bfa_q_deq(&rxf->mcast_active_q, &qe);
  520. bfa_q_qe_init(qe);
  521. list_add_tail(qe, &rxf->mcast_pending_add_q);
  522. mac = (struct bna_mac *)qe;
  523. if (bna_rxf_mcast_del(rxf, mac, cleanup))
  524. return 1;
  525. }
  526. return 0;
  527. }
  528. static int
  529. bna_rxf_rss_cfg_apply(struct bna_rxf *rxf)
  530. {
  531. if (rxf->rss_pending) {
  532. if (rxf->rss_pending & BNA_RSS_F_RIT_PENDING) {
  533. rxf->rss_pending &= ~BNA_RSS_F_RIT_PENDING;
  534. bna_bfi_rit_cfg(rxf);
  535. return 1;
  536. }
  537. if (rxf->rss_pending & BNA_RSS_F_CFG_PENDING) {
  538. rxf->rss_pending &= ~BNA_RSS_F_CFG_PENDING;
  539. bna_bfi_rss_cfg(rxf);
  540. return 1;
  541. }
  542. if (rxf->rss_pending & BNA_RSS_F_STATUS_PENDING) {
  543. rxf->rss_pending &= ~BNA_RSS_F_STATUS_PENDING;
  544. bna_bfi_rss_enable(rxf);
  545. return 1;
  546. }
  547. }
  548. return 0;
  549. }
  550. static int
  551. bna_rxf_cfg_apply(struct bna_rxf *rxf)
  552. {
  553. if (bna_rxf_ucast_cfg_apply(rxf))
  554. return 1;
  555. if (bna_rxf_mcast_cfg_apply(rxf))
  556. return 1;
  557. if (bna_rxf_promisc_cfg_apply(rxf))
  558. return 1;
  559. if (bna_rxf_allmulti_cfg_apply(rxf))
  560. return 1;
  561. if (bna_rxf_vlan_cfg_apply(rxf))
  562. return 1;
  563. if (bna_rxf_vlan_strip_cfg_apply(rxf))
  564. return 1;
  565. if (bna_rxf_rss_cfg_apply(rxf))
  566. return 1;
  567. return 0;
  568. }
  569. /* Only software reset */
  570. static int
  571. bna_rxf_fltr_clear(struct bna_rxf *rxf)
  572. {
  573. if (bna_rxf_ucast_cfg_reset(rxf, BNA_HARD_CLEANUP))
  574. return 1;
  575. if (bna_rxf_mcast_cfg_reset(rxf, BNA_HARD_CLEANUP))
  576. return 1;
  577. if (bna_rxf_promisc_cfg_reset(rxf, BNA_HARD_CLEANUP))
  578. return 1;
  579. if (bna_rxf_allmulti_cfg_reset(rxf, BNA_HARD_CLEANUP))
  580. return 1;
  581. return 0;
  582. }
  583. static void
  584. bna_rxf_cfg_reset(struct bna_rxf *rxf)
  585. {
  586. bna_rxf_ucast_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  587. bna_rxf_mcast_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  588. bna_rxf_promisc_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  589. bna_rxf_allmulti_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  590. bna_rxf_vlan_cfg_soft_reset(rxf);
  591. bna_rxf_rss_cfg_soft_reset(rxf);
  592. }
  593. static void
  594. bna_rit_init(struct bna_rxf *rxf, int rit_size)
  595. {
  596. struct bna_rx *rx = rxf->rx;
  597. struct bna_rxp *rxp;
  598. struct list_head *qe;
  599. int offset = 0;
  600. rxf->rit_size = rit_size;
  601. list_for_each(qe, &rx->rxp_q) {
  602. rxp = (struct bna_rxp *)qe;
  603. rxf->rit[offset] = rxp->cq.ccb->id;
  604. offset++;
  605. }
  606. }
  607. void
  608. bna_bfi_rxf_cfg_rsp(struct bna_rxf *rxf, struct bfi_msgq_mhdr *msghdr)
  609. {
  610. bfa_fsm_send_event(rxf, RXF_E_FW_RESP);
  611. }
  612. void
  613. bna_bfi_rxf_mcast_add_rsp(struct bna_rxf *rxf,
  614. struct bfi_msgq_mhdr *msghdr)
  615. {
  616. struct bfi_enet_mcast_add_req *req =
  617. &rxf->bfi_enet_cmd.mcast_add_req;
  618. struct bfi_enet_mcast_add_rsp *rsp =
  619. (struct bfi_enet_mcast_add_rsp *)msghdr;
  620. bna_rxf_mchandle_attach(rxf, (u8 *)&req->mac_addr,
  621. ntohs(rsp->handle));
  622. bfa_fsm_send_event(rxf, RXF_E_FW_RESP);
  623. }
  624. static void
  625. bna_rxf_init(struct bna_rxf *rxf,
  626. struct bna_rx *rx,
  627. struct bna_rx_config *q_config,
  628. struct bna_res_info *res_info)
  629. {
  630. rxf->rx = rx;
  631. INIT_LIST_HEAD(&rxf->ucast_pending_add_q);
  632. INIT_LIST_HEAD(&rxf->ucast_pending_del_q);
  633. rxf->ucast_pending_set = 0;
  634. rxf->ucast_active_set = 0;
  635. INIT_LIST_HEAD(&rxf->ucast_active_q);
  636. rxf->ucast_pending_mac = NULL;
  637. INIT_LIST_HEAD(&rxf->mcast_pending_add_q);
  638. INIT_LIST_HEAD(&rxf->mcast_pending_del_q);
  639. INIT_LIST_HEAD(&rxf->mcast_active_q);
  640. INIT_LIST_HEAD(&rxf->mcast_handle_q);
  641. if (q_config->paused)
  642. rxf->flags |= BNA_RXF_F_PAUSED;
  643. rxf->rit = (u8 *)
  644. res_info[BNA_RX_RES_MEM_T_RIT].res_u.mem_info.mdl[0].kva;
  645. bna_rit_init(rxf, q_config->num_paths);
  646. rxf->rss_status = q_config->rss_status;
  647. if (rxf->rss_status == BNA_STATUS_T_ENABLED) {
  648. rxf->rss_cfg = q_config->rss_config;
  649. rxf->rss_pending |= BNA_RSS_F_CFG_PENDING;
  650. rxf->rss_pending |= BNA_RSS_F_RIT_PENDING;
  651. rxf->rss_pending |= BNA_RSS_F_STATUS_PENDING;
  652. }
  653. rxf->vlan_filter_status = BNA_STATUS_T_DISABLED;
  654. memset(rxf->vlan_filter_table, 0,
  655. (sizeof(u32) * (BFI_ENET_VLAN_ID_MAX / 32)));
  656. rxf->vlan_filter_table[0] |= 1; /* for pure priority tagged frames */
  657. rxf->vlan_pending_bitmask = (u8)BFI_VLAN_BMASK_ALL;
  658. rxf->vlan_strip_status = q_config->vlan_strip_status;
  659. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  660. }
  661. static void
  662. bna_rxf_uninit(struct bna_rxf *rxf)
  663. {
  664. struct bna_mac *mac;
  665. rxf->ucast_pending_set = 0;
  666. rxf->ucast_active_set = 0;
  667. while (!list_empty(&rxf->ucast_pending_add_q)) {
  668. bfa_q_deq(&rxf->ucast_pending_add_q, &mac);
  669. bfa_q_qe_init(&mac->qe);
  670. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  671. }
  672. if (rxf->ucast_pending_mac) {
  673. bfa_q_qe_init(&rxf->ucast_pending_mac->qe);
  674. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod,
  675. rxf->ucast_pending_mac);
  676. rxf->ucast_pending_mac = NULL;
  677. }
  678. while (!list_empty(&rxf->mcast_pending_add_q)) {
  679. bfa_q_deq(&rxf->mcast_pending_add_q, &mac);
  680. bfa_q_qe_init(&mac->qe);
  681. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  682. }
  683. rxf->rxmode_pending = 0;
  684. rxf->rxmode_pending_bitmask = 0;
  685. if (rxf->rx->bna->promisc_rid == rxf->rx->rid)
  686. rxf->rx->bna->promisc_rid = BFI_INVALID_RID;
  687. if (rxf->rx->bna->default_mode_rid == rxf->rx->rid)
  688. rxf->rx->bna->default_mode_rid = BFI_INVALID_RID;
  689. rxf->rss_pending = 0;
  690. rxf->vlan_strip_pending = false;
  691. rxf->flags = 0;
  692. rxf->rx = NULL;
  693. }
  694. static void
  695. bna_rx_cb_rxf_started(struct bna_rx *rx)
  696. {
  697. bfa_fsm_send_event(rx, RX_E_RXF_STARTED);
  698. }
  699. static void
  700. bna_rxf_start(struct bna_rxf *rxf)
  701. {
  702. rxf->start_cbfn = bna_rx_cb_rxf_started;
  703. rxf->start_cbarg = rxf->rx;
  704. bfa_fsm_send_event(rxf, RXF_E_START);
  705. }
  706. static void
  707. bna_rx_cb_rxf_stopped(struct bna_rx *rx)
  708. {
  709. bfa_fsm_send_event(rx, RX_E_RXF_STOPPED);
  710. }
  711. static void
  712. bna_rxf_stop(struct bna_rxf *rxf)
  713. {
  714. rxf->stop_cbfn = bna_rx_cb_rxf_stopped;
  715. rxf->stop_cbarg = rxf->rx;
  716. bfa_fsm_send_event(rxf, RXF_E_STOP);
  717. }
  718. static void
  719. bna_rxf_fail(struct bna_rxf *rxf)
  720. {
  721. bfa_fsm_send_event(rxf, RXF_E_FAIL);
  722. }
  723. enum bna_cb_status
  724. bna_rx_ucast_set(struct bna_rx *rx, u8 *ucmac,
  725. void (*cbfn)(struct bnad *, struct bna_rx *))
  726. {
  727. struct bna_rxf *rxf = &rx->rxf;
  728. if (rxf->ucast_pending_mac == NULL) {
  729. rxf->ucast_pending_mac =
  730. bna_ucam_mod_mac_get(&rxf->rx->bna->ucam_mod);
  731. if (rxf->ucast_pending_mac == NULL)
  732. return BNA_CB_UCAST_CAM_FULL;
  733. bfa_q_qe_init(&rxf->ucast_pending_mac->qe);
  734. }
  735. memcpy(rxf->ucast_pending_mac->addr, ucmac, ETH_ALEN);
  736. rxf->ucast_pending_set = 1;
  737. rxf->cam_fltr_cbfn = cbfn;
  738. rxf->cam_fltr_cbarg = rx->bna->bnad;
  739. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  740. return BNA_CB_SUCCESS;
  741. }
  742. enum bna_cb_status
  743. bna_rx_mcast_add(struct bna_rx *rx, u8 *addr,
  744. void (*cbfn)(struct bnad *, struct bna_rx *))
  745. {
  746. struct bna_rxf *rxf = &rx->rxf;
  747. struct bna_mac *mac;
  748. /* Check if already added or pending addition */
  749. if (bna_mac_find(&rxf->mcast_active_q, addr) ||
  750. bna_mac_find(&rxf->mcast_pending_add_q, addr)) {
  751. if (cbfn)
  752. cbfn(rx->bna->bnad, rx);
  753. return BNA_CB_SUCCESS;
  754. }
  755. mac = bna_mcam_mod_mac_get(&rxf->rx->bna->mcam_mod);
  756. if (mac == NULL)
  757. return BNA_CB_MCAST_LIST_FULL;
  758. bfa_q_qe_init(&mac->qe);
  759. memcpy(mac->addr, addr, ETH_ALEN);
  760. list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
  761. rxf->cam_fltr_cbfn = cbfn;
  762. rxf->cam_fltr_cbarg = rx->bna->bnad;
  763. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  764. return BNA_CB_SUCCESS;
  765. }
  766. enum bna_cb_status
  767. bna_rx_mcast_listset(struct bna_rx *rx, int count, u8 *mclist,
  768. void (*cbfn)(struct bnad *, struct bna_rx *))
  769. {
  770. struct bna_rxf *rxf = &rx->rxf;
  771. struct list_head list_head;
  772. struct list_head *qe;
  773. u8 *mcaddr;
  774. struct bna_mac *mac;
  775. int i;
  776. /* Allocate nodes */
  777. INIT_LIST_HEAD(&list_head);
  778. for (i = 0, mcaddr = mclist; i < count; i++) {
  779. mac = bna_mcam_mod_mac_get(&rxf->rx->bna->mcam_mod);
  780. if (mac == NULL)
  781. goto err_return;
  782. bfa_q_qe_init(&mac->qe);
  783. memcpy(mac->addr, mcaddr, ETH_ALEN);
  784. list_add_tail(&mac->qe, &list_head);
  785. mcaddr += ETH_ALEN;
  786. }
  787. /* Purge the pending_add_q */
  788. while (!list_empty(&rxf->mcast_pending_add_q)) {
  789. bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
  790. bfa_q_qe_init(qe);
  791. mac = (struct bna_mac *)qe;
  792. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  793. }
  794. /* Schedule active_q entries for deletion */
  795. while (!list_empty(&rxf->mcast_active_q)) {
  796. bfa_q_deq(&rxf->mcast_active_q, &qe);
  797. mac = (struct bna_mac *)qe;
  798. bfa_q_qe_init(&mac->qe);
  799. list_add_tail(&mac->qe, &rxf->mcast_pending_del_q);
  800. }
  801. /* Add the new entries */
  802. while (!list_empty(&list_head)) {
  803. bfa_q_deq(&list_head, &qe);
  804. mac = (struct bna_mac *)qe;
  805. bfa_q_qe_init(&mac->qe);
  806. list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
  807. }
  808. rxf->cam_fltr_cbfn = cbfn;
  809. rxf->cam_fltr_cbarg = rx->bna->bnad;
  810. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  811. return BNA_CB_SUCCESS;
  812. err_return:
  813. while (!list_empty(&list_head)) {
  814. bfa_q_deq(&list_head, &qe);
  815. mac = (struct bna_mac *)qe;
  816. bfa_q_qe_init(&mac->qe);
  817. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  818. }
  819. return BNA_CB_MCAST_LIST_FULL;
  820. }
  821. void
  822. bna_rx_vlan_add(struct bna_rx *rx, int vlan_id)
  823. {
  824. struct bna_rxf *rxf = &rx->rxf;
  825. int index = (vlan_id >> BFI_VLAN_WORD_SHIFT);
  826. int bit = (1 << (vlan_id & BFI_VLAN_WORD_MASK));
  827. int group_id = (vlan_id >> BFI_VLAN_BLOCK_SHIFT);
  828. rxf->vlan_filter_table[index] |= bit;
  829. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
  830. rxf->vlan_pending_bitmask |= (1 << group_id);
  831. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  832. }
  833. }
  834. void
  835. bna_rx_vlan_del(struct bna_rx *rx, int vlan_id)
  836. {
  837. struct bna_rxf *rxf = &rx->rxf;
  838. int index = (vlan_id >> BFI_VLAN_WORD_SHIFT);
  839. int bit = (1 << (vlan_id & BFI_VLAN_WORD_MASK));
  840. int group_id = (vlan_id >> BFI_VLAN_BLOCK_SHIFT);
  841. rxf->vlan_filter_table[index] &= ~bit;
  842. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
  843. rxf->vlan_pending_bitmask |= (1 << group_id);
  844. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  845. }
  846. }
  847. static int
  848. bna_rxf_ucast_cfg_apply(struct bna_rxf *rxf)
  849. {
  850. struct bna_mac *mac = NULL;
  851. struct list_head *qe;
  852. /* Delete MAC addresses previousely added */
  853. if (!list_empty(&rxf->ucast_pending_del_q)) {
  854. bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
  855. bfa_q_qe_init(qe);
  856. mac = (struct bna_mac *)qe;
  857. bna_bfi_ucast_req(rxf, mac, BFI_ENET_H2I_MAC_UCAST_DEL_REQ);
  858. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  859. return 1;
  860. }
  861. /* Set default unicast MAC */
  862. if (rxf->ucast_pending_set) {
  863. rxf->ucast_pending_set = 0;
  864. memcpy(rxf->ucast_active_mac.addr,
  865. rxf->ucast_pending_mac->addr, ETH_ALEN);
  866. rxf->ucast_active_set = 1;
  867. bna_bfi_ucast_req(rxf, &rxf->ucast_active_mac,
  868. BFI_ENET_H2I_MAC_UCAST_SET_REQ);
  869. return 1;
  870. }
  871. /* Add additional MAC entries */
  872. if (!list_empty(&rxf->ucast_pending_add_q)) {
  873. bfa_q_deq(&rxf->ucast_pending_add_q, &qe);
  874. bfa_q_qe_init(qe);
  875. mac = (struct bna_mac *)qe;
  876. list_add_tail(&mac->qe, &rxf->ucast_active_q);
  877. bna_bfi_ucast_req(rxf, mac, BFI_ENET_H2I_MAC_UCAST_ADD_REQ);
  878. return 1;
  879. }
  880. return 0;
  881. }
  882. static int
  883. bna_rxf_ucast_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  884. {
  885. struct list_head *qe;
  886. struct bna_mac *mac;
  887. /* Throw away delete pending ucast entries */
  888. while (!list_empty(&rxf->ucast_pending_del_q)) {
  889. bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
  890. bfa_q_qe_init(qe);
  891. mac = (struct bna_mac *)qe;
  892. if (cleanup == BNA_SOFT_CLEANUP)
  893. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  894. else {
  895. bna_bfi_ucast_req(rxf, mac,
  896. BFI_ENET_H2I_MAC_UCAST_DEL_REQ);
  897. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  898. return 1;
  899. }
  900. }
  901. /* Move active ucast entries to pending_add_q */
  902. while (!list_empty(&rxf->ucast_active_q)) {
  903. bfa_q_deq(&rxf->ucast_active_q, &qe);
  904. bfa_q_qe_init(qe);
  905. list_add_tail(qe, &rxf->ucast_pending_add_q);
  906. if (cleanup == BNA_HARD_CLEANUP) {
  907. mac = (struct bna_mac *)qe;
  908. bna_bfi_ucast_req(rxf, mac,
  909. BFI_ENET_H2I_MAC_UCAST_DEL_REQ);
  910. return 1;
  911. }
  912. }
  913. if (rxf->ucast_active_set) {
  914. rxf->ucast_pending_set = 1;
  915. rxf->ucast_active_set = 0;
  916. if (cleanup == BNA_HARD_CLEANUP) {
  917. bna_bfi_ucast_req(rxf, &rxf->ucast_active_mac,
  918. BFI_ENET_H2I_MAC_UCAST_CLR_REQ);
  919. return 1;
  920. }
  921. }
  922. return 0;
  923. }
  924. static int
  925. bna_rxf_promisc_cfg_apply(struct bna_rxf *rxf)
  926. {
  927. struct bna *bna = rxf->rx->bna;
  928. /* Enable/disable promiscuous mode */
  929. if (is_promisc_enable(rxf->rxmode_pending,
  930. rxf->rxmode_pending_bitmask)) {
  931. /* move promisc configuration from pending -> active */
  932. promisc_inactive(rxf->rxmode_pending,
  933. rxf->rxmode_pending_bitmask);
  934. rxf->rxmode_active |= BNA_RXMODE_PROMISC;
  935. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_ENABLED);
  936. return 1;
  937. } else if (is_promisc_disable(rxf->rxmode_pending,
  938. rxf->rxmode_pending_bitmask)) {
  939. /* move promisc configuration from pending -> active */
  940. promisc_inactive(rxf->rxmode_pending,
  941. rxf->rxmode_pending_bitmask);
  942. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  943. bna->promisc_rid = BFI_INVALID_RID;
  944. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_DISABLED);
  945. return 1;
  946. }
  947. return 0;
  948. }
  949. static int
  950. bna_rxf_promisc_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  951. {
  952. struct bna *bna = rxf->rx->bna;
  953. /* Clear pending promisc mode disable */
  954. if (is_promisc_disable(rxf->rxmode_pending,
  955. rxf->rxmode_pending_bitmask)) {
  956. promisc_inactive(rxf->rxmode_pending,
  957. rxf->rxmode_pending_bitmask);
  958. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  959. bna->promisc_rid = BFI_INVALID_RID;
  960. if (cleanup == BNA_HARD_CLEANUP) {
  961. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_DISABLED);
  962. return 1;
  963. }
  964. }
  965. /* Move promisc mode config from active -> pending */
  966. if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  967. promisc_enable(rxf->rxmode_pending,
  968. rxf->rxmode_pending_bitmask);
  969. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  970. if (cleanup == BNA_HARD_CLEANUP) {
  971. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_DISABLED);
  972. return 1;
  973. }
  974. }
  975. return 0;
  976. }
  977. static int
  978. bna_rxf_allmulti_cfg_apply(struct bna_rxf *rxf)
  979. {
  980. /* Enable/disable allmulti mode */
  981. if (is_allmulti_enable(rxf->rxmode_pending,
  982. rxf->rxmode_pending_bitmask)) {
  983. /* move allmulti configuration from pending -> active */
  984. allmulti_inactive(rxf->rxmode_pending,
  985. rxf->rxmode_pending_bitmask);
  986. rxf->rxmode_active |= BNA_RXMODE_ALLMULTI;
  987. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_DISABLED);
  988. return 1;
  989. } else if (is_allmulti_disable(rxf->rxmode_pending,
  990. rxf->rxmode_pending_bitmask)) {
  991. /* move allmulti configuration from pending -> active */
  992. allmulti_inactive(rxf->rxmode_pending,
  993. rxf->rxmode_pending_bitmask);
  994. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  995. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_ENABLED);
  996. return 1;
  997. }
  998. return 0;
  999. }
  1000. static int
  1001. bna_rxf_allmulti_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  1002. {
  1003. /* Clear pending allmulti mode disable */
  1004. if (is_allmulti_disable(rxf->rxmode_pending,
  1005. rxf->rxmode_pending_bitmask)) {
  1006. allmulti_inactive(rxf->rxmode_pending,
  1007. rxf->rxmode_pending_bitmask);
  1008. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1009. if (cleanup == BNA_HARD_CLEANUP) {
  1010. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_ENABLED);
  1011. return 1;
  1012. }
  1013. }
  1014. /* Move allmulti mode config from active -> pending */
  1015. if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  1016. allmulti_enable(rxf->rxmode_pending,
  1017. rxf->rxmode_pending_bitmask);
  1018. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1019. if (cleanup == BNA_HARD_CLEANUP) {
  1020. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_ENABLED);
  1021. return 1;
  1022. }
  1023. }
  1024. return 0;
  1025. }
  1026. static int
  1027. bna_rxf_promisc_enable(struct bna_rxf *rxf)
  1028. {
  1029. struct bna *bna = rxf->rx->bna;
  1030. int ret = 0;
  1031. if (is_promisc_enable(rxf->rxmode_pending,
  1032. rxf->rxmode_pending_bitmask) ||
  1033. (rxf->rxmode_active & BNA_RXMODE_PROMISC)) {
  1034. /* Do nothing if pending enable or already enabled */
  1035. } else if (is_promisc_disable(rxf->rxmode_pending,
  1036. rxf->rxmode_pending_bitmask)) {
  1037. /* Turn off pending disable command */
  1038. promisc_inactive(rxf->rxmode_pending,
  1039. rxf->rxmode_pending_bitmask);
  1040. } else {
  1041. /* Schedule enable */
  1042. promisc_enable(rxf->rxmode_pending,
  1043. rxf->rxmode_pending_bitmask);
  1044. bna->promisc_rid = rxf->rx->rid;
  1045. ret = 1;
  1046. }
  1047. return ret;
  1048. }
  1049. static int
  1050. bna_rxf_promisc_disable(struct bna_rxf *rxf)
  1051. {
  1052. struct bna *bna = rxf->rx->bna;
  1053. int ret = 0;
  1054. if (is_promisc_disable(rxf->rxmode_pending,
  1055. rxf->rxmode_pending_bitmask) ||
  1056. (!(rxf->rxmode_active & BNA_RXMODE_PROMISC))) {
  1057. /* Do nothing if pending disable or already disabled */
  1058. } else if (is_promisc_enable(rxf->rxmode_pending,
  1059. rxf->rxmode_pending_bitmask)) {
  1060. /* Turn off pending enable command */
  1061. promisc_inactive(rxf->rxmode_pending,
  1062. rxf->rxmode_pending_bitmask);
  1063. bna->promisc_rid = BFI_INVALID_RID;
  1064. } else if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  1065. /* Schedule disable */
  1066. promisc_disable(rxf->rxmode_pending,
  1067. rxf->rxmode_pending_bitmask);
  1068. ret = 1;
  1069. }
  1070. return ret;
  1071. }
  1072. static int
  1073. bna_rxf_allmulti_enable(struct bna_rxf *rxf)
  1074. {
  1075. int ret = 0;
  1076. if (is_allmulti_enable(rxf->rxmode_pending,
  1077. rxf->rxmode_pending_bitmask) ||
  1078. (rxf->rxmode_active & BNA_RXMODE_ALLMULTI)) {
  1079. /* Do nothing if pending enable or already enabled */
  1080. } else if (is_allmulti_disable(rxf->rxmode_pending,
  1081. rxf->rxmode_pending_bitmask)) {
  1082. /* Turn off pending disable command */
  1083. allmulti_inactive(rxf->rxmode_pending,
  1084. rxf->rxmode_pending_bitmask);
  1085. } else {
  1086. /* Schedule enable */
  1087. allmulti_enable(rxf->rxmode_pending,
  1088. rxf->rxmode_pending_bitmask);
  1089. ret = 1;
  1090. }
  1091. return ret;
  1092. }
  1093. static int
  1094. bna_rxf_allmulti_disable(struct bna_rxf *rxf)
  1095. {
  1096. int ret = 0;
  1097. if (is_allmulti_disable(rxf->rxmode_pending,
  1098. rxf->rxmode_pending_bitmask) ||
  1099. (!(rxf->rxmode_active & BNA_RXMODE_ALLMULTI))) {
  1100. /* Do nothing if pending disable or already disabled */
  1101. } else if (is_allmulti_enable(rxf->rxmode_pending,
  1102. rxf->rxmode_pending_bitmask)) {
  1103. /* Turn off pending enable command */
  1104. allmulti_inactive(rxf->rxmode_pending,
  1105. rxf->rxmode_pending_bitmask);
  1106. } else if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  1107. /* Schedule disable */
  1108. allmulti_disable(rxf->rxmode_pending,
  1109. rxf->rxmode_pending_bitmask);
  1110. ret = 1;
  1111. }
  1112. return ret;
  1113. }
  1114. static int
  1115. bna_rxf_vlan_strip_cfg_apply(struct bna_rxf *rxf)
  1116. {
  1117. if (rxf->vlan_strip_pending) {
  1118. rxf->vlan_strip_pending = false;
  1119. bna_bfi_vlan_strip_enable(rxf);
  1120. return 1;
  1121. }
  1122. return 0;
  1123. }
  1124. /**
  1125. * RX
  1126. */
  1127. #define BNA_GET_RXQS(qcfg) (((qcfg)->rxp_type == BNA_RXP_SINGLE) ? \
  1128. (qcfg)->num_paths : ((qcfg)->num_paths * 2))
  1129. #define SIZE_TO_PAGES(size) (((size) >> PAGE_SHIFT) + ((((size) &\
  1130. (PAGE_SIZE - 1)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT))
  1131. #define call_rx_stop_cbfn(rx) \
  1132. do { \
  1133. if ((rx)->stop_cbfn) { \
  1134. void (*cbfn)(void *, struct bna_rx *); \
  1135. void *cbarg; \
  1136. cbfn = (rx)->stop_cbfn; \
  1137. cbarg = (rx)->stop_cbarg; \
  1138. (rx)->stop_cbfn = NULL; \
  1139. (rx)->stop_cbarg = NULL; \
  1140. cbfn(cbarg, rx); \
  1141. } \
  1142. } while (0)
  1143. #define call_rx_stall_cbfn(rx) \
  1144. do { \
  1145. if ((rx)->rx_stall_cbfn) \
  1146. (rx)->rx_stall_cbfn((rx)->bna->bnad, (rx)); \
  1147. } while (0)
  1148. #define bfi_enet_datapath_q_init(bfi_q, bna_qpt) \
  1149. do { \
  1150. struct bna_dma_addr cur_q_addr = \
  1151. *((struct bna_dma_addr *)((bna_qpt)->kv_qpt_ptr)); \
  1152. (bfi_q)->pg_tbl.a32.addr_lo = (bna_qpt)->hw_qpt_ptr.lsb; \
  1153. (bfi_q)->pg_tbl.a32.addr_hi = (bna_qpt)->hw_qpt_ptr.msb; \
  1154. (bfi_q)->first_entry.a32.addr_lo = cur_q_addr.lsb; \
  1155. (bfi_q)->first_entry.a32.addr_hi = cur_q_addr.msb; \
  1156. (bfi_q)->pages = htons((u16)(bna_qpt)->page_count); \
  1157. (bfi_q)->page_sz = htons((u16)(bna_qpt)->page_size);\
  1158. } while (0)
  1159. static void bna_bfi_rx_enet_start(struct bna_rx *rx);
  1160. static void bna_rx_enet_stop(struct bna_rx *rx);
  1161. static void bna_rx_mod_cb_rx_stopped(void *arg, struct bna_rx *rx);
  1162. bfa_fsm_state_decl(bna_rx, stopped,
  1163. struct bna_rx, enum bna_rx_event);
  1164. bfa_fsm_state_decl(bna_rx, start_wait,
  1165. struct bna_rx, enum bna_rx_event);
  1166. bfa_fsm_state_decl(bna_rx, rxf_start_wait,
  1167. struct bna_rx, enum bna_rx_event);
  1168. bfa_fsm_state_decl(bna_rx, started,
  1169. struct bna_rx, enum bna_rx_event);
  1170. bfa_fsm_state_decl(bna_rx, rxf_stop_wait,
  1171. struct bna_rx, enum bna_rx_event);
  1172. bfa_fsm_state_decl(bna_rx, stop_wait,
  1173. struct bna_rx, enum bna_rx_event);
  1174. bfa_fsm_state_decl(bna_rx, cleanup_wait,
  1175. struct bna_rx, enum bna_rx_event);
  1176. bfa_fsm_state_decl(bna_rx, failed,
  1177. struct bna_rx, enum bna_rx_event);
  1178. bfa_fsm_state_decl(bna_rx, quiesce_wait,
  1179. struct bna_rx, enum bna_rx_event);
  1180. static void bna_rx_sm_stopped_entry(struct bna_rx *rx)
  1181. {
  1182. call_rx_stop_cbfn(rx);
  1183. }
  1184. static void bna_rx_sm_stopped(struct bna_rx *rx,
  1185. enum bna_rx_event event)
  1186. {
  1187. switch (event) {
  1188. case RX_E_START:
  1189. bfa_fsm_set_state(rx, bna_rx_sm_start_wait);
  1190. break;
  1191. case RX_E_STOP:
  1192. call_rx_stop_cbfn(rx);
  1193. break;
  1194. case RX_E_FAIL:
  1195. /* no-op */
  1196. break;
  1197. default:
  1198. bfa_sm_fault(event);
  1199. break;
  1200. }
  1201. }
  1202. static void bna_rx_sm_start_wait_entry(struct bna_rx *rx)
  1203. {
  1204. bna_bfi_rx_enet_start(rx);
  1205. }
  1206. void
  1207. bna_rx_sm_stop_wait_entry(struct bna_rx *rx)
  1208. {
  1209. }
  1210. static void
  1211. bna_rx_sm_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
  1212. {
  1213. switch (event) {
  1214. case RX_E_FAIL:
  1215. case RX_E_STOPPED:
  1216. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1217. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1218. break;
  1219. case RX_E_STARTED:
  1220. bna_rx_enet_stop(rx);
  1221. break;
  1222. default:
  1223. bfa_sm_fault(event);
  1224. break;
  1225. }
  1226. }
  1227. static void bna_rx_sm_start_wait(struct bna_rx *rx,
  1228. enum bna_rx_event event)
  1229. {
  1230. switch (event) {
  1231. case RX_E_STOP:
  1232. bfa_fsm_set_state(rx, bna_rx_sm_stop_wait);
  1233. break;
  1234. case RX_E_FAIL:
  1235. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1236. break;
  1237. case RX_E_STARTED:
  1238. bfa_fsm_set_state(rx, bna_rx_sm_rxf_start_wait);
  1239. break;
  1240. default:
  1241. bfa_sm_fault(event);
  1242. break;
  1243. }
  1244. }
  1245. static void bna_rx_sm_rxf_start_wait_entry(struct bna_rx *rx)
  1246. {
  1247. rx->rx_post_cbfn(rx->bna->bnad, rx);
  1248. bna_rxf_start(&rx->rxf);
  1249. }
  1250. void
  1251. bna_rx_sm_rxf_stop_wait_entry(struct bna_rx *rx)
  1252. {
  1253. }
  1254. static void
  1255. bna_rx_sm_rxf_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
  1256. {
  1257. switch (event) {
  1258. case RX_E_FAIL:
  1259. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1260. bna_rxf_fail(&rx->rxf);
  1261. call_rx_stall_cbfn(rx);
  1262. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1263. break;
  1264. case RX_E_RXF_STARTED:
  1265. bna_rxf_stop(&rx->rxf);
  1266. break;
  1267. case RX_E_RXF_STOPPED:
  1268. bfa_fsm_set_state(rx, bna_rx_sm_stop_wait);
  1269. call_rx_stall_cbfn(rx);
  1270. bna_rx_enet_stop(rx);
  1271. break;
  1272. default:
  1273. bfa_sm_fault(event);
  1274. break;
  1275. }
  1276. }
  1277. void
  1278. bna_rx_sm_started_entry(struct bna_rx *rx)
  1279. {
  1280. struct bna_rxp *rxp;
  1281. struct list_head *qe_rxp;
  1282. int is_regular = (rx->type == BNA_RX_T_REGULAR);
  1283. /* Start IB */
  1284. list_for_each(qe_rxp, &rx->rxp_q) {
  1285. rxp = (struct bna_rxp *)qe_rxp;
  1286. bna_ib_start(rx->bna, &rxp->cq.ib, is_regular);
  1287. }
  1288. bna_ethport_cb_rx_started(&rx->bna->ethport);
  1289. }
  1290. static void
  1291. bna_rx_sm_started(struct bna_rx *rx, enum bna_rx_event event)
  1292. {
  1293. switch (event) {
  1294. case RX_E_STOP:
  1295. bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
  1296. bna_ethport_cb_rx_stopped(&rx->bna->ethport);
  1297. bna_rxf_stop(&rx->rxf);
  1298. break;
  1299. case RX_E_FAIL:
  1300. bfa_fsm_set_state(rx, bna_rx_sm_failed);
  1301. bna_ethport_cb_rx_stopped(&rx->bna->ethport);
  1302. bna_rxf_fail(&rx->rxf);
  1303. call_rx_stall_cbfn(rx);
  1304. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1305. break;
  1306. default:
  1307. bfa_sm_fault(event);
  1308. break;
  1309. }
  1310. }
  1311. static void bna_rx_sm_rxf_start_wait(struct bna_rx *rx,
  1312. enum bna_rx_event event)
  1313. {
  1314. switch (event) {
  1315. case RX_E_STOP:
  1316. bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
  1317. break;
  1318. case RX_E_FAIL:
  1319. bfa_fsm_set_state(rx, bna_rx_sm_failed);
  1320. bna_rxf_fail(&rx->rxf);
  1321. call_rx_stall_cbfn(rx);
  1322. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1323. break;
  1324. case RX_E_RXF_STARTED:
  1325. bfa_fsm_set_state(rx, bna_rx_sm_started);
  1326. break;
  1327. default:
  1328. bfa_sm_fault(event);
  1329. break;
  1330. }
  1331. }
  1332. void
  1333. bna_rx_sm_cleanup_wait_entry(struct bna_rx *rx)
  1334. {
  1335. }
  1336. void
  1337. bna_rx_sm_cleanup_wait(struct bna_rx *rx, enum bna_rx_event event)
  1338. {
  1339. switch (event) {
  1340. case RX_E_FAIL:
  1341. case RX_E_RXF_STOPPED:
  1342. /* No-op */
  1343. break;
  1344. case RX_E_CLEANUP_DONE:
  1345. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1346. break;
  1347. default:
  1348. bfa_sm_fault(event);
  1349. break;
  1350. }
  1351. }
  1352. static void
  1353. bna_rx_sm_failed_entry(struct bna_rx *rx)
  1354. {
  1355. }
  1356. static void
  1357. bna_rx_sm_failed(struct bna_rx *rx, enum bna_rx_event event)
  1358. {
  1359. switch (event) {
  1360. case RX_E_START:
  1361. bfa_fsm_set_state(rx, bna_rx_sm_quiesce_wait);
  1362. break;
  1363. case RX_E_STOP:
  1364. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1365. break;
  1366. case RX_E_FAIL:
  1367. case RX_E_RXF_STARTED:
  1368. case RX_E_RXF_STOPPED:
  1369. /* No-op */
  1370. break;
  1371. case RX_E_CLEANUP_DONE:
  1372. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1373. break;
  1374. default:
  1375. bfa_sm_fault(event);
  1376. break;
  1377. } }
  1378. static void
  1379. bna_rx_sm_quiesce_wait_entry(struct bna_rx *rx)
  1380. {
  1381. }
  1382. static void
  1383. bna_rx_sm_quiesce_wait(struct bna_rx *rx, enum bna_rx_event event)
  1384. {
  1385. switch (event) {
  1386. case RX_E_STOP:
  1387. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1388. break;
  1389. case RX_E_FAIL:
  1390. bfa_fsm_set_state(rx, bna_rx_sm_failed);
  1391. break;
  1392. case RX_E_CLEANUP_DONE:
  1393. bfa_fsm_set_state(rx, bna_rx_sm_start_wait);
  1394. break;
  1395. default:
  1396. bfa_sm_fault(event);
  1397. break;
  1398. }
  1399. }
  1400. static void
  1401. bna_bfi_rx_enet_start(struct bna_rx *rx)
  1402. {
  1403. struct bfi_enet_rx_cfg_req *cfg_req = &rx->bfi_enet_cmd.cfg_req;
  1404. struct bna_rxp *rxp = NULL;
  1405. struct bna_rxq *q0 = NULL, *q1 = NULL;
  1406. struct list_head *rxp_qe;
  1407. int i;
  1408. bfi_msgq_mhdr_set(cfg_req->mh, BFI_MC_ENET,
  1409. BFI_ENET_H2I_RX_CFG_SET_REQ, 0, rx->rid);
  1410. cfg_req->mh.num_entries = htons(
  1411. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rx_cfg_req)));
  1412. cfg_req->num_queue_sets = rx->num_paths;
  1413. for (i = 0, rxp_qe = bfa_q_first(&rx->rxp_q);
  1414. i < rx->num_paths;
  1415. i++, rxp_qe = bfa_q_next(rxp_qe)) {
  1416. rxp = (struct bna_rxp *)rxp_qe;
  1417. GET_RXQS(rxp, q0, q1);
  1418. switch (rxp->type) {
  1419. case BNA_RXP_SLR:
  1420. case BNA_RXP_HDS:
  1421. /* Small RxQ */
  1422. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].qs.q,
  1423. &q1->qpt);
  1424. cfg_req->q_cfg[i].qs.rx_buffer_size =
  1425. htons((u16)q1->buffer_size);
  1426. /* Fall through */
  1427. case BNA_RXP_SINGLE:
  1428. /* Large/Single RxQ */
  1429. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].ql.q,
  1430. &q0->qpt);
  1431. q0->buffer_size =
  1432. bna_enet_mtu_get(&rx->bna->enet);
  1433. cfg_req->q_cfg[i].ql.rx_buffer_size =
  1434. htons((u16)q0->buffer_size);
  1435. break;
  1436. default:
  1437. BUG_ON(1);
  1438. }
  1439. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].cq.q,
  1440. &rxp->cq.qpt);
  1441. cfg_req->q_cfg[i].ib.index_addr.a32.addr_lo =
  1442. rxp->cq.ib.ib_seg_host_addr.lsb;
  1443. cfg_req->q_cfg[i].ib.index_addr.a32.addr_hi =
  1444. rxp->cq.ib.ib_seg_host_addr.msb;
  1445. cfg_req->q_cfg[i].ib.intr.msix_index =
  1446. htons((u16)rxp->cq.ib.intr_vector);
  1447. }
  1448. cfg_req->ib_cfg.int_pkt_dma = BNA_STATUS_T_DISABLED;
  1449. cfg_req->ib_cfg.int_enabled = BNA_STATUS_T_ENABLED;
  1450. cfg_req->ib_cfg.int_pkt_enabled = BNA_STATUS_T_DISABLED;
  1451. cfg_req->ib_cfg.continuous_coalescing = BNA_STATUS_T_DISABLED;
  1452. cfg_req->ib_cfg.msix = (rxp->cq.ib.intr_type == BNA_INTR_T_MSIX)
  1453. ? BNA_STATUS_T_ENABLED :
  1454. BNA_STATUS_T_DISABLED;
  1455. cfg_req->ib_cfg.coalescing_timeout =
  1456. htonl((u32)rxp->cq.ib.coalescing_timeo);
  1457. cfg_req->ib_cfg.inter_pkt_timeout =
  1458. htonl((u32)rxp->cq.ib.interpkt_timeo);
  1459. cfg_req->ib_cfg.inter_pkt_count = (u8)rxp->cq.ib.interpkt_count;
  1460. switch (rxp->type) {
  1461. case BNA_RXP_SLR:
  1462. cfg_req->rx_cfg.rxq_type = BFI_ENET_RXQ_LARGE_SMALL;
  1463. break;
  1464. case BNA_RXP_HDS:
  1465. cfg_req->rx_cfg.rxq_type = BFI_ENET_RXQ_HDS;
  1466. cfg_req->rx_cfg.hds.type = rx->hds_cfg.hdr_type;
  1467. cfg_req->rx_cfg.hds.force_offset = rx->hds_cfg.forced_offset;
  1468. cfg_req->rx_cfg.hds.max_header_size = rx->hds_cfg.forced_offset;
  1469. break;
  1470. case BNA_RXP_SINGLE:
  1471. cfg_req->rx_cfg.rxq_type = BFI_ENET_RXQ_SINGLE;
  1472. break;
  1473. default:
  1474. BUG_ON(1);
  1475. }
  1476. cfg_req->rx_cfg.strip_vlan = rx->rxf.vlan_strip_status;
  1477. bfa_msgq_cmd_set(&rx->msgq_cmd, NULL, NULL,
  1478. sizeof(struct bfi_enet_rx_cfg_req), &cfg_req->mh);
  1479. bfa_msgq_cmd_post(&rx->bna->msgq, &rx->msgq_cmd);
  1480. }
  1481. static void
  1482. bna_bfi_rx_enet_stop(struct bna_rx *rx)
  1483. {
  1484. struct bfi_enet_req *req = &rx->bfi_enet_cmd.req;
  1485. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  1486. BFI_ENET_H2I_RX_CFG_CLR_REQ, 0, rx->rid);
  1487. req->mh.num_entries = htons(
  1488. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_req)));
  1489. bfa_msgq_cmd_set(&rx->msgq_cmd, NULL, NULL, sizeof(struct bfi_enet_req),
  1490. &req->mh);
  1491. bfa_msgq_cmd_post(&rx->bna->msgq, &rx->msgq_cmd);
  1492. }
  1493. static void
  1494. bna_rx_enet_stop(struct bna_rx *rx)
  1495. {
  1496. struct bna_rxp *rxp;
  1497. struct list_head *qe_rxp;
  1498. /* Stop IB */
  1499. list_for_each(qe_rxp, &rx->rxp_q) {
  1500. rxp = (struct bna_rxp *)qe_rxp;
  1501. bna_ib_stop(rx->bna, &rxp->cq.ib);
  1502. }
  1503. bna_bfi_rx_enet_stop(rx);
  1504. }
  1505. static int
  1506. bna_rx_res_check(struct bna_rx_mod *rx_mod, struct bna_rx_config *rx_cfg)
  1507. {
  1508. if ((rx_mod->rx_free_count == 0) ||
  1509. (rx_mod->rxp_free_count == 0) ||
  1510. (rx_mod->rxq_free_count == 0))
  1511. return 0;
  1512. if (rx_cfg->rxp_type == BNA_RXP_SINGLE) {
  1513. if ((rx_mod->rxp_free_count < rx_cfg->num_paths) ||
  1514. (rx_mod->rxq_free_count < rx_cfg->num_paths))
  1515. return 0;
  1516. } else {
  1517. if ((rx_mod->rxp_free_count < rx_cfg->num_paths) ||
  1518. (rx_mod->rxq_free_count < (2 * rx_cfg->num_paths)))
  1519. return 0;
  1520. }
  1521. return 1;
  1522. }
  1523. static struct bna_rxq *
  1524. bna_rxq_get(struct bna_rx_mod *rx_mod)
  1525. {
  1526. struct bna_rxq *rxq = NULL;
  1527. struct list_head *qe = NULL;
  1528. bfa_q_deq(&rx_mod->rxq_free_q, &qe);
  1529. rx_mod->rxq_free_count--;
  1530. rxq = (struct bna_rxq *)qe;
  1531. bfa_q_qe_init(&rxq->qe);
  1532. return rxq;
  1533. }
  1534. static void
  1535. bna_rxq_put(struct bna_rx_mod *rx_mod, struct bna_rxq *rxq)
  1536. {
  1537. bfa_q_qe_init(&rxq->qe);
  1538. list_add_tail(&rxq->qe, &rx_mod->rxq_free_q);
  1539. rx_mod->rxq_free_count++;
  1540. }
  1541. static struct bna_rxp *
  1542. bna_rxp_get(struct bna_rx_mod *rx_mod)
  1543. {
  1544. struct list_head *qe = NULL;
  1545. struct bna_rxp *rxp = NULL;
  1546. bfa_q_deq(&rx_mod->rxp_free_q, &qe);
  1547. rx_mod->rxp_free_count--;
  1548. rxp = (struct bna_rxp *)qe;
  1549. bfa_q_qe_init(&rxp->qe);
  1550. return rxp;
  1551. }
  1552. static void
  1553. bna_rxp_put(struct bna_rx_mod *rx_mod, struct bna_rxp *rxp)
  1554. {
  1555. bfa_q_qe_init(&rxp->qe);
  1556. list_add_tail(&rxp->qe, &rx_mod->rxp_free_q);
  1557. rx_mod->rxp_free_count++;
  1558. }
  1559. static struct bna_rx *
  1560. bna_rx_get(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
  1561. {
  1562. struct list_head *qe = NULL;
  1563. struct bna_rx *rx = NULL;
  1564. if (type == BNA_RX_T_REGULAR) {
  1565. bfa_q_deq(&rx_mod->rx_free_q, &qe);
  1566. } else
  1567. bfa_q_deq_tail(&rx_mod->rx_free_q, &qe);
  1568. rx_mod->rx_free_count--;
  1569. rx = (struct bna_rx *)qe;
  1570. bfa_q_qe_init(&rx->qe);
  1571. list_add_tail(&rx->qe, &rx_mod->rx_active_q);
  1572. rx->type = type;
  1573. return rx;
  1574. }
  1575. static void
  1576. bna_rx_put(struct bna_rx_mod *rx_mod, struct bna_rx *rx)
  1577. {
  1578. struct list_head *prev_qe = NULL;
  1579. struct list_head *qe;
  1580. bfa_q_qe_init(&rx->qe);
  1581. list_for_each(qe, &rx_mod->rx_free_q) {
  1582. if (((struct bna_rx *)qe)->rid < rx->rid)
  1583. prev_qe = qe;
  1584. else
  1585. break;
  1586. }
  1587. if (prev_qe == NULL) {
  1588. /* This is the first entry */
  1589. bfa_q_enq_head(&rx_mod->rx_free_q, &rx->qe);
  1590. } else if (bfa_q_next(prev_qe) == &rx_mod->rx_free_q) {
  1591. /* This is the last entry */
  1592. list_add_tail(&rx->qe, &rx_mod->rx_free_q);
  1593. } else {
  1594. /* Somewhere in the middle */
  1595. bfa_q_next(&rx->qe) = bfa_q_next(prev_qe);
  1596. bfa_q_prev(&rx->qe) = prev_qe;
  1597. bfa_q_next(prev_qe) = &rx->qe;
  1598. bfa_q_prev(bfa_q_next(&rx->qe)) = &rx->qe;
  1599. }
  1600. rx_mod->rx_free_count++;
  1601. }
  1602. static void
  1603. bna_rxp_add_rxqs(struct bna_rxp *rxp, struct bna_rxq *q0,
  1604. struct bna_rxq *q1)
  1605. {
  1606. switch (rxp->type) {
  1607. case BNA_RXP_SINGLE:
  1608. rxp->rxq.single.only = q0;
  1609. rxp->rxq.single.reserved = NULL;
  1610. break;
  1611. case BNA_RXP_SLR:
  1612. rxp->rxq.slr.large = q0;
  1613. rxp->rxq.slr.small = q1;
  1614. break;
  1615. case BNA_RXP_HDS:
  1616. rxp->rxq.hds.data = q0;
  1617. rxp->rxq.hds.hdr = q1;
  1618. break;
  1619. default:
  1620. break;
  1621. }
  1622. }
  1623. static void
  1624. bna_rxq_qpt_setup(struct bna_rxq *rxq,
  1625. struct bna_rxp *rxp,
  1626. u32 page_count,
  1627. u32 page_size,
  1628. struct bna_mem_descr *qpt_mem,
  1629. struct bna_mem_descr *swqpt_mem,
  1630. struct bna_mem_descr *page_mem)
  1631. {
  1632. int i;
  1633. rxq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
  1634. rxq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
  1635. rxq->qpt.kv_qpt_ptr = qpt_mem->kva;
  1636. rxq->qpt.page_count = page_count;
  1637. rxq->qpt.page_size = page_size;
  1638. rxq->rcb->sw_qpt = (void **) swqpt_mem->kva;
  1639. for (i = 0; i < rxq->qpt.page_count; i++) {
  1640. rxq->rcb->sw_qpt[i] = page_mem[i].kva;
  1641. ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].lsb =
  1642. page_mem[i].dma.lsb;
  1643. ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].msb =
  1644. page_mem[i].dma.msb;
  1645. }
  1646. }
  1647. static void
  1648. bna_rxp_cqpt_setup(struct bna_rxp *rxp,
  1649. u32 page_count,
  1650. u32 page_size,
  1651. struct bna_mem_descr *qpt_mem,
  1652. struct bna_mem_descr *swqpt_mem,
  1653. struct bna_mem_descr *page_mem)
  1654. {
  1655. int i;
  1656. rxp->cq.qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
  1657. rxp->cq.qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
  1658. rxp->cq.qpt.kv_qpt_ptr = qpt_mem->kva;
  1659. rxp->cq.qpt.page_count = page_count;
  1660. rxp->cq.qpt.page_size = page_size;
  1661. rxp->cq.ccb->sw_qpt = (void **) swqpt_mem->kva;
  1662. for (i = 0; i < rxp->cq.qpt.page_count; i++) {
  1663. rxp->cq.ccb->sw_qpt[i] = page_mem[i].kva;
  1664. ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].lsb =
  1665. page_mem[i].dma.lsb;
  1666. ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].msb =
  1667. page_mem[i].dma.msb;
  1668. }
  1669. }
  1670. static void
  1671. bna_rx_mod_cb_rx_stopped(void *arg, struct bna_rx *rx)
  1672. {
  1673. struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg;
  1674. bfa_wc_down(&rx_mod->rx_stop_wc);
  1675. }
  1676. static void
  1677. bna_rx_mod_cb_rx_stopped_all(void *arg)
  1678. {
  1679. struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg;
  1680. if (rx_mod->stop_cbfn)
  1681. rx_mod->stop_cbfn(&rx_mod->bna->enet);
  1682. rx_mod->stop_cbfn = NULL;
  1683. }
  1684. static void
  1685. bna_rx_start(struct bna_rx *rx)
  1686. {
  1687. rx->rx_flags |= BNA_RX_F_ENET_STARTED;
  1688. if (rx->rx_flags & BNA_RX_F_ENABLED)
  1689. bfa_fsm_send_event(rx, RX_E_START);
  1690. }
  1691. static void
  1692. bna_rx_stop(struct bna_rx *rx)
  1693. {
  1694. rx->rx_flags &= ~BNA_RX_F_ENET_STARTED;
  1695. if (rx->fsm == (bfa_fsm_t) bna_rx_sm_stopped)
  1696. bna_rx_mod_cb_rx_stopped(&rx->bna->rx_mod, rx);
  1697. else {
  1698. rx->stop_cbfn = bna_rx_mod_cb_rx_stopped;
  1699. rx->stop_cbarg = &rx->bna->rx_mod;
  1700. bfa_fsm_send_event(rx, RX_E_STOP);
  1701. }
  1702. }
  1703. static void
  1704. bna_rx_fail(struct bna_rx *rx)
  1705. {
  1706. /* Indicate Enet is not enabled, and failed */
  1707. rx->rx_flags &= ~BNA_RX_F_ENET_STARTED;
  1708. bfa_fsm_send_event(rx, RX_E_FAIL);
  1709. }
  1710. void
  1711. bna_rx_mod_start(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
  1712. {
  1713. struct bna_rx *rx;
  1714. struct list_head *qe;
  1715. rx_mod->flags |= BNA_RX_MOD_F_ENET_STARTED;
  1716. if (type == BNA_RX_T_LOOPBACK)
  1717. rx_mod->flags |= BNA_RX_MOD_F_ENET_LOOPBACK;
  1718. list_for_each(qe, &rx_mod->rx_active_q) {
  1719. rx = (struct bna_rx *)qe;
  1720. if (rx->type == type)
  1721. bna_rx_start(rx);
  1722. }
  1723. }
  1724. void
  1725. bna_rx_mod_stop(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
  1726. {
  1727. struct bna_rx *rx;
  1728. struct list_head *qe;
  1729. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_STARTED;
  1730. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_LOOPBACK;
  1731. rx_mod->stop_cbfn = bna_enet_cb_rx_stopped;
  1732. bfa_wc_init(&rx_mod->rx_stop_wc, bna_rx_mod_cb_rx_stopped_all, rx_mod);
  1733. list_for_each(qe, &rx_mod->rx_active_q) {
  1734. rx = (struct bna_rx *)qe;
  1735. if (rx->type == type) {
  1736. bfa_wc_up(&rx_mod->rx_stop_wc);
  1737. bna_rx_stop(rx);
  1738. }
  1739. }
  1740. bfa_wc_wait(&rx_mod->rx_stop_wc);
  1741. }
  1742. void
  1743. bna_rx_mod_fail(struct bna_rx_mod *rx_mod)
  1744. {
  1745. struct bna_rx *rx;
  1746. struct list_head *qe;
  1747. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_STARTED;
  1748. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_LOOPBACK;
  1749. list_for_each(qe, &rx_mod->rx_active_q) {
  1750. rx = (struct bna_rx *)qe;
  1751. bna_rx_fail(rx);
  1752. }
  1753. }
  1754. void bna_rx_mod_init(struct bna_rx_mod *rx_mod, struct bna *bna,
  1755. struct bna_res_info *res_info)
  1756. {
  1757. int index;
  1758. struct bna_rx *rx_ptr;
  1759. struct bna_rxp *rxp_ptr;
  1760. struct bna_rxq *rxq_ptr;
  1761. rx_mod->bna = bna;
  1762. rx_mod->flags = 0;
  1763. rx_mod->rx = (struct bna_rx *)
  1764. res_info[BNA_MOD_RES_MEM_T_RX_ARRAY].res_u.mem_info.mdl[0].kva;
  1765. rx_mod->rxp = (struct bna_rxp *)
  1766. res_info[BNA_MOD_RES_MEM_T_RXP_ARRAY].res_u.mem_info.mdl[0].kva;
  1767. rx_mod->rxq = (struct bna_rxq *)
  1768. res_info[BNA_MOD_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.mdl[0].kva;
  1769. /* Initialize the queues */
  1770. INIT_LIST_HEAD(&rx_mod->rx_free_q);
  1771. rx_mod->rx_free_count = 0;
  1772. INIT_LIST_HEAD(&rx_mod->rxq_free_q);
  1773. rx_mod->rxq_free_count = 0;
  1774. INIT_LIST_HEAD(&rx_mod->rxp_free_q);
  1775. rx_mod->rxp_free_count = 0;
  1776. INIT_LIST_HEAD(&rx_mod->rx_active_q);
  1777. /* Build RX queues */
  1778. for (index = 0; index < bna->ioceth.attr.num_rxp; index++) {
  1779. rx_ptr = &rx_mod->rx[index];
  1780. bfa_q_qe_init(&rx_ptr->qe);
  1781. INIT_LIST_HEAD(&rx_ptr->rxp_q);
  1782. rx_ptr->bna = NULL;
  1783. rx_ptr->rid = index;
  1784. rx_ptr->stop_cbfn = NULL;
  1785. rx_ptr->stop_cbarg = NULL;
  1786. list_add_tail(&rx_ptr->qe, &rx_mod->rx_free_q);
  1787. rx_mod->rx_free_count++;
  1788. }
  1789. /* build RX-path queue */
  1790. for (index = 0; index < bna->ioceth.attr.num_rxp; index++) {
  1791. rxp_ptr = &rx_mod->rxp[index];
  1792. bfa_q_qe_init(&rxp_ptr->qe);
  1793. list_add_tail(&rxp_ptr->qe, &rx_mod->rxp_free_q);
  1794. rx_mod->rxp_free_count++;
  1795. }
  1796. /* build RXQ queue */
  1797. for (index = 0; index < (bna->ioceth.attr.num_rxp * 2); index++) {
  1798. rxq_ptr = &rx_mod->rxq[index];
  1799. bfa_q_qe_init(&rxq_ptr->qe);
  1800. list_add_tail(&rxq_ptr->qe, &rx_mod->rxq_free_q);
  1801. rx_mod->rxq_free_count++;
  1802. }
  1803. }
  1804. void
  1805. bna_rx_mod_uninit(struct bna_rx_mod *rx_mod)
  1806. {
  1807. struct list_head *qe;
  1808. int i;
  1809. i = 0;
  1810. list_for_each(qe, &rx_mod->rx_free_q)
  1811. i++;
  1812. i = 0;
  1813. list_for_each(qe, &rx_mod->rxp_free_q)
  1814. i++;
  1815. i = 0;
  1816. list_for_each(qe, &rx_mod->rxq_free_q)
  1817. i++;
  1818. rx_mod->bna = NULL;
  1819. }
  1820. void
  1821. bna_bfi_rx_enet_start_rsp(struct bna_rx *rx, struct bfi_msgq_mhdr *msghdr)
  1822. {
  1823. struct bfi_enet_rx_cfg_rsp *cfg_rsp = &rx->bfi_enet_cmd.cfg_rsp;
  1824. struct bna_rxp *rxp = NULL;
  1825. struct bna_rxq *q0 = NULL, *q1 = NULL;
  1826. struct list_head *rxp_qe;
  1827. int i;
  1828. bfa_msgq_rsp_copy(&rx->bna->msgq, (u8 *)cfg_rsp,
  1829. sizeof(struct bfi_enet_rx_cfg_rsp));
  1830. rx->hw_id = cfg_rsp->hw_id;
  1831. for (i = 0, rxp_qe = bfa_q_first(&rx->rxp_q);
  1832. i < rx->num_paths;
  1833. i++, rxp_qe = bfa_q_next(rxp_qe)) {
  1834. rxp = (struct bna_rxp *)rxp_qe;
  1835. GET_RXQS(rxp, q0, q1);
  1836. /* Setup doorbells */
  1837. rxp->cq.ccb->i_dbell->doorbell_addr =
  1838. rx->bna->pcidev.pci_bar_kva
  1839. + ntohl(cfg_rsp->q_handles[i].i_dbell);
  1840. rxp->hw_id = cfg_rsp->q_handles[i].hw_cqid;
  1841. q0->rcb->q_dbell =
  1842. rx->bna->pcidev.pci_bar_kva
  1843. + ntohl(cfg_rsp->q_handles[i].ql_dbell);
  1844. q0->hw_id = cfg_rsp->q_handles[i].hw_lqid;
  1845. if (q1) {
  1846. q1->rcb->q_dbell =
  1847. rx->bna->pcidev.pci_bar_kva
  1848. + ntohl(cfg_rsp->q_handles[i].qs_dbell);
  1849. q1->hw_id = cfg_rsp->q_handles[i].hw_sqid;
  1850. }
  1851. /* Initialize producer/consumer indexes */
  1852. (*rxp->cq.ccb->hw_producer_index) = 0;
  1853. rxp->cq.ccb->producer_index = 0;
  1854. q0->rcb->producer_index = q0->rcb->consumer_index = 0;
  1855. if (q1)
  1856. q1->rcb->producer_index = q1->rcb->consumer_index = 0;
  1857. }
  1858. bfa_fsm_send_event(rx, RX_E_STARTED);
  1859. }
  1860. void
  1861. bna_bfi_rx_enet_stop_rsp(struct bna_rx *rx, struct bfi_msgq_mhdr *msghdr)
  1862. {
  1863. bfa_fsm_send_event(rx, RX_E_STOPPED);
  1864. }
  1865. void
  1866. bna_rx_res_req(struct bna_rx_config *q_cfg, struct bna_res_info *res_info)
  1867. {
  1868. u32 cq_size, hq_size, dq_size;
  1869. u32 cpage_count, hpage_count, dpage_count;
  1870. struct bna_mem_info *mem_info;
  1871. u32 cq_depth;
  1872. u32 hq_depth;
  1873. u32 dq_depth;
  1874. dq_depth = q_cfg->q_depth;
  1875. hq_depth = ((q_cfg->rxp_type == BNA_RXP_SINGLE) ? 0 : q_cfg->q_depth);
  1876. cq_depth = dq_depth + hq_depth;
  1877. BNA_TO_POWER_OF_2_HIGH(cq_depth);
  1878. cq_size = cq_depth * BFI_CQ_WI_SIZE;
  1879. cq_size = ALIGN(cq_size, PAGE_SIZE);
  1880. cpage_count = SIZE_TO_PAGES(cq_size);
  1881. BNA_TO_POWER_OF_2_HIGH(dq_depth);
  1882. dq_size = dq_depth * BFI_RXQ_WI_SIZE;
  1883. dq_size = ALIGN(dq_size, PAGE_SIZE);
  1884. dpage_count = SIZE_TO_PAGES(dq_size);
  1885. if (BNA_RXP_SINGLE != q_cfg->rxp_type) {
  1886. BNA_TO_POWER_OF_2_HIGH(hq_depth);
  1887. hq_size = hq_depth * BFI_RXQ_WI_SIZE;
  1888. hq_size = ALIGN(hq_size, PAGE_SIZE);
  1889. hpage_count = SIZE_TO_PAGES(hq_size);
  1890. } else
  1891. hpage_count = 0;
  1892. res_info[BNA_RX_RES_MEM_T_CCB].res_type = BNA_RES_T_MEM;
  1893. mem_info = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info;
  1894. mem_info->mem_type = BNA_MEM_T_KVA;
  1895. mem_info->len = sizeof(struct bna_ccb);
  1896. mem_info->num = q_cfg->num_paths;
  1897. res_info[BNA_RX_RES_MEM_T_RCB].res_type = BNA_RES_T_MEM;
  1898. mem_info = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info;
  1899. mem_info->mem_type = BNA_MEM_T_KVA;
  1900. mem_info->len = sizeof(struct bna_rcb);
  1901. mem_info->num = BNA_GET_RXQS(q_cfg);
  1902. res_info[BNA_RX_RES_MEM_T_CQPT].res_type = BNA_RES_T_MEM;
  1903. mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info;
  1904. mem_info->mem_type = BNA_MEM_T_DMA;
  1905. mem_info->len = cpage_count * sizeof(struct bna_dma_addr);
  1906. mem_info->num = q_cfg->num_paths;
  1907. res_info[BNA_RX_RES_MEM_T_CSWQPT].res_type = BNA_RES_T_MEM;
  1908. mem_info = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info;
  1909. mem_info->mem_type = BNA_MEM_T_KVA;
  1910. mem_info->len = cpage_count * sizeof(void *);
  1911. mem_info->num = q_cfg->num_paths;
  1912. res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_type = BNA_RES_T_MEM;
  1913. mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info;
  1914. mem_info->mem_type = BNA_MEM_T_DMA;
  1915. mem_info->len = PAGE_SIZE;
  1916. mem_info->num = cpage_count * q_cfg->num_paths;
  1917. res_info[BNA_RX_RES_MEM_T_DQPT].res_type = BNA_RES_T_MEM;
  1918. mem_info = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info;
  1919. mem_info->mem_type = BNA_MEM_T_DMA;
  1920. mem_info->len = dpage_count * sizeof(struct bna_dma_addr);
  1921. mem_info->num = q_cfg->num_paths;
  1922. res_info[BNA_RX_RES_MEM_T_DSWQPT].res_type = BNA_RES_T_MEM;
  1923. mem_info = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info;
  1924. mem_info->mem_type = BNA_MEM_T_KVA;
  1925. mem_info->len = dpage_count * sizeof(void *);
  1926. mem_info->num = q_cfg->num_paths;
  1927. res_info[BNA_RX_RES_MEM_T_DPAGE].res_type = BNA_RES_T_MEM;
  1928. mem_info = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info;
  1929. mem_info->mem_type = BNA_MEM_T_DMA;
  1930. mem_info->len = PAGE_SIZE;
  1931. mem_info->num = dpage_count * q_cfg->num_paths;
  1932. res_info[BNA_RX_RES_MEM_T_HQPT].res_type = BNA_RES_T_MEM;
  1933. mem_info = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info;
  1934. mem_info->mem_type = BNA_MEM_T_DMA;
  1935. mem_info->len = hpage_count * sizeof(struct bna_dma_addr);
  1936. mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
  1937. res_info[BNA_RX_RES_MEM_T_HSWQPT].res_type = BNA_RES_T_MEM;
  1938. mem_info = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info;
  1939. mem_info->mem_type = BNA_MEM_T_KVA;
  1940. mem_info->len = hpage_count * sizeof(void *);
  1941. mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
  1942. res_info[BNA_RX_RES_MEM_T_HPAGE].res_type = BNA_RES_T_MEM;
  1943. mem_info = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info;
  1944. mem_info->mem_type = BNA_MEM_T_DMA;
  1945. mem_info->len = (hpage_count ? PAGE_SIZE : 0);
  1946. mem_info->num = (hpage_count ? (hpage_count * q_cfg->num_paths) : 0);
  1947. res_info[BNA_RX_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
  1948. mem_info = &res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info;
  1949. mem_info->mem_type = BNA_MEM_T_DMA;
  1950. mem_info->len = BFI_IBIDX_SIZE;
  1951. mem_info->num = q_cfg->num_paths;
  1952. res_info[BNA_RX_RES_MEM_T_RIT].res_type = BNA_RES_T_MEM;
  1953. mem_info = &res_info[BNA_RX_RES_MEM_T_RIT].res_u.mem_info;
  1954. mem_info->mem_type = BNA_MEM_T_KVA;
  1955. mem_info->len = BFI_ENET_RSS_RIT_MAX;
  1956. mem_info->num = 1;
  1957. res_info[BNA_RX_RES_T_INTR].res_type = BNA_RES_T_INTR;
  1958. res_info[BNA_RX_RES_T_INTR].res_u.intr_info.intr_type = BNA_INTR_T_MSIX;
  1959. res_info[BNA_RX_RES_T_INTR].res_u.intr_info.num = q_cfg->num_paths;
  1960. }
  1961. struct bna_rx *
  1962. bna_rx_create(struct bna *bna, struct bnad *bnad,
  1963. struct bna_rx_config *rx_cfg,
  1964. const struct bna_rx_event_cbfn *rx_cbfn,
  1965. struct bna_res_info *res_info,
  1966. void *priv)
  1967. {
  1968. struct bna_rx_mod *rx_mod = &bna->rx_mod;
  1969. struct bna_rx *rx;
  1970. struct bna_rxp *rxp;
  1971. struct bna_rxq *q0;
  1972. struct bna_rxq *q1;
  1973. struct bna_intr_info *intr_info;
  1974. u32 page_count;
  1975. struct bna_mem_descr *ccb_mem;
  1976. struct bna_mem_descr *rcb_mem;
  1977. struct bna_mem_descr *unmapq_mem;
  1978. struct bna_mem_descr *cqpt_mem;
  1979. struct bna_mem_descr *cswqpt_mem;
  1980. struct bna_mem_descr *cpage_mem;
  1981. struct bna_mem_descr *hqpt_mem;
  1982. struct bna_mem_descr *dqpt_mem;
  1983. struct bna_mem_descr *hsqpt_mem;
  1984. struct bna_mem_descr *dsqpt_mem;
  1985. struct bna_mem_descr *hpage_mem;
  1986. struct bna_mem_descr *dpage_mem;
  1987. int i, cpage_idx = 0, dpage_idx = 0, hpage_idx = 0;
  1988. int dpage_count, hpage_count, rcb_idx;
  1989. if (!bna_rx_res_check(rx_mod, rx_cfg))
  1990. return NULL;
  1991. intr_info = &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
  1992. ccb_mem = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info.mdl[0];
  1993. rcb_mem = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info.mdl[0];
  1994. unmapq_mem = &res_info[BNA_RX_RES_MEM_T_UNMAPQ].res_u.mem_info.mdl[0];
  1995. cqpt_mem = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info.mdl[0];
  1996. cswqpt_mem = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info.mdl[0];
  1997. cpage_mem = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.mdl[0];
  1998. hqpt_mem = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info.mdl[0];
  1999. dqpt_mem = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info.mdl[0];
  2000. hsqpt_mem = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info.mdl[0];
  2001. dsqpt_mem = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info.mdl[0];
  2002. hpage_mem = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.mdl[0];
  2003. dpage_mem = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.mdl[0];
  2004. page_count = res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.num /
  2005. rx_cfg->num_paths;
  2006. dpage_count = res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.num /
  2007. rx_cfg->num_paths;
  2008. hpage_count = res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.num /
  2009. rx_cfg->num_paths;
  2010. rx = bna_rx_get(rx_mod, rx_cfg->rx_type);
  2011. rx->bna = bna;
  2012. rx->rx_flags = 0;
  2013. INIT_LIST_HEAD(&rx->rxp_q);
  2014. rx->stop_cbfn = NULL;
  2015. rx->stop_cbarg = NULL;
  2016. rx->priv = priv;
  2017. rx->rcb_setup_cbfn = rx_cbfn->rcb_setup_cbfn;
  2018. rx->rcb_destroy_cbfn = rx_cbfn->rcb_destroy_cbfn;
  2019. rx->ccb_setup_cbfn = rx_cbfn->ccb_setup_cbfn;
  2020. rx->ccb_destroy_cbfn = rx_cbfn->ccb_destroy_cbfn;
  2021. rx->rx_stall_cbfn = rx_cbfn->rx_stall_cbfn;
  2022. /* Following callbacks are mandatory */
  2023. rx->rx_cleanup_cbfn = rx_cbfn->rx_cleanup_cbfn;
  2024. rx->rx_post_cbfn = rx_cbfn->rx_post_cbfn;
  2025. if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_ENET_STARTED) {
  2026. switch (rx->type) {
  2027. case BNA_RX_T_REGULAR:
  2028. if (!(rx->bna->rx_mod.flags &
  2029. BNA_RX_MOD_F_ENET_LOOPBACK))
  2030. rx->rx_flags |= BNA_RX_F_ENET_STARTED;
  2031. break;
  2032. case BNA_RX_T_LOOPBACK:
  2033. if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_ENET_LOOPBACK)
  2034. rx->rx_flags |= BNA_RX_F_ENET_STARTED;
  2035. break;
  2036. }
  2037. }
  2038. rx->num_paths = rx_cfg->num_paths;
  2039. for (i = 0, rcb_idx = 0; i < rx->num_paths; i++) {
  2040. rxp = bna_rxp_get(rx_mod);
  2041. list_add_tail(&rxp->qe, &rx->rxp_q);
  2042. rxp->type = rx_cfg->rxp_type;
  2043. rxp->rx = rx;
  2044. rxp->cq.rx = rx;
  2045. q0 = bna_rxq_get(rx_mod);
  2046. if (BNA_RXP_SINGLE == rx_cfg->rxp_type)
  2047. q1 = NULL;
  2048. else
  2049. q1 = bna_rxq_get(rx_mod);
  2050. if (1 == intr_info->num)
  2051. rxp->vector = intr_info->idl[0].vector;
  2052. else
  2053. rxp->vector = intr_info->idl[i].vector;
  2054. /* Setup IB */
  2055. rxp->cq.ib.ib_seg_host_addr.lsb =
  2056. res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.lsb;
  2057. rxp->cq.ib.ib_seg_host_addr.msb =
  2058. res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.msb;
  2059. rxp->cq.ib.ib_seg_host_addr_kva =
  2060. res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].kva;
  2061. rxp->cq.ib.intr_type = intr_info->intr_type;
  2062. if (intr_info->intr_type == BNA_INTR_T_MSIX)
  2063. rxp->cq.ib.intr_vector = rxp->vector;
  2064. else
  2065. rxp->cq.ib.intr_vector = (1 << rxp->vector);
  2066. rxp->cq.ib.coalescing_timeo = rx_cfg->coalescing_timeo;
  2067. rxp->cq.ib.interpkt_count = BFI_RX_INTERPKT_COUNT;
  2068. rxp->cq.ib.interpkt_timeo = BFI_RX_INTERPKT_TIMEO;
  2069. bna_rxp_add_rxqs(rxp, q0, q1);
  2070. /* Setup large Q */
  2071. q0->rx = rx;
  2072. q0->rxp = rxp;
  2073. q0->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva;
  2074. q0->rcb->unmap_q = (void *)unmapq_mem[rcb_idx].kva;
  2075. rcb_idx++;
  2076. q0->rcb->q_depth = rx_cfg->q_depth;
  2077. q0->rcb->rxq = q0;
  2078. q0->rcb->bnad = bna->bnad;
  2079. q0->rcb->id = 0;
  2080. q0->rx_packets = q0->rx_bytes = 0;
  2081. q0->rx_packets_with_error = q0->rxbuf_alloc_failed = 0;
  2082. bna_rxq_qpt_setup(q0, rxp, dpage_count, PAGE_SIZE,
  2083. &dqpt_mem[i], &dsqpt_mem[i], &dpage_mem[dpage_idx]);
  2084. q0->rcb->page_idx = dpage_idx;
  2085. q0->rcb->page_count = dpage_count;
  2086. dpage_idx += dpage_count;
  2087. if (rx->rcb_setup_cbfn)
  2088. rx->rcb_setup_cbfn(bnad, q0->rcb);
  2089. /* Setup small Q */
  2090. if (q1) {
  2091. q1->rx = rx;
  2092. q1->rxp = rxp;
  2093. q1->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva;
  2094. q1->rcb->unmap_q = (void *)unmapq_mem[rcb_idx].kva;
  2095. rcb_idx++;
  2096. q1->rcb->q_depth = rx_cfg->q_depth;
  2097. q1->rcb->rxq = q1;
  2098. q1->rcb->bnad = bna->bnad;
  2099. q1->rcb->id = 1;
  2100. q1->buffer_size = (rx_cfg->rxp_type == BNA_RXP_HDS) ?
  2101. rx_cfg->hds_config.forced_offset
  2102. : rx_cfg->small_buff_size;
  2103. q1->rx_packets = q1->rx_bytes = 0;
  2104. q1->rx_packets_with_error = q1->rxbuf_alloc_failed = 0;
  2105. bna_rxq_qpt_setup(q1, rxp, hpage_count, PAGE_SIZE,
  2106. &hqpt_mem[i], &hsqpt_mem[i],
  2107. &hpage_mem[hpage_idx]);
  2108. q1->rcb->page_idx = hpage_idx;
  2109. q1->rcb->page_count = hpage_count;
  2110. hpage_idx += hpage_count;
  2111. if (rx->rcb_setup_cbfn)
  2112. rx->rcb_setup_cbfn(bnad, q1->rcb);
  2113. }
  2114. /* Setup CQ */
  2115. rxp->cq.ccb = (struct bna_ccb *) ccb_mem[i].kva;
  2116. rxp->cq.ccb->q_depth = rx_cfg->q_depth +
  2117. ((rx_cfg->rxp_type == BNA_RXP_SINGLE) ?
  2118. 0 : rx_cfg->q_depth);
  2119. rxp->cq.ccb->cq = &rxp->cq;
  2120. rxp->cq.ccb->rcb[0] = q0->rcb;
  2121. q0->rcb->ccb = rxp->cq.ccb;
  2122. if (q1) {
  2123. rxp->cq.ccb->rcb[1] = q1->rcb;
  2124. q1->rcb->ccb = rxp->cq.ccb;
  2125. }
  2126. rxp->cq.ccb->hw_producer_index =
  2127. (u32 *)rxp->cq.ib.ib_seg_host_addr_kva;
  2128. rxp->cq.ccb->i_dbell = &rxp->cq.ib.door_bell;
  2129. rxp->cq.ccb->intr_type = rxp->cq.ib.intr_type;
  2130. rxp->cq.ccb->intr_vector = rxp->cq.ib.intr_vector;
  2131. rxp->cq.ccb->rx_coalescing_timeo =
  2132. rxp->cq.ib.coalescing_timeo;
  2133. rxp->cq.ccb->pkt_rate.small_pkt_cnt = 0;
  2134. rxp->cq.ccb->pkt_rate.large_pkt_cnt = 0;
  2135. rxp->cq.ccb->bnad = bna->bnad;
  2136. rxp->cq.ccb->id = i;
  2137. bna_rxp_cqpt_setup(rxp, page_count, PAGE_SIZE,
  2138. &cqpt_mem[i], &cswqpt_mem[i], &cpage_mem[cpage_idx]);
  2139. rxp->cq.ccb->page_idx = cpage_idx;
  2140. rxp->cq.ccb->page_count = page_count;
  2141. cpage_idx += page_count;
  2142. if (rx->ccb_setup_cbfn)
  2143. rx->ccb_setup_cbfn(bnad, rxp->cq.ccb);
  2144. }
  2145. rx->hds_cfg = rx_cfg->hds_config;
  2146. bna_rxf_init(&rx->rxf, rx, rx_cfg, res_info);
  2147. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  2148. rx_mod->rid_mask |= (1 << rx->rid);
  2149. return rx;
  2150. }
  2151. void
  2152. bna_rx_destroy(struct bna_rx *rx)
  2153. {
  2154. struct bna_rx_mod *rx_mod = &rx->bna->rx_mod;
  2155. struct bna_rxq *q0 = NULL;
  2156. struct bna_rxq *q1 = NULL;
  2157. struct bna_rxp *rxp;
  2158. struct list_head *qe;
  2159. bna_rxf_uninit(&rx->rxf);
  2160. while (!list_empty(&rx->rxp_q)) {
  2161. bfa_q_deq(&rx->rxp_q, &rxp);
  2162. GET_RXQS(rxp, q0, q1);
  2163. if (rx->rcb_destroy_cbfn)
  2164. rx->rcb_destroy_cbfn(rx->bna->bnad, q0->rcb);
  2165. q0->rcb = NULL;
  2166. q0->rxp = NULL;
  2167. q0->rx = NULL;
  2168. bna_rxq_put(rx_mod, q0);
  2169. if (q1) {
  2170. if (rx->rcb_destroy_cbfn)
  2171. rx->rcb_destroy_cbfn(rx->bna->bnad, q1->rcb);
  2172. q1->rcb = NULL;
  2173. q1->rxp = NULL;
  2174. q1->rx = NULL;
  2175. bna_rxq_put(rx_mod, q1);
  2176. }
  2177. rxp->rxq.slr.large = NULL;
  2178. rxp->rxq.slr.small = NULL;
  2179. if (rx->ccb_destroy_cbfn)
  2180. rx->ccb_destroy_cbfn(rx->bna->bnad, rxp->cq.ccb);
  2181. rxp->cq.ccb = NULL;
  2182. rxp->rx = NULL;
  2183. bna_rxp_put(rx_mod, rxp);
  2184. }
  2185. list_for_each(qe, &rx_mod->rx_active_q) {
  2186. if (qe == &rx->qe) {
  2187. list_del(&rx->qe);
  2188. bfa_q_qe_init(&rx->qe);
  2189. break;
  2190. }
  2191. }
  2192. rx_mod->rid_mask &= ~(1 << rx->rid);
  2193. rx->bna = NULL;
  2194. rx->priv = NULL;
  2195. bna_rx_put(rx_mod, rx);
  2196. }
  2197. void
  2198. bna_rx_enable(struct bna_rx *rx)
  2199. {
  2200. if (rx->fsm != (bfa_sm_t)bna_rx_sm_stopped)
  2201. return;
  2202. rx->rx_flags |= BNA_RX_F_ENABLED;
  2203. if (rx->rx_flags & BNA_RX_F_ENET_STARTED)
  2204. bfa_fsm_send_event(rx, RX_E_START);
  2205. }
  2206. void
  2207. bna_rx_disable(struct bna_rx *rx, enum bna_cleanup_type type,
  2208. void (*cbfn)(void *, struct bna_rx *))
  2209. {
  2210. if (type == BNA_SOFT_CLEANUP) {
  2211. /* h/w should not be accessed. Treat we're stopped */
  2212. (*cbfn)(rx->bna->bnad, rx);
  2213. } else {
  2214. rx->stop_cbfn = cbfn;
  2215. rx->stop_cbarg = rx->bna->bnad;
  2216. rx->rx_flags &= ~BNA_RX_F_ENABLED;
  2217. bfa_fsm_send_event(rx, RX_E_STOP);
  2218. }
  2219. }
  2220. void
  2221. bna_rx_cleanup_complete(struct bna_rx *rx)
  2222. {
  2223. bfa_fsm_send_event(rx, RX_E_CLEANUP_DONE);
  2224. }
  2225. enum bna_cb_status
  2226. bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode new_mode,
  2227. enum bna_rxmode bitmask,
  2228. void (*cbfn)(struct bnad *, struct bna_rx *))
  2229. {
  2230. struct bna_rxf *rxf = &rx->rxf;
  2231. int need_hw_config = 0;
  2232. /* Error checks */
  2233. if (is_promisc_enable(new_mode, bitmask)) {
  2234. /* If promisc mode is already enabled elsewhere in the system */
  2235. if ((rx->bna->promisc_rid != BFI_INVALID_RID) &&
  2236. (rx->bna->promisc_rid != rxf->rx->rid))
  2237. goto err_return;
  2238. /* If default mode is already enabled in the system */
  2239. if (rx->bna->default_mode_rid != BFI_INVALID_RID)
  2240. goto err_return;
  2241. /* Trying to enable promiscuous and default mode together */
  2242. if (is_default_enable(new_mode, bitmask))
  2243. goto err_return;
  2244. }
  2245. if (is_default_enable(new_mode, bitmask)) {
  2246. /* If default mode is already enabled elsewhere in the system */
  2247. if ((rx->bna->default_mode_rid != BFI_INVALID_RID) &&
  2248. (rx->bna->default_mode_rid != rxf->rx->rid)) {
  2249. goto err_return;
  2250. }
  2251. /* If promiscuous mode is already enabled in the system */
  2252. if (rx->bna->promisc_rid != BFI_INVALID_RID)
  2253. goto err_return;
  2254. }
  2255. /* Process the commands */
  2256. if (is_promisc_enable(new_mode, bitmask)) {
  2257. if (bna_rxf_promisc_enable(rxf))
  2258. need_hw_config = 1;
  2259. } else if (is_promisc_disable(new_mode, bitmask)) {
  2260. if (bna_rxf_promisc_disable(rxf))
  2261. need_hw_config = 1;
  2262. }
  2263. if (is_allmulti_enable(new_mode, bitmask)) {
  2264. if (bna_rxf_allmulti_enable(rxf))
  2265. need_hw_config = 1;
  2266. } else if (is_allmulti_disable(new_mode, bitmask)) {
  2267. if (bna_rxf_allmulti_disable(rxf))
  2268. need_hw_config = 1;
  2269. }
  2270. /* Trigger h/w if needed */
  2271. if (need_hw_config) {
  2272. rxf->cam_fltr_cbfn = cbfn;
  2273. rxf->cam_fltr_cbarg = rx->bna->bnad;
  2274. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  2275. } else if (cbfn)
  2276. (*cbfn)(rx->bna->bnad, rx);
  2277. return BNA_CB_SUCCESS;
  2278. err_return:
  2279. return BNA_CB_FAIL;
  2280. }
  2281. void
  2282. bna_rx_vlanfilter_enable(struct bna_rx *rx)
  2283. {
  2284. struct bna_rxf *rxf = &rx->rxf;
  2285. if (rxf->vlan_filter_status == BNA_STATUS_T_DISABLED) {
  2286. rxf->vlan_filter_status = BNA_STATUS_T_ENABLED;
  2287. rxf->vlan_pending_bitmask = (u8)BFI_VLAN_BMASK_ALL;
  2288. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  2289. }
  2290. }
  2291. void
  2292. bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo)
  2293. {
  2294. struct bna_rxp *rxp;
  2295. struct list_head *qe;
  2296. list_for_each(qe, &rx->rxp_q) {
  2297. rxp = (struct bna_rxp *)qe;
  2298. rxp->cq.ccb->rx_coalescing_timeo = coalescing_timeo;
  2299. bna_ib_coalescing_timeo_set(&rxp->cq.ib, coalescing_timeo);
  2300. }
  2301. }
  2302. void
  2303. bna_rx_dim_reconfig(struct bna *bna, const u32 vector[][BNA_BIAS_T_MAX])
  2304. {
  2305. int i, j;
  2306. for (i = 0; i < BNA_LOAD_T_MAX; i++)
  2307. for (j = 0; j < BNA_BIAS_T_MAX; j++)
  2308. bna->rx_mod.dim_vector[i][j] = vector[i][j];
  2309. }
  2310. void
  2311. bna_rx_dim_update(struct bna_ccb *ccb)
  2312. {
  2313. struct bna *bna = ccb->cq->rx->bna;
  2314. u32 load, bias;
  2315. u32 pkt_rt, small_rt, large_rt;
  2316. u8 coalescing_timeo;
  2317. if ((ccb->pkt_rate.small_pkt_cnt == 0) &&
  2318. (ccb->pkt_rate.large_pkt_cnt == 0))
  2319. return;
  2320. /* Arrive at preconfigured coalescing timeo value based on pkt rate */
  2321. small_rt = ccb->pkt_rate.small_pkt_cnt;
  2322. large_rt = ccb->pkt_rate.large_pkt_cnt;
  2323. pkt_rt = small_rt + large_rt;
  2324. if (pkt_rt < BNA_PKT_RATE_10K)
  2325. load = BNA_LOAD_T_LOW_4;
  2326. else if (pkt_rt < BNA_PKT_RATE_20K)
  2327. load = BNA_LOAD_T_LOW_3;
  2328. else if (pkt_rt < BNA_PKT_RATE_30K)
  2329. load = BNA_LOAD_T_LOW_2;
  2330. else if (pkt_rt < BNA_PKT_RATE_40K)
  2331. load = BNA_LOAD_T_LOW_1;
  2332. else if (pkt_rt < BNA_PKT_RATE_50K)
  2333. load = BNA_LOAD_T_HIGH_1;
  2334. else if (pkt_rt < BNA_PKT_RATE_60K)
  2335. load = BNA_LOAD_T_HIGH_2;
  2336. else if (pkt_rt < BNA_PKT_RATE_80K)
  2337. load = BNA_LOAD_T_HIGH_3;
  2338. else
  2339. load = BNA_LOAD_T_HIGH_4;
  2340. if (small_rt > (large_rt << 1))
  2341. bias = 0;
  2342. else
  2343. bias = 1;
  2344. ccb->pkt_rate.small_pkt_cnt = 0;
  2345. ccb->pkt_rate.large_pkt_cnt = 0;
  2346. coalescing_timeo = bna->rx_mod.dim_vector[load][bias];
  2347. ccb->rx_coalescing_timeo = coalescing_timeo;
  2348. /* Set it to IB */
  2349. bna_ib_coalescing_timeo_set(&ccb->cq->ib, coalescing_timeo);
  2350. }
  2351. const u32 bna_napi_dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX] = {
  2352. {12, 12},
  2353. {6, 10},
  2354. {5, 10},
  2355. {4, 8},
  2356. {3, 6},
  2357. {3, 6},
  2358. {2, 4},
  2359. {1, 2},
  2360. };
  2361. /**
  2362. * TX
  2363. */
  2364. #define call_tx_stop_cbfn(tx) \
  2365. do { \
  2366. if ((tx)->stop_cbfn) { \
  2367. void (*cbfn)(void *, struct bna_tx *); \
  2368. void *cbarg; \
  2369. cbfn = (tx)->stop_cbfn; \
  2370. cbarg = (tx)->stop_cbarg; \
  2371. (tx)->stop_cbfn = NULL; \
  2372. (tx)->stop_cbarg = NULL; \
  2373. cbfn(cbarg, (tx)); \
  2374. } \
  2375. } while (0)
  2376. #define call_tx_prio_change_cbfn(tx) \
  2377. do { \
  2378. if ((tx)->prio_change_cbfn) { \
  2379. void (*cbfn)(struct bnad *, struct bna_tx *); \
  2380. cbfn = (tx)->prio_change_cbfn; \
  2381. (tx)->prio_change_cbfn = NULL; \
  2382. cbfn((tx)->bna->bnad, (tx)); \
  2383. } \
  2384. } while (0)
  2385. static void bna_tx_mod_cb_tx_stopped(void *tx_mod, struct bna_tx *tx);
  2386. static void bna_bfi_tx_enet_start(struct bna_tx *tx);
  2387. static void bna_tx_enet_stop(struct bna_tx *tx);
  2388. enum bna_tx_event {
  2389. TX_E_START = 1,
  2390. TX_E_STOP = 2,
  2391. TX_E_FAIL = 3,
  2392. TX_E_STARTED = 4,
  2393. TX_E_STOPPED = 5,
  2394. TX_E_PRIO_CHANGE = 6,
  2395. TX_E_CLEANUP_DONE = 7,
  2396. TX_E_BW_UPDATE = 8,
  2397. };
  2398. bfa_fsm_state_decl(bna_tx, stopped, struct bna_tx, enum bna_tx_event);
  2399. bfa_fsm_state_decl(bna_tx, start_wait, struct bna_tx, enum bna_tx_event);
  2400. bfa_fsm_state_decl(bna_tx, started, struct bna_tx, enum bna_tx_event);
  2401. bfa_fsm_state_decl(bna_tx, stop_wait, struct bna_tx, enum bna_tx_event);
  2402. bfa_fsm_state_decl(bna_tx, cleanup_wait, struct bna_tx,
  2403. enum bna_tx_event);
  2404. bfa_fsm_state_decl(bna_tx, prio_stop_wait, struct bna_tx,
  2405. enum bna_tx_event);
  2406. bfa_fsm_state_decl(bna_tx, prio_cleanup_wait, struct bna_tx,
  2407. enum bna_tx_event);
  2408. bfa_fsm_state_decl(bna_tx, failed, struct bna_tx, enum bna_tx_event);
  2409. bfa_fsm_state_decl(bna_tx, quiesce_wait, struct bna_tx,
  2410. enum bna_tx_event);
  2411. static void
  2412. bna_tx_sm_stopped_entry(struct bna_tx *tx)
  2413. {
  2414. call_tx_stop_cbfn(tx);
  2415. }
  2416. static void
  2417. bna_tx_sm_stopped(struct bna_tx *tx, enum bna_tx_event event)
  2418. {
  2419. switch (event) {
  2420. case TX_E_START:
  2421. bfa_fsm_set_state(tx, bna_tx_sm_start_wait);
  2422. break;
  2423. case TX_E_STOP:
  2424. call_tx_stop_cbfn(tx);
  2425. break;
  2426. case TX_E_FAIL:
  2427. /* No-op */
  2428. break;
  2429. case TX_E_PRIO_CHANGE:
  2430. call_tx_prio_change_cbfn(tx);
  2431. break;
  2432. case TX_E_BW_UPDATE:
  2433. /* No-op */
  2434. break;
  2435. default:
  2436. bfa_sm_fault(event);
  2437. }
  2438. }
  2439. static void
  2440. bna_tx_sm_start_wait_entry(struct bna_tx *tx)
  2441. {
  2442. bna_bfi_tx_enet_start(tx);
  2443. }
  2444. static void
  2445. bna_tx_sm_start_wait(struct bna_tx *tx, enum bna_tx_event event)
  2446. {
  2447. switch (event) {
  2448. case TX_E_STOP:
  2449. tx->flags &= ~(BNA_TX_F_PRIO_CHANGED | BNA_TX_F_BW_UPDATED);
  2450. bfa_fsm_set_state(tx, bna_tx_sm_stop_wait);
  2451. break;
  2452. case TX_E_FAIL:
  2453. tx->flags &= ~(BNA_TX_F_PRIO_CHANGED | BNA_TX_F_BW_UPDATED);
  2454. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  2455. break;
  2456. case TX_E_STARTED:
  2457. if (tx->flags & (BNA_TX_F_PRIO_CHANGED | BNA_TX_F_BW_UPDATED)) {
  2458. tx->flags &= ~(BNA_TX_F_PRIO_CHANGED |
  2459. BNA_TX_F_BW_UPDATED);
  2460. bfa_fsm_set_state(tx, bna_tx_sm_prio_stop_wait);
  2461. } else
  2462. bfa_fsm_set_state(tx, bna_tx_sm_started);
  2463. break;
  2464. case TX_E_PRIO_CHANGE:
  2465. tx->flags |= BNA_TX_F_PRIO_CHANGED;
  2466. break;
  2467. case TX_E_BW_UPDATE:
  2468. tx->flags |= BNA_TX_F_BW_UPDATED;
  2469. break;
  2470. default:
  2471. bfa_sm_fault(event);
  2472. }
  2473. }
  2474. static void
  2475. bna_tx_sm_started_entry(struct bna_tx *tx)
  2476. {
  2477. struct bna_txq *txq;
  2478. struct list_head *qe;
  2479. int is_regular = (tx->type == BNA_TX_T_REGULAR);
  2480. list_for_each(qe, &tx->txq_q) {
  2481. txq = (struct bna_txq *)qe;
  2482. txq->tcb->priority = txq->priority;
  2483. /* Start IB */
  2484. bna_ib_start(tx->bna, &txq->ib, is_regular);
  2485. }
  2486. tx->tx_resume_cbfn(tx->bna->bnad, tx);
  2487. }
  2488. static void
  2489. bna_tx_sm_started(struct bna_tx *tx, enum bna_tx_event event)
  2490. {
  2491. switch (event) {
  2492. case TX_E_STOP:
  2493. bfa_fsm_set_state(tx, bna_tx_sm_stop_wait);
  2494. tx->tx_stall_cbfn(tx->bna->bnad, tx);
  2495. bna_tx_enet_stop(tx);
  2496. break;
  2497. case TX_E_FAIL:
  2498. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2499. tx->tx_stall_cbfn(tx->bna->bnad, tx);
  2500. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2501. break;
  2502. case TX_E_PRIO_CHANGE:
  2503. case TX_E_BW_UPDATE:
  2504. bfa_fsm_set_state(tx, bna_tx_sm_prio_stop_wait);
  2505. break;
  2506. default:
  2507. bfa_sm_fault(event);
  2508. }
  2509. }
  2510. static void
  2511. bna_tx_sm_stop_wait_entry(struct bna_tx *tx)
  2512. {
  2513. }
  2514. static void
  2515. bna_tx_sm_stop_wait(struct bna_tx *tx, enum bna_tx_event event)
  2516. {
  2517. switch (event) {
  2518. case TX_E_FAIL:
  2519. case TX_E_STOPPED:
  2520. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2521. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2522. break;
  2523. case TX_E_STARTED:
  2524. /**
  2525. * We are here due to start_wait -> stop_wait transition on
  2526. * TX_E_STOP event
  2527. */
  2528. bna_tx_enet_stop(tx);
  2529. break;
  2530. case TX_E_PRIO_CHANGE:
  2531. case TX_E_BW_UPDATE:
  2532. /* No-op */
  2533. break;
  2534. default:
  2535. bfa_sm_fault(event);
  2536. }
  2537. }
  2538. static void
  2539. bna_tx_sm_cleanup_wait_entry(struct bna_tx *tx)
  2540. {
  2541. }
  2542. static void
  2543. bna_tx_sm_cleanup_wait(struct bna_tx *tx, enum bna_tx_event event)
  2544. {
  2545. switch (event) {
  2546. case TX_E_FAIL:
  2547. case TX_E_PRIO_CHANGE:
  2548. case TX_E_BW_UPDATE:
  2549. /* No-op */
  2550. break;
  2551. case TX_E_CLEANUP_DONE:
  2552. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  2553. break;
  2554. default:
  2555. bfa_sm_fault(event);
  2556. }
  2557. }
  2558. static void
  2559. bna_tx_sm_prio_stop_wait_entry(struct bna_tx *tx)
  2560. {
  2561. tx->tx_stall_cbfn(tx->bna->bnad, tx);
  2562. bna_tx_enet_stop(tx);
  2563. }
  2564. static void
  2565. bna_tx_sm_prio_stop_wait(struct bna_tx *tx, enum bna_tx_event event)
  2566. {
  2567. switch (event) {
  2568. case TX_E_STOP:
  2569. bfa_fsm_set_state(tx, bna_tx_sm_stop_wait);
  2570. break;
  2571. case TX_E_FAIL:
  2572. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2573. call_tx_prio_change_cbfn(tx);
  2574. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2575. break;
  2576. case TX_E_STOPPED:
  2577. bfa_fsm_set_state(tx, bna_tx_sm_prio_cleanup_wait);
  2578. break;
  2579. case TX_E_PRIO_CHANGE:
  2580. case TX_E_BW_UPDATE:
  2581. /* No-op */
  2582. break;
  2583. default:
  2584. bfa_sm_fault(event);
  2585. }
  2586. }
  2587. static void
  2588. bna_tx_sm_prio_cleanup_wait_entry(struct bna_tx *tx)
  2589. {
  2590. call_tx_prio_change_cbfn(tx);
  2591. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2592. }
  2593. static void
  2594. bna_tx_sm_prio_cleanup_wait(struct bna_tx *tx, enum bna_tx_event event)
  2595. {
  2596. switch (event) {
  2597. case TX_E_STOP:
  2598. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2599. break;
  2600. case TX_E_FAIL:
  2601. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2602. break;
  2603. case TX_E_PRIO_CHANGE:
  2604. case TX_E_BW_UPDATE:
  2605. /* No-op */
  2606. break;
  2607. case TX_E_CLEANUP_DONE:
  2608. bfa_fsm_set_state(tx, bna_tx_sm_start_wait);
  2609. break;
  2610. default:
  2611. bfa_sm_fault(event);
  2612. }
  2613. }
  2614. static void
  2615. bna_tx_sm_failed_entry(struct bna_tx *tx)
  2616. {
  2617. }
  2618. static void
  2619. bna_tx_sm_failed(struct bna_tx *tx, enum bna_tx_event event)
  2620. {
  2621. switch (event) {
  2622. case TX_E_START:
  2623. bfa_fsm_set_state(tx, bna_tx_sm_quiesce_wait);
  2624. break;
  2625. case TX_E_STOP:
  2626. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2627. break;
  2628. case TX_E_FAIL:
  2629. /* No-op */
  2630. break;
  2631. case TX_E_CLEANUP_DONE:
  2632. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  2633. break;
  2634. default:
  2635. bfa_sm_fault(event);
  2636. }
  2637. }
  2638. static void
  2639. bna_tx_sm_quiesce_wait_entry(struct bna_tx *tx)
  2640. {
  2641. }
  2642. static void
  2643. bna_tx_sm_quiesce_wait(struct bna_tx *tx, enum bna_tx_event event)
  2644. {
  2645. switch (event) {
  2646. case TX_E_STOP:
  2647. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2648. break;
  2649. case TX_E_FAIL:
  2650. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2651. break;
  2652. case TX_E_CLEANUP_DONE:
  2653. bfa_fsm_set_state(tx, bna_tx_sm_start_wait);
  2654. break;
  2655. case TX_E_BW_UPDATE:
  2656. /* No-op */
  2657. break;
  2658. default:
  2659. bfa_sm_fault(event);
  2660. }
  2661. }
  2662. static void
  2663. bna_bfi_tx_enet_start(struct bna_tx *tx)
  2664. {
  2665. struct bfi_enet_tx_cfg_req *cfg_req = &tx->bfi_enet_cmd.cfg_req;
  2666. struct bna_txq *txq = NULL;
  2667. struct list_head *qe;
  2668. int i;
  2669. bfi_msgq_mhdr_set(cfg_req->mh, BFI_MC_ENET,
  2670. BFI_ENET_H2I_TX_CFG_SET_REQ, 0, tx->rid);
  2671. cfg_req->mh.num_entries = htons(
  2672. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_tx_cfg_req)));
  2673. cfg_req->num_queues = tx->num_txq;
  2674. for (i = 0, qe = bfa_q_first(&tx->txq_q);
  2675. i < tx->num_txq;
  2676. i++, qe = bfa_q_next(qe)) {
  2677. txq = (struct bna_txq *)qe;
  2678. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].q.q, &txq->qpt);
  2679. cfg_req->q_cfg[i].q.priority = txq->priority;
  2680. cfg_req->q_cfg[i].ib.index_addr.a32.addr_lo =
  2681. txq->ib.ib_seg_host_addr.lsb;
  2682. cfg_req->q_cfg[i].ib.index_addr.a32.addr_hi =
  2683. txq->ib.ib_seg_host_addr.msb;
  2684. cfg_req->q_cfg[i].ib.intr.msix_index =
  2685. htons((u16)txq->ib.intr_vector);
  2686. }
  2687. cfg_req->ib_cfg.int_pkt_dma = BNA_STATUS_T_ENABLED;
  2688. cfg_req->ib_cfg.int_enabled = BNA_STATUS_T_ENABLED;
  2689. cfg_req->ib_cfg.int_pkt_enabled = BNA_STATUS_T_DISABLED;
  2690. cfg_req->ib_cfg.continuous_coalescing = BNA_STATUS_T_ENABLED;
  2691. cfg_req->ib_cfg.msix = (txq->ib.intr_type == BNA_INTR_T_MSIX)
  2692. ? BNA_STATUS_T_ENABLED : BNA_STATUS_T_DISABLED;
  2693. cfg_req->ib_cfg.coalescing_timeout =
  2694. htonl((u32)txq->ib.coalescing_timeo);
  2695. cfg_req->ib_cfg.inter_pkt_timeout =
  2696. htonl((u32)txq->ib.interpkt_timeo);
  2697. cfg_req->ib_cfg.inter_pkt_count = (u8)txq->ib.interpkt_count;
  2698. cfg_req->tx_cfg.vlan_mode = BFI_ENET_TX_VLAN_WI;
  2699. cfg_req->tx_cfg.vlan_id = htons((u16)tx->txf_vlan_id);
  2700. cfg_req->tx_cfg.admit_tagged_frame = BNA_STATUS_T_DISABLED;
  2701. cfg_req->tx_cfg.apply_vlan_filter = BNA_STATUS_T_DISABLED;
  2702. bfa_msgq_cmd_set(&tx->msgq_cmd, NULL, NULL,
  2703. sizeof(struct bfi_enet_tx_cfg_req), &cfg_req->mh);
  2704. bfa_msgq_cmd_post(&tx->bna->msgq, &tx->msgq_cmd);
  2705. }
  2706. static void
  2707. bna_bfi_tx_enet_stop(struct bna_tx *tx)
  2708. {
  2709. struct bfi_enet_req *req = &tx->bfi_enet_cmd.req;
  2710. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  2711. BFI_ENET_H2I_TX_CFG_CLR_REQ, 0, tx->rid);
  2712. req->mh.num_entries = htons(
  2713. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_req)));
  2714. bfa_msgq_cmd_set(&tx->msgq_cmd, NULL, NULL, sizeof(struct bfi_enet_req),
  2715. &req->mh);
  2716. bfa_msgq_cmd_post(&tx->bna->msgq, &tx->msgq_cmd);
  2717. }
  2718. static void
  2719. bna_tx_enet_stop(struct bna_tx *tx)
  2720. {
  2721. struct bna_txq *txq;
  2722. struct list_head *qe;
  2723. /* Stop IB */
  2724. list_for_each(qe, &tx->txq_q) {
  2725. txq = (struct bna_txq *)qe;
  2726. bna_ib_stop(tx->bna, &txq->ib);
  2727. }
  2728. bna_bfi_tx_enet_stop(tx);
  2729. }
  2730. static void
  2731. bna_txq_qpt_setup(struct bna_txq *txq, int page_count, int page_size,
  2732. struct bna_mem_descr *qpt_mem,
  2733. struct bna_mem_descr *swqpt_mem,
  2734. struct bna_mem_descr *page_mem)
  2735. {
  2736. int i;
  2737. txq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
  2738. txq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
  2739. txq->qpt.kv_qpt_ptr = qpt_mem->kva;
  2740. txq->qpt.page_count = page_count;
  2741. txq->qpt.page_size = page_size;
  2742. txq->tcb->sw_qpt = (void **) swqpt_mem->kva;
  2743. for (i = 0; i < page_count; i++) {
  2744. txq->tcb->sw_qpt[i] = page_mem[i].kva;
  2745. ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].lsb =
  2746. page_mem[i].dma.lsb;
  2747. ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].msb =
  2748. page_mem[i].dma.msb;
  2749. }
  2750. }
  2751. static struct bna_tx *
  2752. bna_tx_get(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
  2753. {
  2754. struct list_head *qe = NULL;
  2755. struct bna_tx *tx = NULL;
  2756. if (list_empty(&tx_mod->tx_free_q))
  2757. return NULL;
  2758. if (type == BNA_TX_T_REGULAR) {
  2759. bfa_q_deq(&tx_mod->tx_free_q, &qe);
  2760. } else {
  2761. bfa_q_deq_tail(&tx_mod->tx_free_q, &qe);
  2762. }
  2763. tx = (struct bna_tx *)qe;
  2764. bfa_q_qe_init(&tx->qe);
  2765. tx->type = type;
  2766. return tx;
  2767. }
  2768. static void
  2769. bna_tx_free(struct bna_tx *tx)
  2770. {
  2771. struct bna_tx_mod *tx_mod = &tx->bna->tx_mod;
  2772. struct bna_txq *txq;
  2773. struct list_head *prev_qe;
  2774. struct list_head *qe;
  2775. while (!list_empty(&tx->txq_q)) {
  2776. bfa_q_deq(&tx->txq_q, &txq);
  2777. bfa_q_qe_init(&txq->qe);
  2778. txq->tcb = NULL;
  2779. txq->tx = NULL;
  2780. list_add_tail(&txq->qe, &tx_mod->txq_free_q);
  2781. }
  2782. list_for_each(qe, &tx_mod->tx_active_q) {
  2783. if (qe == &tx->qe) {
  2784. list_del(&tx->qe);
  2785. bfa_q_qe_init(&tx->qe);
  2786. break;
  2787. }
  2788. }
  2789. tx->bna = NULL;
  2790. tx->priv = NULL;
  2791. prev_qe = NULL;
  2792. list_for_each(qe, &tx_mod->tx_free_q) {
  2793. if (((struct bna_tx *)qe)->rid < tx->rid)
  2794. prev_qe = qe;
  2795. else {
  2796. break;
  2797. }
  2798. }
  2799. if (prev_qe == NULL) {
  2800. /* This is the first entry */
  2801. bfa_q_enq_head(&tx_mod->tx_free_q, &tx->qe);
  2802. } else if (bfa_q_next(prev_qe) == &tx_mod->tx_free_q) {
  2803. /* This is the last entry */
  2804. list_add_tail(&tx->qe, &tx_mod->tx_free_q);
  2805. } else {
  2806. /* Somewhere in the middle */
  2807. bfa_q_next(&tx->qe) = bfa_q_next(prev_qe);
  2808. bfa_q_prev(&tx->qe) = prev_qe;
  2809. bfa_q_next(prev_qe) = &tx->qe;
  2810. bfa_q_prev(bfa_q_next(&tx->qe)) = &tx->qe;
  2811. }
  2812. }
  2813. static void
  2814. bna_tx_start(struct bna_tx *tx)
  2815. {
  2816. tx->flags |= BNA_TX_F_ENET_STARTED;
  2817. if (tx->flags & BNA_TX_F_ENABLED)
  2818. bfa_fsm_send_event(tx, TX_E_START);
  2819. }
  2820. static void
  2821. bna_tx_stop(struct bna_tx *tx)
  2822. {
  2823. tx->stop_cbfn = bna_tx_mod_cb_tx_stopped;
  2824. tx->stop_cbarg = &tx->bna->tx_mod;
  2825. tx->flags &= ~BNA_TX_F_ENET_STARTED;
  2826. bfa_fsm_send_event(tx, TX_E_STOP);
  2827. }
  2828. static void
  2829. bna_tx_fail(struct bna_tx *tx)
  2830. {
  2831. tx->flags &= ~BNA_TX_F_ENET_STARTED;
  2832. bfa_fsm_send_event(tx, TX_E_FAIL);
  2833. }
  2834. void
  2835. bna_bfi_tx_enet_start_rsp(struct bna_tx *tx, struct bfi_msgq_mhdr *msghdr)
  2836. {
  2837. struct bfi_enet_tx_cfg_rsp *cfg_rsp = &tx->bfi_enet_cmd.cfg_rsp;
  2838. struct bna_txq *txq = NULL;
  2839. struct list_head *qe;
  2840. int i;
  2841. bfa_msgq_rsp_copy(&tx->bna->msgq, (u8 *)cfg_rsp,
  2842. sizeof(struct bfi_enet_tx_cfg_rsp));
  2843. tx->hw_id = cfg_rsp->hw_id;
  2844. for (i = 0, qe = bfa_q_first(&tx->txq_q);
  2845. i < tx->num_txq; i++, qe = bfa_q_next(qe)) {
  2846. txq = (struct bna_txq *)qe;
  2847. /* Setup doorbells */
  2848. txq->tcb->i_dbell->doorbell_addr =
  2849. tx->bna->pcidev.pci_bar_kva
  2850. + ntohl(cfg_rsp->q_handles[i].i_dbell);
  2851. txq->tcb->q_dbell =
  2852. tx->bna->pcidev.pci_bar_kva
  2853. + ntohl(cfg_rsp->q_handles[i].q_dbell);
  2854. txq->hw_id = cfg_rsp->q_handles[i].hw_qid;
  2855. /* Initialize producer/consumer indexes */
  2856. (*txq->tcb->hw_consumer_index) = 0;
  2857. txq->tcb->producer_index = txq->tcb->consumer_index = 0;
  2858. }
  2859. bfa_fsm_send_event(tx, TX_E_STARTED);
  2860. }
  2861. void
  2862. bna_bfi_tx_enet_stop_rsp(struct bna_tx *tx, struct bfi_msgq_mhdr *msghdr)
  2863. {
  2864. bfa_fsm_send_event(tx, TX_E_STOPPED);
  2865. }
  2866. void
  2867. bna_bfi_bw_update_aen(struct bna_tx_mod *tx_mod)
  2868. {
  2869. struct bna_tx *tx;
  2870. struct list_head *qe;
  2871. list_for_each(qe, &tx_mod->tx_active_q) {
  2872. tx = (struct bna_tx *)qe;
  2873. bfa_fsm_send_event(tx, TX_E_BW_UPDATE);
  2874. }
  2875. }
  2876. void
  2877. bna_tx_res_req(int num_txq, int txq_depth, struct bna_res_info *res_info)
  2878. {
  2879. u32 q_size;
  2880. u32 page_count;
  2881. struct bna_mem_info *mem_info;
  2882. res_info[BNA_TX_RES_MEM_T_TCB].res_type = BNA_RES_T_MEM;
  2883. mem_info = &res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info;
  2884. mem_info->mem_type = BNA_MEM_T_KVA;
  2885. mem_info->len = sizeof(struct bna_tcb);
  2886. mem_info->num = num_txq;
  2887. q_size = txq_depth * BFI_TXQ_WI_SIZE;
  2888. q_size = ALIGN(q_size, PAGE_SIZE);
  2889. page_count = q_size >> PAGE_SHIFT;
  2890. res_info[BNA_TX_RES_MEM_T_QPT].res_type = BNA_RES_T_MEM;
  2891. mem_info = &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info;
  2892. mem_info->mem_type = BNA_MEM_T_DMA;
  2893. mem_info->len = page_count * sizeof(struct bna_dma_addr);
  2894. mem_info->num = num_txq;
  2895. res_info[BNA_TX_RES_MEM_T_SWQPT].res_type = BNA_RES_T_MEM;
  2896. mem_info = &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info;
  2897. mem_info->mem_type = BNA_MEM_T_KVA;
  2898. mem_info->len = page_count * sizeof(void *);
  2899. mem_info->num = num_txq;
  2900. res_info[BNA_TX_RES_MEM_T_PAGE].res_type = BNA_RES_T_MEM;
  2901. mem_info = &res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info;
  2902. mem_info->mem_type = BNA_MEM_T_DMA;
  2903. mem_info->len = PAGE_SIZE;
  2904. mem_info->num = num_txq * page_count;
  2905. res_info[BNA_TX_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
  2906. mem_info = &res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info;
  2907. mem_info->mem_type = BNA_MEM_T_DMA;
  2908. mem_info->len = BFI_IBIDX_SIZE;
  2909. mem_info->num = num_txq;
  2910. res_info[BNA_TX_RES_INTR_T_TXCMPL].res_type = BNA_RES_T_INTR;
  2911. res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.intr_type =
  2912. BNA_INTR_T_MSIX;
  2913. res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.num = num_txq;
  2914. }
  2915. struct bna_tx *
  2916. bna_tx_create(struct bna *bna, struct bnad *bnad,
  2917. struct bna_tx_config *tx_cfg,
  2918. const struct bna_tx_event_cbfn *tx_cbfn,
  2919. struct bna_res_info *res_info, void *priv)
  2920. {
  2921. struct bna_intr_info *intr_info;
  2922. struct bna_tx_mod *tx_mod = &bna->tx_mod;
  2923. struct bna_tx *tx;
  2924. struct bna_txq *txq;
  2925. struct list_head *qe;
  2926. int page_count;
  2927. int page_size;
  2928. int page_idx;
  2929. int i;
  2930. intr_info = &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
  2931. page_count = (res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info.num) /
  2932. tx_cfg->num_txq;
  2933. page_size = res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info.len;
  2934. /**
  2935. * Get resources
  2936. */
  2937. if ((intr_info->num != 1) && (intr_info->num != tx_cfg->num_txq))
  2938. return NULL;
  2939. /* Tx */
  2940. tx = bna_tx_get(tx_mod, tx_cfg->tx_type);
  2941. if (!tx)
  2942. return NULL;
  2943. tx->bna = bna;
  2944. tx->priv = priv;
  2945. /* TxQs */
  2946. INIT_LIST_HEAD(&tx->txq_q);
  2947. for (i = 0; i < tx_cfg->num_txq; i++) {
  2948. if (list_empty(&tx_mod->txq_free_q))
  2949. goto err_return;
  2950. bfa_q_deq(&tx_mod->txq_free_q, &txq);
  2951. bfa_q_qe_init(&txq->qe);
  2952. list_add_tail(&txq->qe, &tx->txq_q);
  2953. txq->tx = tx;
  2954. }
  2955. /*
  2956. * Initialize
  2957. */
  2958. /* Tx */
  2959. tx->tcb_setup_cbfn = tx_cbfn->tcb_setup_cbfn;
  2960. tx->tcb_destroy_cbfn = tx_cbfn->tcb_destroy_cbfn;
  2961. /* Following callbacks are mandatory */
  2962. tx->tx_stall_cbfn = tx_cbfn->tx_stall_cbfn;
  2963. tx->tx_resume_cbfn = tx_cbfn->tx_resume_cbfn;
  2964. tx->tx_cleanup_cbfn = tx_cbfn->tx_cleanup_cbfn;
  2965. list_add_tail(&tx->qe, &tx_mod->tx_active_q);
  2966. tx->num_txq = tx_cfg->num_txq;
  2967. tx->flags = 0;
  2968. if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_ENET_STARTED) {
  2969. switch (tx->type) {
  2970. case BNA_TX_T_REGULAR:
  2971. if (!(tx->bna->tx_mod.flags &
  2972. BNA_TX_MOD_F_ENET_LOOPBACK))
  2973. tx->flags |= BNA_TX_F_ENET_STARTED;
  2974. break;
  2975. case BNA_TX_T_LOOPBACK:
  2976. if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_ENET_LOOPBACK)
  2977. tx->flags |= BNA_TX_F_ENET_STARTED;
  2978. break;
  2979. }
  2980. }
  2981. /* TxQ */
  2982. i = 0;
  2983. page_idx = 0;
  2984. list_for_each(qe, &tx->txq_q) {
  2985. txq = (struct bna_txq *)qe;
  2986. txq->tcb = (struct bna_tcb *)
  2987. res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info.mdl[i].kva;
  2988. txq->tx_packets = 0;
  2989. txq->tx_bytes = 0;
  2990. /* IB */
  2991. txq->ib.ib_seg_host_addr.lsb =
  2992. res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.lsb;
  2993. txq->ib.ib_seg_host_addr.msb =
  2994. res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.msb;
  2995. txq->ib.ib_seg_host_addr_kva =
  2996. res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].kva;
  2997. txq->ib.intr_type = intr_info->intr_type;
  2998. txq->ib.intr_vector = (intr_info->num == 1) ?
  2999. intr_info->idl[0].vector :
  3000. intr_info->idl[i].vector;
  3001. if (intr_info->intr_type == BNA_INTR_T_INTX)
  3002. txq->ib.intr_vector = (1 << txq->ib.intr_vector);
  3003. txq->ib.coalescing_timeo = tx_cfg->coalescing_timeo;
  3004. txq->ib.interpkt_timeo = 0; /* Not used */
  3005. txq->ib.interpkt_count = BFI_TX_INTERPKT_COUNT;
  3006. /* TCB */
  3007. txq->tcb->q_depth = tx_cfg->txq_depth;
  3008. txq->tcb->unmap_q = (void *)
  3009. res_info[BNA_TX_RES_MEM_T_UNMAPQ].res_u.mem_info.mdl[i].kva;
  3010. txq->tcb->hw_consumer_index =
  3011. (u32 *)txq->ib.ib_seg_host_addr_kva;
  3012. txq->tcb->i_dbell = &txq->ib.door_bell;
  3013. txq->tcb->intr_type = txq->ib.intr_type;
  3014. txq->tcb->intr_vector = txq->ib.intr_vector;
  3015. txq->tcb->txq = txq;
  3016. txq->tcb->bnad = bnad;
  3017. txq->tcb->id = i;
  3018. /* QPT, SWQPT, Pages */
  3019. bna_txq_qpt_setup(txq, page_count, page_size,
  3020. &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info.mdl[i],
  3021. &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info.mdl[i],
  3022. &res_info[BNA_TX_RES_MEM_T_PAGE].
  3023. res_u.mem_info.mdl[page_idx]);
  3024. txq->tcb->page_idx = page_idx;
  3025. txq->tcb->page_count = page_count;
  3026. page_idx += page_count;
  3027. /* Callback to bnad for setting up TCB */
  3028. if (tx->tcb_setup_cbfn)
  3029. (tx->tcb_setup_cbfn)(bna->bnad, txq->tcb);
  3030. if (tx_cfg->num_txq == BFI_TX_MAX_PRIO)
  3031. txq->priority = txq->tcb->id;
  3032. else
  3033. txq->priority = tx_mod->default_prio;
  3034. i++;
  3035. }
  3036. tx->txf_vlan_id = 0;
  3037. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  3038. tx_mod->rid_mask |= (1 << tx->rid);
  3039. return tx;
  3040. err_return:
  3041. bna_tx_free(tx);
  3042. return NULL;
  3043. }
  3044. void
  3045. bna_tx_destroy(struct bna_tx *tx)
  3046. {
  3047. struct bna_txq *txq;
  3048. struct list_head *qe;
  3049. list_for_each(qe, &tx->txq_q) {
  3050. txq = (struct bna_txq *)qe;
  3051. if (tx->tcb_destroy_cbfn)
  3052. (tx->tcb_destroy_cbfn)(tx->bna->bnad, txq->tcb);
  3053. }
  3054. tx->bna->tx_mod.rid_mask &= ~(1 << tx->rid);
  3055. bna_tx_free(tx);
  3056. }
  3057. void
  3058. bna_tx_enable(struct bna_tx *tx)
  3059. {
  3060. if (tx->fsm != (bfa_sm_t)bna_tx_sm_stopped)
  3061. return;
  3062. tx->flags |= BNA_TX_F_ENABLED;
  3063. if (tx->flags & BNA_TX_F_ENET_STARTED)
  3064. bfa_fsm_send_event(tx, TX_E_START);
  3065. }
  3066. void
  3067. bna_tx_disable(struct bna_tx *tx, enum bna_cleanup_type type,
  3068. void (*cbfn)(void *, struct bna_tx *))
  3069. {
  3070. if (type == BNA_SOFT_CLEANUP) {
  3071. (*cbfn)(tx->bna->bnad, tx);
  3072. return;
  3073. }
  3074. tx->stop_cbfn = cbfn;
  3075. tx->stop_cbarg = tx->bna->bnad;
  3076. tx->flags &= ~BNA_TX_F_ENABLED;
  3077. bfa_fsm_send_event(tx, TX_E_STOP);
  3078. }
  3079. void
  3080. bna_tx_cleanup_complete(struct bna_tx *tx)
  3081. {
  3082. bfa_fsm_send_event(tx, TX_E_CLEANUP_DONE);
  3083. }
  3084. static void
  3085. bna_tx_mod_cb_tx_stopped(void *arg, struct bna_tx *tx)
  3086. {
  3087. struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg;
  3088. bfa_wc_down(&tx_mod->tx_stop_wc);
  3089. }
  3090. static void
  3091. bna_tx_mod_cb_tx_stopped_all(void *arg)
  3092. {
  3093. struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg;
  3094. if (tx_mod->stop_cbfn)
  3095. tx_mod->stop_cbfn(&tx_mod->bna->enet);
  3096. tx_mod->stop_cbfn = NULL;
  3097. }
  3098. void
  3099. bna_tx_mod_init(struct bna_tx_mod *tx_mod, struct bna *bna,
  3100. struct bna_res_info *res_info)
  3101. {
  3102. int i;
  3103. tx_mod->bna = bna;
  3104. tx_mod->flags = 0;
  3105. tx_mod->tx = (struct bna_tx *)
  3106. res_info[BNA_MOD_RES_MEM_T_TX_ARRAY].res_u.mem_info.mdl[0].kva;
  3107. tx_mod->txq = (struct bna_txq *)
  3108. res_info[BNA_MOD_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.mdl[0].kva;
  3109. INIT_LIST_HEAD(&tx_mod->tx_free_q);
  3110. INIT_LIST_HEAD(&tx_mod->tx_active_q);
  3111. INIT_LIST_HEAD(&tx_mod->txq_free_q);
  3112. for (i = 0; i < bna->ioceth.attr.num_txq; i++) {
  3113. tx_mod->tx[i].rid = i;
  3114. bfa_q_qe_init(&tx_mod->tx[i].qe);
  3115. list_add_tail(&tx_mod->tx[i].qe, &tx_mod->tx_free_q);
  3116. bfa_q_qe_init(&tx_mod->txq[i].qe);
  3117. list_add_tail(&tx_mod->txq[i].qe, &tx_mod->txq_free_q);
  3118. }
  3119. tx_mod->prio_map = BFI_TX_PRIO_MAP_ALL;
  3120. tx_mod->default_prio = 0;
  3121. tx_mod->iscsi_over_cee = BNA_STATUS_T_DISABLED;
  3122. tx_mod->iscsi_prio = -1;
  3123. }
  3124. void
  3125. bna_tx_mod_uninit(struct bna_tx_mod *tx_mod)
  3126. {
  3127. struct list_head *qe;
  3128. int i;
  3129. i = 0;
  3130. list_for_each(qe, &tx_mod->tx_free_q)
  3131. i++;
  3132. i = 0;
  3133. list_for_each(qe, &tx_mod->txq_free_q)
  3134. i++;
  3135. tx_mod->bna = NULL;
  3136. }
  3137. void
  3138. bna_tx_mod_start(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
  3139. {
  3140. struct bna_tx *tx;
  3141. struct list_head *qe;
  3142. tx_mod->flags |= BNA_TX_MOD_F_ENET_STARTED;
  3143. if (type == BNA_TX_T_LOOPBACK)
  3144. tx_mod->flags |= BNA_TX_MOD_F_ENET_LOOPBACK;
  3145. list_for_each(qe, &tx_mod->tx_active_q) {
  3146. tx = (struct bna_tx *)qe;
  3147. if (tx->type == type)
  3148. bna_tx_start(tx);
  3149. }
  3150. }
  3151. void
  3152. bna_tx_mod_stop(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
  3153. {
  3154. struct bna_tx *tx;
  3155. struct list_head *qe;
  3156. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_STARTED;
  3157. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_LOOPBACK;
  3158. tx_mod->stop_cbfn = bna_enet_cb_tx_stopped;
  3159. bfa_wc_init(&tx_mod->tx_stop_wc, bna_tx_mod_cb_tx_stopped_all, tx_mod);
  3160. list_for_each(qe, &tx_mod->tx_active_q) {
  3161. tx = (struct bna_tx *)qe;
  3162. if (tx->type == type) {
  3163. bfa_wc_up(&tx_mod->tx_stop_wc);
  3164. bna_tx_stop(tx);
  3165. }
  3166. }
  3167. bfa_wc_wait(&tx_mod->tx_stop_wc);
  3168. }
  3169. void
  3170. bna_tx_mod_fail(struct bna_tx_mod *tx_mod)
  3171. {
  3172. struct bna_tx *tx;
  3173. struct list_head *qe;
  3174. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_STARTED;
  3175. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_LOOPBACK;
  3176. list_for_each(qe, &tx_mod->tx_active_q) {
  3177. tx = (struct bna_tx *)qe;
  3178. bna_tx_fail(tx);
  3179. }
  3180. }
  3181. void
  3182. bna_tx_coalescing_timeo_set(struct bna_tx *tx, int coalescing_timeo)
  3183. {
  3184. struct bna_txq *txq;
  3185. struct list_head *qe;
  3186. list_for_each(qe, &tx->txq_q) {
  3187. txq = (struct bna_txq *)qe;
  3188. bna_ib_coalescing_timeo_set(&txq->ib, coalescing_timeo);
  3189. }
  3190. }