fsl_upm.c 8.5 KB

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  1. /*
  2. * Freescale UPM NAND driver.
  3. *
  4. * Copyright © 2007-2008 MontaVista Software, Inc.
  5. *
  6. * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/delay.h>
  16. #include <linux/mtd/nand.h>
  17. #include <linux/mtd/nand_ecc.h>
  18. #include <linux/mtd/partitions.h>
  19. #include <linux/mtd/mtd.h>
  20. #include <linux/of_platform.h>
  21. #include <linux/of_gpio.h>
  22. #include <linux/io.h>
  23. #include <linux/slab.h>
  24. #include <asm/fsl_lbc.h>
  25. #define FSL_UPM_WAIT_RUN_PATTERN 0x1
  26. #define FSL_UPM_WAIT_WRITE_BYTE 0x2
  27. #define FSL_UPM_WAIT_WRITE_BUFFER 0x4
  28. struct fsl_upm_nand {
  29. struct device *dev;
  30. struct mtd_info mtd;
  31. struct nand_chip chip;
  32. int last_ctrl;
  33. struct mtd_partition *parts;
  34. struct fsl_upm upm;
  35. uint8_t upm_addr_offset;
  36. uint8_t upm_cmd_offset;
  37. void __iomem *io_base;
  38. int rnb_gpio[NAND_MAX_CHIPS];
  39. uint32_t mchip_offsets[NAND_MAX_CHIPS];
  40. uint32_t mchip_count;
  41. uint32_t mchip_number;
  42. int chip_delay;
  43. uint32_t wait_flags;
  44. };
  45. static inline struct fsl_upm_nand *to_fsl_upm_nand(struct mtd_info *mtdinfo)
  46. {
  47. return container_of(mtdinfo, struct fsl_upm_nand, mtd);
  48. }
  49. static int fun_chip_ready(struct mtd_info *mtd)
  50. {
  51. struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
  52. if (gpio_get_value(fun->rnb_gpio[fun->mchip_number]))
  53. return 1;
  54. dev_vdbg(fun->dev, "busy\n");
  55. return 0;
  56. }
  57. static void fun_wait_rnb(struct fsl_upm_nand *fun)
  58. {
  59. if (fun->rnb_gpio[fun->mchip_number] >= 0) {
  60. int cnt = 1000000;
  61. while (--cnt && !fun_chip_ready(&fun->mtd))
  62. cpu_relax();
  63. if (!cnt)
  64. dev_err(fun->dev, "tired waiting for RNB\n");
  65. } else {
  66. ndelay(100);
  67. }
  68. }
  69. static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  70. {
  71. struct nand_chip *chip = mtd->priv;
  72. struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
  73. u32 mar;
  74. if (!(ctrl & fun->last_ctrl)) {
  75. fsl_upm_end_pattern(&fun->upm);
  76. if (cmd == NAND_CMD_NONE)
  77. return;
  78. fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
  79. }
  80. if (ctrl & NAND_CTRL_CHANGE) {
  81. if (ctrl & NAND_ALE)
  82. fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
  83. else if (ctrl & NAND_CLE)
  84. fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
  85. }
  86. mar = (cmd << (32 - fun->upm.width)) |
  87. fun->mchip_offsets[fun->mchip_number];
  88. fsl_upm_run_pattern(&fun->upm, chip->IO_ADDR_R, mar);
  89. if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
  90. fun_wait_rnb(fun);
  91. }
  92. static void fun_select_chip(struct mtd_info *mtd, int mchip_nr)
  93. {
  94. struct nand_chip *chip = mtd->priv;
  95. struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
  96. if (mchip_nr == -1) {
  97. chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
  98. } else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) {
  99. fun->mchip_number = mchip_nr;
  100. chip->IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
  101. chip->IO_ADDR_W = chip->IO_ADDR_R;
  102. } else {
  103. BUG();
  104. }
  105. }
  106. static uint8_t fun_read_byte(struct mtd_info *mtd)
  107. {
  108. struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
  109. return in_8(fun->chip.IO_ADDR_R);
  110. }
  111. static void fun_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  112. {
  113. struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
  114. int i;
  115. for (i = 0; i < len; i++)
  116. buf[i] = in_8(fun->chip.IO_ADDR_R);
  117. }
  118. static void fun_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  119. {
  120. struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
  121. int i;
  122. for (i = 0; i < len; i++) {
  123. out_8(fun->chip.IO_ADDR_W, buf[i]);
  124. if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
  125. fun_wait_rnb(fun);
  126. }
  127. if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
  128. fun_wait_rnb(fun);
  129. }
  130. static int __devinit fun_chip_init(struct fsl_upm_nand *fun,
  131. const struct device_node *upm_np,
  132. const struct resource *io_res)
  133. {
  134. int ret;
  135. struct device_node *flash_np;
  136. struct mtd_part_parser_data ppdata;
  137. fun->chip.IO_ADDR_R = fun->io_base;
  138. fun->chip.IO_ADDR_W = fun->io_base;
  139. fun->chip.cmd_ctrl = fun_cmd_ctrl;
  140. fun->chip.chip_delay = fun->chip_delay;
  141. fun->chip.read_byte = fun_read_byte;
  142. fun->chip.read_buf = fun_read_buf;
  143. fun->chip.write_buf = fun_write_buf;
  144. fun->chip.ecc.mode = NAND_ECC_SOFT;
  145. if (fun->mchip_count > 1)
  146. fun->chip.select_chip = fun_select_chip;
  147. if (fun->rnb_gpio[0] >= 0)
  148. fun->chip.dev_ready = fun_chip_ready;
  149. fun->mtd.priv = &fun->chip;
  150. fun->mtd.owner = THIS_MODULE;
  151. flash_np = of_get_next_child(upm_np, NULL);
  152. if (!flash_np)
  153. return -ENODEV;
  154. fun->mtd.name = kasprintf(GFP_KERNEL, "0x%llx.%s", (u64)io_res->start,
  155. flash_np->name);
  156. if (!fun->mtd.name) {
  157. ret = -ENOMEM;
  158. goto err;
  159. }
  160. ret = nand_scan(&fun->mtd, fun->mchip_count);
  161. if (ret)
  162. goto err;
  163. ppdata.of_node = flash_np;
  164. ret = mtd_device_parse_register(&fun->mtd, NULL, &ppdata, NULL, 0);
  165. err:
  166. of_node_put(flash_np);
  167. if (ret)
  168. kfree(fun->mtd.name);
  169. return ret;
  170. }
  171. static int __devinit fun_probe(struct platform_device *ofdev)
  172. {
  173. struct fsl_upm_nand *fun;
  174. struct resource io_res;
  175. const __be32 *prop;
  176. int rnb_gpio;
  177. int ret;
  178. int size;
  179. int i;
  180. fun = kzalloc(sizeof(*fun), GFP_KERNEL);
  181. if (!fun)
  182. return -ENOMEM;
  183. ret = of_address_to_resource(ofdev->dev.of_node, 0, &io_res);
  184. if (ret) {
  185. dev_err(&ofdev->dev, "can't get IO base\n");
  186. goto err1;
  187. }
  188. ret = fsl_upm_find(io_res.start, &fun->upm);
  189. if (ret) {
  190. dev_err(&ofdev->dev, "can't find UPM\n");
  191. goto err1;
  192. }
  193. prop = of_get_property(ofdev->dev.of_node, "fsl,upm-addr-offset",
  194. &size);
  195. if (!prop || size != sizeof(uint32_t)) {
  196. dev_err(&ofdev->dev, "can't get UPM address offset\n");
  197. ret = -EINVAL;
  198. goto err1;
  199. }
  200. fun->upm_addr_offset = *prop;
  201. prop = of_get_property(ofdev->dev.of_node, "fsl,upm-cmd-offset", &size);
  202. if (!prop || size != sizeof(uint32_t)) {
  203. dev_err(&ofdev->dev, "can't get UPM command offset\n");
  204. ret = -EINVAL;
  205. goto err1;
  206. }
  207. fun->upm_cmd_offset = *prop;
  208. prop = of_get_property(ofdev->dev.of_node,
  209. "fsl,upm-addr-line-cs-offsets", &size);
  210. if (prop && (size / sizeof(uint32_t)) > 0) {
  211. fun->mchip_count = size / sizeof(uint32_t);
  212. if (fun->mchip_count >= NAND_MAX_CHIPS) {
  213. dev_err(&ofdev->dev, "too much multiple chips\n");
  214. goto err1;
  215. }
  216. for (i = 0; i < fun->mchip_count; i++)
  217. fun->mchip_offsets[i] = be32_to_cpu(prop[i]);
  218. } else {
  219. fun->mchip_count = 1;
  220. }
  221. for (i = 0; i < fun->mchip_count; i++) {
  222. fun->rnb_gpio[i] = -1;
  223. rnb_gpio = of_get_gpio(ofdev->dev.of_node, i);
  224. if (rnb_gpio >= 0) {
  225. ret = gpio_request(rnb_gpio, dev_name(&ofdev->dev));
  226. if (ret) {
  227. dev_err(&ofdev->dev,
  228. "can't request RNB gpio #%d\n", i);
  229. goto err2;
  230. }
  231. gpio_direction_input(rnb_gpio);
  232. fun->rnb_gpio[i] = rnb_gpio;
  233. } else if (rnb_gpio == -EINVAL) {
  234. dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i);
  235. goto err2;
  236. }
  237. }
  238. prop = of_get_property(ofdev->dev.of_node, "chip-delay", NULL);
  239. if (prop)
  240. fun->chip_delay = be32_to_cpup(prop);
  241. else
  242. fun->chip_delay = 50;
  243. prop = of_get_property(ofdev->dev.of_node, "fsl,upm-wait-flags", &size);
  244. if (prop && size == sizeof(uint32_t))
  245. fun->wait_flags = be32_to_cpup(prop);
  246. else
  247. fun->wait_flags = FSL_UPM_WAIT_RUN_PATTERN |
  248. FSL_UPM_WAIT_WRITE_BYTE;
  249. fun->io_base = devm_ioremap_nocache(&ofdev->dev, io_res.start,
  250. resource_size(&io_res));
  251. if (!fun->io_base) {
  252. ret = -ENOMEM;
  253. goto err2;
  254. }
  255. fun->dev = &ofdev->dev;
  256. fun->last_ctrl = NAND_CLE;
  257. ret = fun_chip_init(fun, ofdev->dev.of_node, &io_res);
  258. if (ret)
  259. goto err2;
  260. dev_set_drvdata(&ofdev->dev, fun);
  261. return 0;
  262. err2:
  263. for (i = 0; i < fun->mchip_count; i++) {
  264. if (fun->rnb_gpio[i] < 0)
  265. break;
  266. gpio_free(fun->rnb_gpio[i]);
  267. }
  268. err1:
  269. kfree(fun);
  270. return ret;
  271. }
  272. static int __devexit fun_remove(struct platform_device *ofdev)
  273. {
  274. struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev);
  275. int i;
  276. nand_release(&fun->mtd);
  277. kfree(fun->mtd.name);
  278. for (i = 0; i < fun->mchip_count; i++) {
  279. if (fun->rnb_gpio[i] < 0)
  280. break;
  281. gpio_free(fun->rnb_gpio[i]);
  282. }
  283. kfree(fun);
  284. return 0;
  285. }
  286. static const struct of_device_id of_fun_match[] = {
  287. { .compatible = "fsl,upm-nand" },
  288. {},
  289. };
  290. MODULE_DEVICE_TABLE(of, of_fun_match);
  291. static struct platform_driver of_fun_driver = {
  292. .driver = {
  293. .name = "fsl,upm-nand",
  294. .owner = THIS_MODULE,
  295. .of_match_table = of_fun_match,
  296. },
  297. .probe = fun_probe,
  298. .remove = __devexit_p(fun_remove),
  299. };
  300. module_platform_driver(of_fun_driver);
  301. MODULE_LICENSE("GPL");
  302. MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
  303. MODULE_DESCRIPTION("Driver for NAND chips working through Freescale "
  304. "LocalBus User-Programmable Machine");