ti_drv2667.c 17 KB

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  1. /* Copyright (c) 2012, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/gpio.h>
  15. #include <linux/i2c.h>
  16. #include <linux/pm.h>
  17. #include <linux/err.h>
  18. #include <linux/of.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <linux/i2c/ti_drv2667.h>
  21. #include "../staging/android/timed_output.h"
  22. #ifdef CONFIG_HAS_EARLYSUSPEND
  23. #include <linux/earlysuspend.h>
  24. #define DRV2667_SUS_LEVEL 1
  25. #endif
  26. #define DRV2667_STATUS_REG 0x00
  27. #define DRV2667_CNTL1_REG 0x01
  28. #define DRV2667_CNTL2_REG 0x02
  29. #define DRV2667_WAV_SEQ3_REG 0x03
  30. #define DRV2667_FIFO_REG 0x0B
  31. #define DRV2667_PAGE_REG 0xFF
  32. #define DRV2667_STANDBY_MASK 0xBF
  33. #define DRV2667_INPUT_MUX_MASK 0x04
  34. #define DRV2667_GAIN_MASK 0xFC
  35. #define DRV2667_GAIN_SHIFT 0
  36. #define DRV2667_TIMEOUT_MASK 0xF3
  37. #define DRV2667_TIMEOUT_SHIFT 2
  38. #define DRV2667_GO_MASK 0x01
  39. #define DRV2667_FIFO_SIZE 100
  40. #define DRV2667_VIB_START_VAL 0x7F
  41. #define DRV2667_REG_PAGE_ID 0x00
  42. #define DRV2667_FIFO_CHUNK_MS 10
  43. #define DRV2667_BYTES_PER_MS 8
  44. #define DRV2667_WAV_SEQ_ID_IDX 0
  45. #define DRV2667_WAV_SEQ_REP_IDX 6
  46. #define DRV2667_WAV_SEQ_FREQ_IDX 8
  47. #define DRV2667_WAV_SEQ_FREQ_MIN 8
  48. #define DRV2667_WAV_SEQ_DUR_IDX 9
  49. #define DRV2667_MIN_IDLE_TIMEOUT_MS 5
  50. #define DRV2667_MAX_IDLE_TIMEOUT_MS 20
  51. #define DRV2667_VTG_MIN_UV 3000000
  52. #define DRV2667_VTG_MAX_UV 5500000
  53. #define DRV2667_VTG_CURR_UA 24000
  54. #define DRV2667_I2C_VTG_MIN_UV 1800000
  55. #define DRV2667_I2C_VTG_MAX_UV 1800000
  56. #define DRV2667_I2C_CURR_UA 9630
  57. /* supports 3 modes in digital - fifo, ram and wave */
  58. enum drv2667_modes {
  59. FIFO_MODE = 0,
  60. RAM_SEQ_MODE,
  61. WAV_SEQ_MODE,
  62. ANALOG_MODE,
  63. };
  64. struct drv2667_data {
  65. struct i2c_client *client;
  66. struct timed_output_dev dev;
  67. struct hrtimer timer;
  68. struct work_struct work;
  69. struct mutex lock;
  70. struct regulator *vdd;
  71. struct regulator *vdd_i2c;
  72. u32 max_runtime_ms;
  73. u32 runtime_left;
  74. u8 buf[DRV2667_FIFO_SIZE + 1];
  75. u8 cntl2_val;
  76. enum drv2667_modes mode;
  77. u32 time_chunk_ms;
  78. #ifdef CONFIG_HAS_EARLYSUSPEND
  79. struct early_suspend es;
  80. #endif
  81. };
  82. static int drv2667_read_reg(struct i2c_client *client, u32 reg)
  83. {
  84. int rc;
  85. rc = i2c_smbus_read_byte_data(client, reg);
  86. if (rc < 0)
  87. dev_err(&client->dev, "i2c reg read for 0x%x failed\n", reg);
  88. return rc;
  89. }
  90. static int drv2667_write_reg(struct i2c_client *client, u32 reg, u8 val)
  91. {
  92. int rc;
  93. rc = i2c_smbus_write_byte_data(client, reg, val);
  94. if (rc < 0)
  95. dev_err(&client->dev, "i2c reg write for 0x%xfailed\n", reg);
  96. return rc;
  97. }
  98. static void drv2667_dump_regs(struct drv2667_data *data, char *label)
  99. {
  100. dev_dbg(&data->client->dev,
  101. "%s: reg0x00 = 0x%x, reg0x01 = 0x%x reg0x02 = 0x%x", label,
  102. drv2667_read_reg(data->client, DRV2667_STATUS_REG),
  103. drv2667_read_reg(data->client, DRV2667_CNTL1_REG),
  104. drv2667_read_reg(data->client, DRV2667_CNTL2_REG));
  105. }
  106. static void drv2667_worker(struct work_struct *work)
  107. {
  108. struct drv2667_data *data;
  109. int rc = 0;
  110. u8 val;
  111. data = container_of(work, struct drv2667_data, work);
  112. if (data->mode == WAV_SEQ_MODE) {
  113. /* clear go bit */
  114. val = data->cntl2_val & ~DRV2667_GO_MASK;
  115. rc = drv2667_write_reg(data->client, DRV2667_CNTL2_REG, val);
  116. if (rc < 0) {
  117. dev_err(&data->client->dev, "i2c send msg failed\n");
  118. return;
  119. }
  120. /* restart wave if runtime is left */
  121. if (data->runtime_left) {
  122. val = data->cntl2_val | DRV2667_GO_MASK;
  123. rc = drv2667_write_reg(data->client,
  124. DRV2667_CNTL2_REG, val);
  125. }
  126. } else if (data->mode == FIFO_MODE) {
  127. /* data is played at 8khz */
  128. if (data->runtime_left < data->time_chunk_ms)
  129. val = data->runtime_left * DRV2667_BYTES_PER_MS;
  130. else
  131. val = data->time_chunk_ms * DRV2667_BYTES_PER_MS;
  132. rc = i2c_master_send(data->client, data->buf, val + 1);
  133. }
  134. if (rc < 0)
  135. dev_err(&data->client->dev, "i2c send message failed\n");
  136. }
  137. static void drv2667_enable(struct timed_output_dev *dev, int runtime)
  138. {
  139. struct drv2667_data *data = container_of(dev, struct drv2667_data, dev);
  140. unsigned long time_ms;
  141. if (runtime > data->max_runtime_ms) {
  142. dev_dbg(&data->client->dev, "Invalid runtime\n");
  143. runtime = data->max_runtime_ms;
  144. }
  145. mutex_lock(&data->lock);
  146. hrtimer_cancel(&data->timer);
  147. data->runtime_left = runtime;
  148. if (data->runtime_left < data->time_chunk_ms)
  149. time_ms = runtime * NSEC_PER_MSEC;
  150. else
  151. time_ms = data->time_chunk_ms * NSEC_PER_MSEC;
  152. hrtimer_start(&data->timer, ktime_set(0, time_ms), HRTIMER_MODE_REL);
  153. schedule_work(&data->work);
  154. mutex_unlock(&data->lock);
  155. }
  156. static int drv2667_get_time(struct timed_output_dev *dev)
  157. {
  158. struct drv2667_data *data = container_of(dev, struct drv2667_data, dev);
  159. if (hrtimer_active(&data->timer))
  160. return data->runtime_left +
  161. ktime_to_ms(hrtimer_get_remaining(&data->timer));
  162. return 0;
  163. }
  164. static enum hrtimer_restart drv2667_timer(struct hrtimer *timer)
  165. {
  166. struct drv2667_data *data;
  167. int time_ms;
  168. data = container_of(timer, struct drv2667_data, timer);
  169. if (data->runtime_left <= data->time_chunk_ms) {
  170. data->runtime_left = 0;
  171. schedule_work(&data->work);
  172. return HRTIMER_NORESTART;
  173. }
  174. data->runtime_left -= data->time_chunk_ms;
  175. if (data->runtime_left < data->time_chunk_ms)
  176. time_ms = data->runtime_left * NSEC_PER_MSEC;
  177. else
  178. time_ms = data->time_chunk_ms * NSEC_PER_MSEC;
  179. hrtimer_forward_now(&data->timer, ktime_set(0, time_ms));
  180. schedule_work(&data->work);
  181. return HRTIMER_RESTART;
  182. }
  183. static int drv2667_vreg_config(struct drv2667_data *data, bool on)
  184. {
  185. int rc = 0;
  186. if (!on)
  187. goto deconfig_vreg;
  188. data->vdd = regulator_get(&data->client->dev, "vdd");
  189. if (IS_ERR(data->vdd)) {
  190. rc = PTR_ERR(data->vdd);
  191. dev_err(&data->client->dev, "unable to request vdd\n");
  192. return rc;
  193. }
  194. if (regulator_count_voltages(data->vdd) > 0) {
  195. rc = regulator_set_voltage(data->vdd,
  196. DRV2667_VTG_MIN_UV, DRV2667_VTG_MAX_UV);
  197. if (rc < 0) {
  198. dev_err(&data->client->dev,
  199. "vdd set voltage failed(%d)\n", rc);
  200. goto put_vdd;
  201. }
  202. }
  203. data->vdd_i2c = regulator_get(&data->client->dev, "vdd-i2c");
  204. if (IS_ERR(data->vdd_i2c)) {
  205. rc = PTR_ERR(data->vdd_i2c);
  206. dev_err(&data->client->dev, "unable to request vdd for i2c\n");
  207. goto reset_vdd_volt;
  208. }
  209. if (regulator_count_voltages(data->vdd_i2c) > 0) {
  210. rc = regulator_set_voltage(data->vdd_i2c,
  211. DRV2667_I2C_VTG_MIN_UV, DRV2667_I2C_VTG_MAX_UV);
  212. if (rc < 0) {
  213. dev_err(&data->client->dev,
  214. "vdd_i2c set voltage failed(%d)\n", rc);
  215. goto put_vdd_i2c;
  216. }
  217. }
  218. return rc;
  219. deconfig_vreg:
  220. if (regulator_count_voltages(data->vdd_i2c) > 0)
  221. regulator_set_voltage(data->vdd_i2c, 0, DRV2667_I2C_VTG_MAX_UV);
  222. put_vdd_i2c:
  223. regulator_put(data->vdd_i2c);
  224. reset_vdd_volt:
  225. if (regulator_count_voltages(data->vdd) > 0)
  226. regulator_set_voltage(data->vdd, 0, DRV2667_VTG_MAX_UV);
  227. put_vdd:
  228. regulator_put(data->vdd);
  229. return rc;
  230. }
  231. static int reg_set_optimum_mode_check(struct regulator *reg, int load_uA)
  232. {
  233. return (regulator_count_voltages(reg) > 0) ?
  234. regulator_set_optimum_mode(reg, load_uA) : 0;
  235. }
  236. static int drv2667_vreg_on(struct drv2667_data *data, bool on)
  237. {
  238. int rc = 0;
  239. if (!on)
  240. goto vreg_off;
  241. rc = reg_set_optimum_mode_check(data->vdd, DRV2667_VTG_CURR_UA);
  242. if (rc < 0) {
  243. dev_err(&data->client->dev,
  244. "Regulator vdd set_opt failed rc=%d\n", rc);
  245. return rc;
  246. }
  247. rc = regulator_enable(data->vdd);
  248. if (rc < 0) {
  249. dev_err(&data->client->dev, "enable vdd failed\n");
  250. return rc;
  251. }
  252. rc = reg_set_optimum_mode_check(data->vdd_i2c, DRV2667_I2C_CURR_UA);
  253. if (rc < 0) {
  254. dev_err(&data->client->dev,
  255. "Regulator vdd_i2c set_opt failed rc=%d\n", rc);
  256. return rc;
  257. }
  258. rc = regulator_enable(data->vdd_i2c);
  259. if (rc < 0) {
  260. dev_err(&data->client->dev, "enable vdd_i2c failed\n");
  261. goto disable_vdd;
  262. }
  263. return rc;
  264. vreg_off:
  265. regulator_disable(data->vdd_i2c);
  266. disable_vdd:
  267. regulator_disable(data->vdd);
  268. return rc;
  269. }
  270. #ifdef CONFIG_PM
  271. static int drv2667_suspend(struct device *dev)
  272. {
  273. struct drv2667_data *data = dev_get_drvdata(dev);
  274. u8 val;
  275. int rc;
  276. hrtimer_cancel(&data->timer);
  277. cancel_work_sync(&data->work);
  278. /* set standby */
  279. val = data->cntl2_val | ~DRV2667_STANDBY_MASK;
  280. rc = drv2667_write_reg(data->client, DRV2667_CNTL2_REG, val);
  281. if (rc < 0)
  282. dev_err(dev, "unable to set standby\n");
  283. /* turn regulators off */
  284. drv2667_vreg_on(data, false);
  285. return 0;
  286. }
  287. static int drv2667_resume(struct device *dev)
  288. {
  289. struct drv2667_data *data = dev_get_drvdata(dev);
  290. int rc;
  291. /* turn regulators on */
  292. rc = drv2667_vreg_on(data, true);
  293. if (rc < 0) {
  294. dev_err(dev, "unable to turn regulators on\n");
  295. return rc;
  296. }
  297. /* clear standby */
  298. rc = drv2667_write_reg(data->client,
  299. DRV2667_CNTL2_REG, data->cntl2_val);
  300. if (rc < 0) {
  301. dev_err(dev, "unable to clear standby\n");
  302. goto vreg_off;
  303. }
  304. return 0;
  305. vreg_off:
  306. drv2667_vreg_on(data, false);
  307. return rc;
  308. }
  309. #ifdef CONFIG_HAS_EARLYSUSPEND
  310. static void drv2667_early_suspend(struct early_suspend *es)
  311. {
  312. struct drv2667_data *data = container_of(es, struct drv2667_data, es);
  313. drv2667_suspend(&data->client->dev);
  314. }
  315. static void drv2667_late_resume(struct early_suspend *es)
  316. {
  317. struct drv2667_data *data = container_of(es, struct drv2667_data, es);
  318. drv2667_resume(&data->client->dev);
  319. }
  320. #endif
  321. static const struct dev_pm_ops drv2667_pm_ops = {
  322. #ifndef CONFIG_HAS_EARLYSUSPEND
  323. .suspend = drv2667_suspend,
  324. .resume = drv2667_resume,
  325. #endif
  326. };
  327. #endif
  328. #ifdef CONFIG_OF
  329. static int drv2667_parse_dt(struct device *dev, struct drv2667_pdata *pdata)
  330. {
  331. struct property *prop;
  332. int rc;
  333. u32 temp;
  334. rc = of_property_read_string(dev->of_node, "ti,label", &pdata->name);
  335. /* set vibrator as default name */
  336. if (rc < 0)
  337. pdata->name = "vibrator";
  338. rc = of_property_read_u32(dev->of_node, "ti,gain", &temp);
  339. /* set gain as 0 */
  340. if (rc < 0)
  341. pdata->gain = 0;
  342. else
  343. pdata->gain = (u8) temp;
  344. rc = of_property_read_u32(dev->of_node, "ti,mode", &temp);
  345. /* set FIFO mode as default */
  346. if (rc < 0)
  347. pdata->mode = FIFO_MODE;
  348. else
  349. pdata->mode = (u8) temp;
  350. /* read wave sequence */
  351. if (pdata->mode == WAV_SEQ_MODE) {
  352. prop = of_find_property(dev->of_node, "ti,wav-seq", &temp);
  353. if (!prop) {
  354. dev_err(dev, "wav seq data not found");
  355. return -ENODEV;
  356. } else if (temp != DRV2667_WAV_SEQ_LEN) {
  357. dev_err(dev, "Invalid length of wav seq data\n");
  358. return -EINVAL;
  359. }
  360. memcpy(pdata->wav_seq, prop->value, DRV2667_WAV_SEQ_LEN);
  361. }
  362. rc = of_property_read_u32(dev->of_node, "ti,idle-timeout-ms", &temp);
  363. /* configure minimum idle timeout */
  364. if (rc < 0)
  365. pdata->idle_timeout_ms = DRV2667_MIN_IDLE_TIMEOUT_MS;
  366. else
  367. pdata->idle_timeout_ms = (u8) temp;
  368. rc = of_property_read_u32(dev->of_node, "ti,max-runtime-ms",
  369. &pdata->max_runtime_ms);
  370. /* configure one sec as default time */
  371. if (rc < 0)
  372. pdata->max_runtime_ms = MSEC_PER_SEC;
  373. return 0;
  374. }
  375. #else
  376. static int drv2667_parse_dt(struct device *dev, struct drv2667_pdata *pdata)
  377. {
  378. return -ENODEV;
  379. }
  380. #endif
  381. static int __devinit drv2667_probe(struct i2c_client *client,
  382. const struct i2c_device_id *id)
  383. {
  384. struct drv2667_data *data;
  385. struct drv2667_pdata *pdata;
  386. int rc, i;
  387. u8 val, fifo_seq_val, reg;
  388. if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
  389. dev_err(&client->dev, "i2c is not supported\n");
  390. return -EIO;
  391. }
  392. if (client->dev.of_node) {
  393. pdata = devm_kzalloc(&client->dev,
  394. sizeof(struct drv2667_pdata), GFP_KERNEL);
  395. if (!pdata) {
  396. dev_err(&client->dev, "unable to allocate pdata\n");
  397. return -ENOMEM;
  398. }
  399. /* parse DT */
  400. rc = drv2667_parse_dt(&client->dev, pdata);
  401. if (rc) {
  402. dev_err(&client->dev, "DT parsing failed\n");
  403. return rc;
  404. }
  405. } else {
  406. pdata = client->dev.platform_data;
  407. if (!pdata) {
  408. dev_err(&client->dev, "invalid pdata\n");
  409. return -EINVAL;
  410. }
  411. }
  412. data = devm_kzalloc(&client->dev, sizeof(struct drv2667_data),
  413. GFP_KERNEL);
  414. if (!data) {
  415. dev_err(&client->dev, "unable to allocate memory\n");
  416. return -ENOMEM;
  417. }
  418. i2c_set_clientdata(client, data);
  419. data->client = client;
  420. data->max_runtime_ms = pdata->max_runtime_ms;
  421. mutex_init(&data->lock);
  422. INIT_WORK(&data->work, drv2667_worker);
  423. hrtimer_init(&data->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
  424. data->timer.function = drv2667_timer;
  425. data->mode = pdata->mode;
  426. /* configure voltage regulators */
  427. rc = drv2667_vreg_config(data, true);
  428. if (rc) {
  429. dev_err(&client->dev, "unable to configure regulators\n");
  430. goto destroy_mutex;
  431. }
  432. /* turn on voltage regulators */
  433. rc = drv2667_vreg_on(data, true);
  434. if (rc) {
  435. dev_err(&client->dev, "unable to turn on regulators\n");
  436. goto deconfig_vreg;
  437. }
  438. rc = drv2667_read_reg(client, DRV2667_CNTL2_REG);
  439. if (rc < 0)
  440. goto vreg_off;
  441. /* set timeout, clear standby */
  442. val = (u8) rc;
  443. if (pdata->idle_timeout_ms < DRV2667_MIN_IDLE_TIMEOUT_MS ||
  444. pdata->idle_timeout_ms > DRV2667_MAX_IDLE_TIMEOUT_MS ||
  445. (pdata->idle_timeout_ms % DRV2667_MIN_IDLE_TIMEOUT_MS)) {
  446. dev_err(&client->dev, "Invalid idle timeout\n");
  447. goto vreg_off;
  448. }
  449. val = (val & DRV2667_TIMEOUT_MASK) |
  450. ((pdata->idle_timeout_ms / DRV2667_MIN_IDLE_TIMEOUT_MS - 1) <<
  451. DRV2667_TIMEOUT_SHIFT);
  452. val &= DRV2667_STANDBY_MASK;
  453. rc = drv2667_write_reg(client, DRV2667_CNTL2_REG, val);
  454. if (rc < 0)
  455. goto vreg_off;
  456. /* cache control2 val */
  457. data->cntl2_val = val;
  458. /* program drv2667 registers */
  459. rc = drv2667_read_reg(client, DRV2667_CNTL1_REG);
  460. if (rc < 0)
  461. goto vreg_off;
  462. /* gain and input mode */
  463. val = (u8) rc;
  464. /* remove this check after adding support for these modes */
  465. if (data->mode == ANALOG_MODE || data->mode == RAM_SEQ_MODE) {
  466. dev_err(&data->client->dev, "Mode not supported\n");
  467. goto vreg_off;
  468. } else
  469. val &= ~DRV2667_INPUT_MUX_MASK; /* set digital mode */
  470. val = (val & DRV2667_GAIN_MASK) | (pdata->gain << DRV2667_GAIN_SHIFT);
  471. rc = drv2667_write_reg(client, DRV2667_CNTL1_REG, val);
  472. if (rc < 0)
  473. goto vreg_off;
  474. if (data->mode == FIFO_MODE) {
  475. /* Load a predefined pattern for FIFO mode */
  476. data->buf[0] = DRV2667_FIFO_REG;
  477. fifo_seq_val = DRV2667_VIB_START_VAL;
  478. for (i = 1; i < DRV2667_FIFO_SIZE - 1; i++, fifo_seq_val++)
  479. data->buf[i] = fifo_seq_val;
  480. data->time_chunk_ms = DRV2667_FIFO_CHUNK_MS;
  481. } else if (data->mode == WAV_SEQ_MODE) {
  482. u8 freq, rep, dur;
  483. /* program wave sequence from pdata */
  484. /* id to wave sequence 3, set page */
  485. rc = drv2667_write_reg(client, DRV2667_WAV_SEQ3_REG,
  486. pdata->wav_seq[DRV2667_WAV_SEQ_ID_IDX]);
  487. if (rc < 0)
  488. goto vreg_off;
  489. /* set page to wave form sequence */
  490. rc = drv2667_write_reg(client, DRV2667_PAGE_REG,
  491. pdata->wav_seq[DRV2667_WAV_SEQ_ID_IDX]);
  492. if (rc < 0)
  493. goto vreg_off;
  494. /* program waveform sequence */
  495. for (reg = 0, i = 0; i < DRV2667_WAV_SEQ_LEN - 1; i++, reg++) {
  496. rc = drv2667_write_reg(client, reg,
  497. pdata->wav_seq[i+1]);
  498. if (rc < 0)
  499. goto vreg_off;
  500. }
  501. /* set page back to normal register space */
  502. rc = drv2667_write_reg(client, DRV2667_PAGE_REG,
  503. DRV2667_REG_PAGE_ID);
  504. if (rc < 0)
  505. goto vreg_off;
  506. freq = pdata->wav_seq[DRV2667_WAV_SEQ_FREQ_IDX];
  507. rep = pdata->wav_seq[DRV2667_WAV_SEQ_REP_IDX];
  508. dur = pdata->wav_seq[DRV2667_WAV_SEQ_DUR_IDX];
  509. data->time_chunk_ms = (rep * dur * MSEC_PER_SEC) /
  510. (freq * DRV2667_WAV_SEQ_FREQ_MIN);
  511. }
  512. drv2667_dump_regs(data, "new");
  513. /* register with timed output class */
  514. data->dev.name = pdata->name;
  515. data->dev.get_time = drv2667_get_time;
  516. data->dev.enable = drv2667_enable;
  517. rc = timed_output_dev_register(&data->dev);
  518. if (rc) {
  519. dev_err(&client->dev, "unable to register with timed_output\n");
  520. goto vreg_off;
  521. }
  522. #ifdef CONFIG_HAS_EARLYSUSPEND
  523. data->es.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + DRV2667_SUS_LEVEL;
  524. data->es.suspend = drv2667_early_suspend;
  525. data->es.resume = drv2667_late_resume;
  526. register_early_suspend(&data->es);
  527. #endif
  528. return 0;
  529. vreg_off:
  530. drv2667_vreg_on(data, false);
  531. deconfig_vreg:
  532. drv2667_vreg_config(data, false);
  533. destroy_mutex:
  534. mutex_destroy(&data->lock);
  535. return rc;
  536. }
  537. static int __devexit drv2667_remove(struct i2c_client *client)
  538. {
  539. struct drv2667_data *data = i2c_get_clientdata(client);
  540. #ifdef CONFIG_HAS_EARLYSUSPEND
  541. unregister_early_suspend(&data->es);
  542. #endif
  543. mutex_destroy(&data->lock);
  544. timed_output_dev_unregister(&data->dev);
  545. hrtimer_cancel(&data->timer);
  546. cancel_work_sync(&data->work);
  547. drv2667_vreg_on(data, false);
  548. drv2667_vreg_config(data, false);
  549. return 0;
  550. }
  551. static const struct i2c_device_id drv2667_id_table[] = {
  552. {"drv2667", 0},
  553. { },
  554. };
  555. MODULE_DEVICE_TABLE(i2c, drv2667_id_table);
  556. #ifdef CONFIG_OF
  557. static const struct of_device_id drv2667_of_id_table[] = {
  558. {.compatible = "ti, drv2667"},
  559. { },
  560. };
  561. #else
  562. #define drv2667_of_id_table NULL
  563. #endif
  564. static struct i2c_driver drv2667_i2c_driver = {
  565. .driver = {
  566. .name = "drv2667",
  567. .owner = THIS_MODULE,
  568. .of_match_table = drv2667_of_id_table,
  569. #ifdef CONFIG_PM
  570. .pm = &drv2667_pm_ops,
  571. #endif
  572. },
  573. .probe = drv2667_probe,
  574. .remove = __devexit_p(drv2667_remove),
  575. .id_table = drv2667_id_table,
  576. };
  577. module_i2c_driver(drv2667_i2c_driver);
  578. MODULE_LICENSE("GPL v2");
  579. MODULE_DESCRIPTION("TI DRV2667 chip driver");