nes_utils.c 32 KB

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  1. /*
  2. * Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. *
  32. */
  33. #include <linux/module.h>
  34. #include <linux/moduleparam.h>
  35. #include <linux/netdevice.h>
  36. #include <linux/etherdevice.h>
  37. #include <linux/ethtool.h>
  38. #include <linux/mii.h>
  39. #include <linux/if_vlan.h>
  40. #include <linux/slab.h>
  41. #include <linux/crc32.h>
  42. #include <linux/in.h>
  43. #include <linux/ip.h>
  44. #include <linux/tcp.h>
  45. #include <linux/init.h>
  46. #include <asm/io.h>
  47. #include <asm/irq.h>
  48. #include <asm/byteorder.h>
  49. #include "nes.h"
  50. static u16 nes_read16_eeprom(void __iomem *addr, u16 offset);
  51. u32 mh_detected;
  52. u32 mh_pauses_sent;
  53. static u32 nes_set_pau(struct nes_device *nesdev)
  54. {
  55. u32 ret = 0;
  56. u32 counter;
  57. nes_write_indexed(nesdev, NES_IDX_GPR2, NES_ENABLE_PAU);
  58. nes_write_indexed(nesdev, NES_IDX_GPR_TRIGGER, 1);
  59. for (counter = 0; counter < NES_PAU_COUNTER; counter++) {
  60. udelay(30);
  61. if (!nes_read_indexed(nesdev, NES_IDX_GPR2)) {
  62. printk(KERN_INFO PFX "PAU is supported.\n");
  63. break;
  64. }
  65. nes_write_indexed(nesdev, NES_IDX_GPR_TRIGGER, 1);
  66. }
  67. if (counter == NES_PAU_COUNTER) {
  68. printk(KERN_INFO PFX "PAU is not supported.\n");
  69. return -EPERM;
  70. }
  71. return ret;
  72. }
  73. /**
  74. * nes_read_eeprom_values -
  75. */
  76. int nes_read_eeprom_values(struct nes_device *nesdev, struct nes_adapter *nesadapter)
  77. {
  78. u32 mac_addr_low;
  79. u16 mac_addr_high;
  80. u16 eeprom_data;
  81. u16 eeprom_offset;
  82. u16 next_section_address;
  83. u16 sw_section_ver;
  84. u8 major_ver = 0;
  85. u8 minor_ver = 0;
  86. /* TODO: deal with EEPROM endian issues */
  87. if (nesadapter->firmware_eeprom_offset == 0) {
  88. /* Read the EEPROM Parameters */
  89. eeprom_data = nes_read16_eeprom(nesdev->regs, 0);
  90. nes_debug(NES_DBG_HW, "EEPROM Offset 0 = 0x%04X\n", eeprom_data);
  91. eeprom_offset = 2 + (((eeprom_data & 0x007f) << 3) <<
  92. ((eeprom_data & 0x0080) >> 7));
  93. nes_debug(NES_DBG_HW, "Firmware Offset = 0x%04X\n", eeprom_offset);
  94. nesadapter->firmware_eeprom_offset = eeprom_offset;
  95. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
  96. if (eeprom_data != 0x5746) {
  97. nes_debug(NES_DBG_HW, "Not a valid Firmware Image = 0x%04X\n", eeprom_data);
  98. return -1;
  99. }
  100. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  101. nes_debug(NES_DBG_HW, "EEPROM Offset %u = 0x%04X\n",
  102. eeprom_offset + 2, eeprom_data);
  103. eeprom_offset += ((eeprom_data & 0x00ff) << 3) << ((eeprom_data & 0x0100) >> 8);
  104. nes_debug(NES_DBG_HW, "Software Offset = 0x%04X\n", eeprom_offset);
  105. nesadapter->software_eeprom_offset = eeprom_offset;
  106. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
  107. if (eeprom_data != 0x5753) {
  108. printk("Not a valid Software Image = 0x%04X\n", eeprom_data);
  109. return -1;
  110. }
  111. sw_section_ver = nes_read16_eeprom(nesdev->regs, nesadapter->software_eeprom_offset + 6);
  112. nes_debug(NES_DBG_HW, "Software section version number = 0x%04X\n",
  113. sw_section_ver);
  114. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  115. nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
  116. eeprom_offset + 2, eeprom_data);
  117. next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
  118. ((eeprom_data & 0x0100) >> 8));
  119. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
  120. if (eeprom_data != 0x414d) {
  121. nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
  122. eeprom_data);
  123. goto no_fw_rev;
  124. }
  125. eeprom_offset = next_section_address;
  126. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  127. nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
  128. eeprom_offset + 2, eeprom_data);
  129. next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
  130. ((eeprom_data & 0x0100) >> 8));
  131. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
  132. if (eeprom_data != 0x4f52) {
  133. nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x4f52 but was 0x%04X\n",
  134. eeprom_data);
  135. goto no_fw_rev;
  136. }
  137. eeprom_offset = next_section_address;
  138. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  139. nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
  140. eeprom_offset + 2, eeprom_data);
  141. next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
  142. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
  143. if (eeprom_data != 0x5746) {
  144. nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5746 but was 0x%04X\n",
  145. eeprom_data);
  146. goto no_fw_rev;
  147. }
  148. eeprom_offset = next_section_address;
  149. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  150. nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
  151. eeprom_offset + 2, eeprom_data);
  152. next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
  153. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
  154. if (eeprom_data != 0x5753) {
  155. nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5753 but was 0x%04X\n",
  156. eeprom_data);
  157. goto no_fw_rev;
  158. }
  159. eeprom_offset = next_section_address;
  160. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  161. nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
  162. eeprom_offset + 2, eeprom_data);
  163. next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
  164. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
  165. if (eeprom_data != 0x414d) {
  166. nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
  167. eeprom_data);
  168. goto no_fw_rev;
  169. }
  170. eeprom_offset = next_section_address;
  171. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  172. nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
  173. eeprom_offset + 2, eeprom_data);
  174. next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
  175. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
  176. if (eeprom_data != 0x464e) {
  177. nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x464e but was 0x%04X\n",
  178. eeprom_data);
  179. goto no_fw_rev;
  180. }
  181. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 8);
  182. printk(PFX "Firmware version %u.%u\n", (u8)(eeprom_data>>8), (u8)eeprom_data);
  183. major_ver = (u8)(eeprom_data >> 8);
  184. minor_ver = (u8)(eeprom_data);
  185. if (nes_drv_opt & NES_DRV_OPT_DISABLE_VIRT_WQ) {
  186. nes_debug(NES_DBG_HW, "Virtual WQs have been disabled\n");
  187. } else if (((major_ver == 2) && (minor_ver > 21)) || ((major_ver > 2) && (major_ver != 255))) {
  188. nesadapter->virtwq = 1;
  189. }
  190. if (((major_ver == 3) && (minor_ver >= 16)) || (major_ver > 3))
  191. nesadapter->send_term_ok = 1;
  192. if (nes_drv_opt & NES_DRV_OPT_ENABLE_PAU) {
  193. if (!nes_set_pau(nesdev))
  194. nesadapter->allow_unaligned_fpdus = 1;
  195. }
  196. nesadapter->firmware_version = (((u32)(u8)(eeprom_data>>8)) << 16) +
  197. (u32)((u8)eeprom_data);
  198. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 10);
  199. printk(PFX "EEPROM version %u.%u\n", (u8)(eeprom_data>>8), (u8)eeprom_data);
  200. nesadapter->eeprom_version = (((u32)(u8)(eeprom_data>>8)) << 16) +
  201. (u32)((u8)eeprom_data);
  202. no_fw_rev:
  203. /* eeprom is valid */
  204. eeprom_offset = nesadapter->software_eeprom_offset;
  205. eeprom_offset += 8;
  206. nesadapter->netdev_max = (u8)nes_read16_eeprom(nesdev->regs, eeprom_offset);
  207. eeprom_offset += 2;
  208. mac_addr_high = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  209. eeprom_offset += 2;
  210. mac_addr_low = (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
  211. eeprom_offset += 2;
  212. mac_addr_low <<= 16;
  213. mac_addr_low += (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
  214. nes_debug(NES_DBG_HW, "Base MAC Address = 0x%04X%08X\n",
  215. mac_addr_high, mac_addr_low);
  216. nes_debug(NES_DBG_HW, "MAC Address count = %u\n", nesadapter->netdev_max);
  217. nesadapter->mac_addr_low = mac_addr_low;
  218. nesadapter->mac_addr_high = mac_addr_high;
  219. /* Read the Phy Type array */
  220. eeprom_offset += 10;
  221. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  222. nesadapter->phy_type[0] = (u8)(eeprom_data >> 8);
  223. nesadapter->phy_type[1] = (u8)eeprom_data;
  224. /* Read the port array */
  225. eeprom_offset += 2;
  226. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  227. nesadapter->phy_type[2] = (u8)(eeprom_data >> 8);
  228. nesadapter->phy_type[3] = (u8)eeprom_data;
  229. /* port_count is set by soft reset reg */
  230. nes_debug(NES_DBG_HW, "port_count = %u, port 0 -> %u, port 1 -> %u,"
  231. " port 2 -> %u, port 3 -> %u\n",
  232. nesadapter->port_count,
  233. nesadapter->phy_type[0], nesadapter->phy_type[1],
  234. nesadapter->phy_type[2], nesadapter->phy_type[3]);
  235. /* Read PD config array */
  236. eeprom_offset += 10;
  237. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  238. nesadapter->pd_config_size[0] = eeprom_data;
  239. eeprom_offset += 2;
  240. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  241. nesadapter->pd_config_base[0] = eeprom_data;
  242. nes_debug(NES_DBG_HW, "PD0 config, size=0x%04x, base=0x%04x\n",
  243. nesadapter->pd_config_size[0], nesadapter->pd_config_base[0]);
  244. eeprom_offset += 2;
  245. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  246. nesadapter->pd_config_size[1] = eeprom_data;
  247. eeprom_offset += 2;
  248. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  249. nesadapter->pd_config_base[1] = eeprom_data;
  250. nes_debug(NES_DBG_HW, "PD1 config, size=0x%04x, base=0x%04x\n",
  251. nesadapter->pd_config_size[1], nesadapter->pd_config_base[1]);
  252. eeprom_offset += 2;
  253. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  254. nesadapter->pd_config_size[2] = eeprom_data;
  255. eeprom_offset += 2;
  256. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  257. nesadapter->pd_config_base[2] = eeprom_data;
  258. nes_debug(NES_DBG_HW, "PD2 config, size=0x%04x, base=0x%04x\n",
  259. nesadapter->pd_config_size[2], nesadapter->pd_config_base[2]);
  260. eeprom_offset += 2;
  261. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  262. nesadapter->pd_config_size[3] = eeprom_data;
  263. eeprom_offset += 2;
  264. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  265. nesadapter->pd_config_base[3] = eeprom_data;
  266. nes_debug(NES_DBG_HW, "PD3 config, size=0x%04x, base=0x%04x\n",
  267. nesadapter->pd_config_size[3], nesadapter->pd_config_base[3]);
  268. /* Read Rx Pool Size */
  269. eeprom_offset += 22; /* 46 */
  270. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  271. eeprom_offset += 2;
  272. nesadapter->rx_pool_size = (((u32)eeprom_data) << 16) +
  273. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  274. nes_debug(NES_DBG_HW, "rx_pool_size = 0x%08X\n", nesadapter->rx_pool_size);
  275. eeprom_offset += 2;
  276. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  277. eeprom_offset += 2;
  278. nesadapter->tx_pool_size = (((u32)eeprom_data) << 16) +
  279. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  280. nes_debug(NES_DBG_HW, "tx_pool_size = 0x%08X\n", nesadapter->tx_pool_size);
  281. eeprom_offset += 2;
  282. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  283. eeprom_offset += 2;
  284. nesadapter->rx_threshold = (((u32)eeprom_data) << 16) +
  285. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  286. nes_debug(NES_DBG_HW, "rx_threshold = 0x%08X\n", nesadapter->rx_threshold);
  287. eeprom_offset += 2;
  288. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  289. eeprom_offset += 2;
  290. nesadapter->tcp_timer_core_clk_divisor = (((u32)eeprom_data) << 16) +
  291. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  292. nes_debug(NES_DBG_HW, "tcp_timer_core_clk_divisor = 0x%08X\n",
  293. nesadapter->tcp_timer_core_clk_divisor);
  294. eeprom_offset += 2;
  295. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  296. eeprom_offset += 2;
  297. nesadapter->iwarp_config = (((u32)eeprom_data) << 16) +
  298. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  299. nes_debug(NES_DBG_HW, "iwarp_config = 0x%08X\n", nesadapter->iwarp_config);
  300. eeprom_offset += 2;
  301. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  302. eeprom_offset += 2;
  303. nesadapter->cm_config = (((u32)eeprom_data) << 16) +
  304. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  305. nes_debug(NES_DBG_HW, "cm_config = 0x%08X\n", nesadapter->cm_config);
  306. eeprom_offset += 2;
  307. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  308. eeprom_offset += 2;
  309. nesadapter->sws_timer_config = (((u32)eeprom_data) << 16) +
  310. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  311. nes_debug(NES_DBG_HW, "sws_timer_config = 0x%08X\n", nesadapter->sws_timer_config);
  312. eeprom_offset += 2;
  313. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  314. eeprom_offset += 2;
  315. nesadapter->tcp_config1 = (((u32)eeprom_data) << 16) +
  316. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  317. nes_debug(NES_DBG_HW, "tcp_config1 = 0x%08X\n", nesadapter->tcp_config1);
  318. eeprom_offset += 2;
  319. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  320. eeprom_offset += 2;
  321. nesadapter->wqm_wat = (((u32)eeprom_data) << 16) +
  322. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  323. nes_debug(NES_DBG_HW, "wqm_wat = 0x%08X\n", nesadapter->wqm_wat);
  324. eeprom_offset += 2;
  325. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  326. eeprom_offset += 2;
  327. nesadapter->core_clock = (((u32)eeprom_data) << 16) +
  328. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  329. nes_debug(NES_DBG_HW, "core_clock = 0x%08X\n", nesadapter->core_clock);
  330. if ((sw_section_ver) && (nesadapter->hw_rev != NE020_REV)) {
  331. eeprom_offset += 2;
  332. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  333. nesadapter->phy_index[0] = (eeprom_data & 0xff00)>>8;
  334. nesadapter->phy_index[1] = eeprom_data & 0x00ff;
  335. eeprom_offset += 2;
  336. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  337. nesadapter->phy_index[2] = (eeprom_data & 0xff00)>>8;
  338. nesadapter->phy_index[3] = eeprom_data & 0x00ff;
  339. } else {
  340. nesadapter->phy_index[0] = 4;
  341. nesadapter->phy_index[1] = 5;
  342. nesadapter->phy_index[2] = 6;
  343. nesadapter->phy_index[3] = 7;
  344. }
  345. nes_debug(NES_DBG_HW, "Phy address map = 0 > %u, 1 > %u, 2 > %u, 3 > %u\n",
  346. nesadapter->phy_index[0],nesadapter->phy_index[1],
  347. nesadapter->phy_index[2],nesadapter->phy_index[3]);
  348. }
  349. return 0;
  350. }
  351. /**
  352. * nes_read16_eeprom
  353. */
  354. static u16 nes_read16_eeprom(void __iomem *addr, u16 offset)
  355. {
  356. writel(NES_EEPROM_READ_REQUEST + (offset >> 1),
  357. (void __iomem *)addr + NES_EEPROM_COMMAND);
  358. do {
  359. } while (readl((void __iomem *)addr + NES_EEPROM_COMMAND) &
  360. NES_EEPROM_READ_REQUEST);
  361. return readw((void __iomem *)addr + NES_EEPROM_DATA);
  362. }
  363. /**
  364. * nes_write_1G_phy_reg
  365. */
  366. void nes_write_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 data)
  367. {
  368. u32 u32temp;
  369. u32 counter;
  370. nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
  371. 0x50020000 | data | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
  372. for (counter = 0; counter < 100 ; counter++) {
  373. udelay(30);
  374. u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
  375. if (u32temp & 1) {
  376. /* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
  377. nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
  378. break;
  379. }
  380. }
  381. if (!(u32temp & 1))
  382. nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
  383. u32temp);
  384. }
  385. /**
  386. * nes_read_1G_phy_reg
  387. * This routine only issues the read, the data must be read
  388. * separately.
  389. */
  390. void nes_read_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 *data)
  391. {
  392. u32 u32temp;
  393. u32 counter;
  394. /* nes_debug(NES_DBG_PHY, "phy addr = %d, mac_index = %d\n",
  395. phy_addr, nesdev->mac_index); */
  396. nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
  397. 0x60020000 | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
  398. for (counter = 0; counter < 100 ; counter++) {
  399. udelay(30);
  400. u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
  401. if (u32temp & 1) {
  402. /* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
  403. nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
  404. break;
  405. }
  406. }
  407. if (!(u32temp & 1)) {
  408. nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
  409. u32temp);
  410. *data = 0xffff;
  411. } else {
  412. *data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
  413. }
  414. }
  415. /**
  416. * nes_write_10G_phy_reg
  417. */
  418. void nes_write_10G_phy_reg(struct nes_device *nesdev, u16 phy_addr, u8 dev_addr, u16 phy_reg,
  419. u16 data)
  420. {
  421. u32 port_addr;
  422. u32 u32temp;
  423. u32 counter;
  424. port_addr = phy_addr;
  425. /* set address */
  426. nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
  427. 0x00020000 | (u32)phy_reg | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
  428. for (counter = 0; counter < 100 ; counter++) {
  429. udelay(30);
  430. u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
  431. if (u32temp & 1) {
  432. nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
  433. break;
  434. }
  435. }
  436. if (!(u32temp & 1))
  437. nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
  438. u32temp);
  439. /* set data */
  440. nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
  441. 0x10020000 | (u32)data | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
  442. for (counter = 0; counter < 100 ; counter++) {
  443. udelay(30);
  444. u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
  445. if (u32temp & 1) {
  446. nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
  447. break;
  448. }
  449. }
  450. if (!(u32temp & 1))
  451. nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
  452. u32temp);
  453. }
  454. /**
  455. * nes_read_10G_phy_reg
  456. * This routine only issues the read, the data must be read
  457. * separately.
  458. */
  459. void nes_read_10G_phy_reg(struct nes_device *nesdev, u8 phy_addr, u8 dev_addr, u16 phy_reg)
  460. {
  461. u32 port_addr;
  462. u32 u32temp;
  463. u32 counter;
  464. port_addr = phy_addr;
  465. /* set address */
  466. nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
  467. 0x00020000 | (u32)phy_reg | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
  468. for (counter = 0; counter < 100 ; counter++) {
  469. udelay(30);
  470. u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
  471. if (u32temp & 1) {
  472. nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
  473. break;
  474. }
  475. }
  476. if (!(u32temp & 1))
  477. nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
  478. u32temp);
  479. /* issue read */
  480. nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
  481. 0x30020000 | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
  482. for (counter = 0; counter < 100 ; counter++) {
  483. udelay(30);
  484. u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
  485. if (u32temp & 1) {
  486. nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
  487. break;
  488. }
  489. }
  490. if (!(u32temp & 1))
  491. nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
  492. u32temp);
  493. }
  494. /**
  495. * nes_get_cqp_request
  496. */
  497. struct nes_cqp_request *nes_get_cqp_request(struct nes_device *nesdev)
  498. {
  499. unsigned long flags;
  500. struct nes_cqp_request *cqp_request = NULL;
  501. if (!list_empty(&nesdev->cqp_avail_reqs)) {
  502. spin_lock_irqsave(&nesdev->cqp.lock, flags);
  503. if (!list_empty(&nesdev->cqp_avail_reqs)) {
  504. cqp_request = list_entry(nesdev->cqp_avail_reqs.next,
  505. struct nes_cqp_request, list);
  506. list_del_init(&cqp_request->list);
  507. }
  508. spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
  509. }
  510. if (cqp_request == NULL) {
  511. cqp_request = kzalloc(sizeof(struct nes_cqp_request), GFP_ATOMIC);
  512. if (cqp_request) {
  513. cqp_request->dynamic = 1;
  514. INIT_LIST_HEAD(&cqp_request->list);
  515. }
  516. }
  517. if (cqp_request) {
  518. init_waitqueue_head(&cqp_request->waitq);
  519. cqp_request->waiting = 0;
  520. cqp_request->request_done = 0;
  521. cqp_request->callback = 0;
  522. init_waitqueue_head(&cqp_request->waitq);
  523. nes_debug(NES_DBG_CQP, "Got cqp request %p from the available list \n",
  524. cqp_request);
  525. } else
  526. printk(KERN_ERR PFX "%s: Could not allocated a CQP request.\n",
  527. __func__);
  528. return cqp_request;
  529. }
  530. void nes_free_cqp_request(struct nes_device *nesdev,
  531. struct nes_cqp_request *cqp_request)
  532. {
  533. unsigned long flags;
  534. nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X) freed.\n",
  535. cqp_request,
  536. le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX]) & 0x3f);
  537. if (cqp_request->dynamic) {
  538. kfree(cqp_request);
  539. } else {
  540. spin_lock_irqsave(&nesdev->cqp.lock, flags);
  541. list_add_tail(&cqp_request->list, &nesdev->cqp_avail_reqs);
  542. spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
  543. }
  544. }
  545. void nes_put_cqp_request(struct nes_device *nesdev,
  546. struct nes_cqp_request *cqp_request)
  547. {
  548. if (atomic_dec_and_test(&cqp_request->refcount))
  549. nes_free_cqp_request(nesdev, cqp_request);
  550. }
  551. /**
  552. * nes_post_cqp_request
  553. */
  554. void nes_post_cqp_request(struct nes_device *nesdev,
  555. struct nes_cqp_request *cqp_request)
  556. {
  557. struct nes_hw_cqp_wqe *cqp_wqe;
  558. unsigned long flags;
  559. u32 cqp_head;
  560. u64 u64temp;
  561. u32 opcode;
  562. int ctx_index = NES_CQP_WQE_COMP_CTX_LOW_IDX;
  563. spin_lock_irqsave(&nesdev->cqp.lock, flags);
  564. if (((((nesdev->cqp.sq_tail+(nesdev->cqp.sq_size*2))-nesdev->cqp.sq_head) &
  565. (nesdev->cqp.sq_size - 1)) != 1)
  566. && (list_empty(&nesdev->cqp_pending_reqs))) {
  567. cqp_head = nesdev->cqp.sq_head++;
  568. nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
  569. cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
  570. memcpy(cqp_wqe, &cqp_request->cqp_wqe, sizeof(*cqp_wqe));
  571. opcode = le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX]);
  572. if ((opcode & NES_CQP_OPCODE_MASK) == NES_CQP_DOWNLOAD_SEGMENT)
  573. ctx_index = NES_CQP_WQE_DL_COMP_CTX_LOW_IDX;
  574. barrier();
  575. u64temp = (unsigned long)cqp_request;
  576. set_wqe_64bit_value(cqp_wqe->wqe_words, ctx_index, u64temp);
  577. nes_debug(NES_DBG_CQP, "CQP request (opcode 0x%02X), line 1 = 0x%08X put on CQPs SQ,"
  578. " request = %p, cqp_head = %u, cqp_tail = %u, cqp_size = %u,"
  579. " waiting = %d, refcount = %d.\n",
  580. opcode & NES_CQP_OPCODE_MASK,
  581. le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX]), cqp_request,
  582. nesdev->cqp.sq_head, nesdev->cqp.sq_tail, nesdev->cqp.sq_size,
  583. cqp_request->waiting, atomic_read(&cqp_request->refcount));
  584. barrier();
  585. /* Ring doorbell (1 WQEs) */
  586. nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x01800000 | nesdev->cqp.qp_id);
  587. barrier();
  588. } else {
  589. nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X), line 1 = 0x%08X"
  590. " put on the pending queue.\n",
  591. cqp_request,
  592. le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f,
  593. le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_ID_IDX]));
  594. list_add_tail(&cqp_request->list, &nesdev->cqp_pending_reqs);
  595. }
  596. spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
  597. return;
  598. }
  599. /**
  600. * nes_arp_table
  601. */
  602. int nes_arp_table(struct nes_device *nesdev, u32 ip_addr, u8 *mac_addr, u32 action)
  603. {
  604. struct nes_adapter *nesadapter = nesdev->nesadapter;
  605. int arp_index;
  606. int err = 0;
  607. __be32 tmp_addr;
  608. for (arp_index = 0; (u32) arp_index < nesadapter->arp_table_size; arp_index++) {
  609. if (nesadapter->arp_table[arp_index].ip_addr == ip_addr)
  610. break;
  611. }
  612. if (action == NES_ARP_ADD) {
  613. if (arp_index != nesadapter->arp_table_size) {
  614. return -1;
  615. }
  616. arp_index = 0;
  617. err = nes_alloc_resource(nesadapter, nesadapter->allocated_arps,
  618. nesadapter->arp_table_size, (u32 *)&arp_index, &nesadapter->next_arp_index);
  619. if (err) {
  620. nes_debug(NES_DBG_NETDEV, "nes_alloc_resource returned error = %u\n", err);
  621. return err;
  622. }
  623. nes_debug(NES_DBG_NETDEV, "ADD, arp_index=%d\n", arp_index);
  624. nesadapter->arp_table[arp_index].ip_addr = ip_addr;
  625. memcpy(nesadapter->arp_table[arp_index].mac_addr, mac_addr, ETH_ALEN);
  626. return arp_index;
  627. }
  628. /* DELETE or RESOLVE */
  629. if (arp_index == nesadapter->arp_table_size) {
  630. tmp_addr = cpu_to_be32(ip_addr);
  631. nes_debug(NES_DBG_NETDEV, "MAC for %pI4 not in ARP table - cannot %s\n",
  632. &tmp_addr, action == NES_ARP_RESOLVE ? "resolve" : "delete");
  633. return -1;
  634. }
  635. if (action == NES_ARP_RESOLVE) {
  636. nes_debug(NES_DBG_NETDEV, "RESOLVE, arp_index=%d\n", arp_index);
  637. return arp_index;
  638. }
  639. if (action == NES_ARP_DELETE) {
  640. nes_debug(NES_DBG_NETDEV, "DELETE, arp_index=%d\n", arp_index);
  641. nesadapter->arp_table[arp_index].ip_addr = 0;
  642. memset(nesadapter->arp_table[arp_index].mac_addr, 0x00, ETH_ALEN);
  643. nes_free_resource(nesadapter, nesadapter->allocated_arps, arp_index);
  644. return arp_index;
  645. }
  646. return -1;
  647. }
  648. /**
  649. * nes_mh_fix
  650. */
  651. void nes_mh_fix(unsigned long parm)
  652. {
  653. unsigned long flags;
  654. struct nes_device *nesdev = (struct nes_device *)parm;
  655. struct nes_adapter *nesadapter = nesdev->nesadapter;
  656. struct nes_vnic *nesvnic;
  657. u32 used_chunks_tx;
  658. u32 temp_used_chunks_tx;
  659. u32 temp_last_used_chunks_tx;
  660. u32 used_chunks_mask;
  661. u32 mac_tx_frames_low;
  662. u32 mac_tx_frames_high;
  663. u32 mac_tx_pauses;
  664. u32 serdes_status;
  665. u32 reset_value;
  666. u32 tx_control;
  667. u32 tx_config;
  668. u32 tx_pause_quanta;
  669. u32 rx_control;
  670. u32 rx_config;
  671. u32 mac_exact_match;
  672. u32 mpp_debug;
  673. u32 i=0;
  674. u32 chunks_tx_progress = 0;
  675. spin_lock_irqsave(&nesadapter->phy_lock, flags);
  676. if ((nesadapter->mac_sw_state[0] != NES_MAC_SW_IDLE) || (nesadapter->mac_link_down[0])) {
  677. spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
  678. goto no_mh_work;
  679. }
  680. nesadapter->mac_sw_state[0] = NES_MAC_SW_MH;
  681. spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
  682. do {
  683. mac_tx_frames_low = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_LOW);
  684. mac_tx_frames_high = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_HIGH);
  685. mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
  686. used_chunks_tx = nes_read_indexed(nesdev, NES_IDX_USED_CHUNKS_TX);
  687. nesdev->mac_pause_frames_sent += mac_tx_pauses;
  688. used_chunks_mask = 0;
  689. temp_used_chunks_tx = used_chunks_tx;
  690. temp_last_used_chunks_tx = nesdev->last_used_chunks_tx;
  691. if (nesdev->netdev[0]) {
  692. nesvnic = netdev_priv(nesdev->netdev[0]);
  693. } else {
  694. break;
  695. }
  696. for (i=0; i<4; i++) {
  697. used_chunks_mask <<= 8;
  698. if (nesvnic->qp_nic_index[i] != 0xff) {
  699. used_chunks_mask |= 0xff;
  700. if ((temp_used_chunks_tx&0xff)<(temp_last_used_chunks_tx&0xff)) {
  701. chunks_tx_progress = 1;
  702. }
  703. }
  704. temp_used_chunks_tx >>= 8;
  705. temp_last_used_chunks_tx >>= 8;
  706. }
  707. if ((mac_tx_frames_low) || (mac_tx_frames_high) ||
  708. (!(used_chunks_tx&used_chunks_mask)) ||
  709. (!(nesdev->last_used_chunks_tx&used_chunks_mask)) ||
  710. (chunks_tx_progress) ) {
  711. nesdev->last_used_chunks_tx = used_chunks_tx;
  712. break;
  713. }
  714. nesdev->last_used_chunks_tx = used_chunks_tx;
  715. barrier();
  716. nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000005);
  717. mh_pauses_sent++;
  718. mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
  719. if (mac_tx_pauses) {
  720. nesdev->mac_pause_frames_sent += mac_tx_pauses;
  721. break;
  722. }
  723. tx_control = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONTROL);
  724. tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
  725. tx_pause_quanta = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA);
  726. rx_control = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONTROL);
  727. rx_config = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONFIG);
  728. mac_exact_match = nes_read_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM);
  729. mpp_debug = nes_read_indexed(nesdev, NES_IDX_MPP_DEBUG);
  730. /* one last ditch effort to avoid a false positive */
  731. mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
  732. if (mac_tx_pauses) {
  733. nesdev->last_mac_tx_pauses = nesdev->mac_pause_frames_sent;
  734. nes_debug(NES_DBG_HW, "failsafe caught slow outbound pause\n");
  735. break;
  736. }
  737. mh_detected++;
  738. nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000000);
  739. nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, 0x00000000);
  740. reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
  741. nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value | 0x0000001d);
  742. while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
  743. & 0x00000040) != 0x00000040) && (i++ < 5000)) {
  744. /* mdelay(1); */
  745. }
  746. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008);
  747. serdes_status = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0);
  748. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x000bdef7);
  749. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE0, 0x9ce73000);
  750. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_MODE0, 0x0ff00000);
  751. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_SIGDET0, 0x00000000);
  752. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_BYPASS0, 0x00000000);
  753. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0, 0x00000000);
  754. if (nesadapter->OneG_Mode) {
  755. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0182222);
  756. } else {
  757. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0042222);
  758. }
  759. serdes_status = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_STATUS0);
  760. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000ff);
  761. nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, tx_control);
  762. nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
  763. nes_write_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA, tx_pause_quanta);
  764. nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONTROL, rx_control);
  765. nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONFIG, rx_config);
  766. nes_write_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM, mac_exact_match);
  767. nes_write_indexed(nesdev, NES_IDX_MPP_DEBUG, mpp_debug);
  768. } while (0);
  769. nesadapter->mac_sw_state[0] = NES_MAC_SW_IDLE;
  770. no_mh_work:
  771. nesdev->nesadapter->mh_timer.expires = jiffies + (HZ/5);
  772. add_timer(&nesdev->nesadapter->mh_timer);
  773. }
  774. /**
  775. * nes_clc
  776. */
  777. void nes_clc(unsigned long parm)
  778. {
  779. unsigned long flags;
  780. struct nes_device *nesdev = (struct nes_device *)parm;
  781. struct nes_adapter *nesadapter = nesdev->nesadapter;
  782. spin_lock_irqsave(&nesadapter->phy_lock, flags);
  783. nesadapter->link_interrupt_count[0] = 0;
  784. nesadapter->link_interrupt_count[1] = 0;
  785. nesadapter->link_interrupt_count[2] = 0;
  786. nesadapter->link_interrupt_count[3] = 0;
  787. spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
  788. nesadapter->lc_timer.expires = jiffies + 3600 * HZ; /* 1 hour */
  789. add_timer(&nesadapter->lc_timer);
  790. }
  791. /**
  792. * nes_dump_mem
  793. */
  794. void nes_dump_mem(unsigned int dump_debug_level, void *addr, int length)
  795. {
  796. char xlate[] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9',
  797. 'a', 'b', 'c', 'd', 'e', 'f'};
  798. char *ptr;
  799. char hex_buf[80];
  800. char ascii_buf[20];
  801. int num_char;
  802. int num_ascii;
  803. int num_hex;
  804. if (!(nes_debug_level & dump_debug_level)) {
  805. return;
  806. }
  807. ptr = addr;
  808. if (length > 0x100) {
  809. nes_debug(dump_debug_level, "Length truncated from %x to %x\n", length, 0x100);
  810. length = 0x100;
  811. }
  812. nes_debug(dump_debug_level, "Address=0x%p, length=0x%x (%d)\n", ptr, length, length);
  813. memset(ascii_buf, 0, 20);
  814. memset(hex_buf, 0, 80);
  815. num_ascii = 0;
  816. num_hex = 0;
  817. for (num_char = 0; num_char < length; num_char++) {
  818. if (num_ascii == 8) {
  819. ascii_buf[num_ascii++] = ' ';
  820. hex_buf[num_hex++] = '-';
  821. hex_buf[num_hex++] = ' ';
  822. }
  823. if (*ptr < 0x20 || *ptr > 0x7e)
  824. ascii_buf[num_ascii++] = '.';
  825. else
  826. ascii_buf[num_ascii++] = *ptr;
  827. hex_buf[num_hex++] = xlate[((*ptr & 0xf0) >> 4)];
  828. hex_buf[num_hex++] = xlate[*ptr & 0x0f];
  829. hex_buf[num_hex++] = ' ';
  830. ptr++;
  831. if (num_ascii >= 17) {
  832. /* output line and reset */
  833. nes_debug(dump_debug_level, " %s | %s\n", hex_buf, ascii_buf);
  834. memset(ascii_buf, 0, 20);
  835. memset(hex_buf, 0, 80);
  836. num_ascii = 0;
  837. num_hex = 0;
  838. }
  839. }
  840. /* output the rest */
  841. if (num_ascii) {
  842. while (num_ascii < 17) {
  843. if (num_ascii == 8) {
  844. hex_buf[num_hex++] = ' ';
  845. hex_buf[num_hex++] = ' ';
  846. }
  847. hex_buf[num_hex++] = ' ';
  848. hex_buf[num_hex++] = ' ';
  849. hex_buf[num_hex++] = ' ';
  850. num_ascii++;
  851. }
  852. nes_debug(dump_debug_level, " %s | %s\n", hex_buf, ascii_buf);
  853. }
  854. }