mthca_dev.h 19 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
  5. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  6. * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
  7. *
  8. * This software is available to you under a choice of one of two
  9. * licenses. You may choose to be licensed under the terms of the GNU
  10. * General Public License (GPL) Version 2, available from the file
  11. * COPYING in the main directory of this source tree, or the
  12. * OpenIB.org BSD license below:
  13. *
  14. * Redistribution and use in source and binary forms, with or
  15. * without modification, are permitted provided that the following
  16. * conditions are met:
  17. *
  18. * - Redistributions of source code must retain the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer.
  21. *
  22. * - Redistributions in binary form must reproduce the above
  23. * copyright notice, this list of conditions and the following
  24. * disclaimer in the documentation and/or other materials
  25. * provided with the distribution.
  26. *
  27. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  28. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  29. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  30. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  31. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  32. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  33. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  34. * SOFTWARE.
  35. */
  36. #ifndef MTHCA_DEV_H
  37. #define MTHCA_DEV_H
  38. #include <linux/spinlock.h>
  39. #include <linux/kernel.h>
  40. #include <linux/pci.h>
  41. #include <linux/dma-mapping.h>
  42. #include <linux/timer.h>
  43. #include <linux/mutex.h>
  44. #include <linux/list.h>
  45. #include <linux/semaphore.h>
  46. #include "mthca_provider.h"
  47. #include "mthca_doorbell.h"
  48. #define DRV_NAME "ib_mthca"
  49. #define PFX DRV_NAME ": "
  50. #define DRV_VERSION "1.0"
  51. #define DRV_RELDATE "April 4, 2008"
  52. enum {
  53. MTHCA_FLAG_DDR_HIDDEN = 1 << 1,
  54. MTHCA_FLAG_SRQ = 1 << 2,
  55. MTHCA_FLAG_MSI_X = 1 << 3,
  56. MTHCA_FLAG_NO_LAM = 1 << 4,
  57. MTHCA_FLAG_FMR = 1 << 5,
  58. MTHCA_FLAG_MEMFREE = 1 << 6,
  59. MTHCA_FLAG_PCIE = 1 << 7,
  60. MTHCA_FLAG_SINAI_OPT = 1 << 8
  61. };
  62. enum {
  63. MTHCA_MAX_PORTS = 2
  64. };
  65. enum {
  66. MTHCA_BOARD_ID_LEN = 64
  67. };
  68. enum {
  69. MTHCA_EQ_CONTEXT_SIZE = 0x40,
  70. MTHCA_CQ_CONTEXT_SIZE = 0x40,
  71. MTHCA_QP_CONTEXT_SIZE = 0x200,
  72. MTHCA_RDB_ENTRY_SIZE = 0x20,
  73. MTHCA_AV_SIZE = 0x20,
  74. MTHCA_MGM_ENTRY_SIZE = 0x100,
  75. /* Arbel FW gives us these, but we need them for Tavor */
  76. MTHCA_MPT_ENTRY_SIZE = 0x40,
  77. MTHCA_MTT_SEG_SIZE = 0x40,
  78. MTHCA_QP_PER_MGM = 4 * (MTHCA_MGM_ENTRY_SIZE / 16 - 2)
  79. };
  80. enum {
  81. MTHCA_EQ_CMD,
  82. MTHCA_EQ_ASYNC,
  83. MTHCA_EQ_COMP,
  84. MTHCA_NUM_EQ
  85. };
  86. enum {
  87. MTHCA_OPCODE_NOP = 0x00,
  88. MTHCA_OPCODE_RDMA_WRITE = 0x08,
  89. MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
  90. MTHCA_OPCODE_SEND = 0x0a,
  91. MTHCA_OPCODE_SEND_IMM = 0x0b,
  92. MTHCA_OPCODE_RDMA_READ = 0x10,
  93. MTHCA_OPCODE_ATOMIC_CS = 0x11,
  94. MTHCA_OPCODE_ATOMIC_FA = 0x12,
  95. MTHCA_OPCODE_BIND_MW = 0x18,
  96. MTHCA_OPCODE_INVALID = 0xff
  97. };
  98. enum {
  99. MTHCA_CMD_USE_EVENTS = 1 << 0,
  100. MTHCA_CMD_POST_DOORBELLS = 1 << 1
  101. };
  102. enum {
  103. MTHCA_CMD_NUM_DBELL_DWORDS = 8
  104. };
  105. struct mthca_cmd {
  106. struct pci_pool *pool;
  107. struct mutex hcr_mutex;
  108. struct semaphore poll_sem;
  109. struct semaphore event_sem;
  110. int max_cmds;
  111. spinlock_t context_lock;
  112. int free_head;
  113. struct mthca_cmd_context *context;
  114. u16 token_mask;
  115. u32 flags;
  116. void __iomem *dbell_map;
  117. u16 dbell_offsets[MTHCA_CMD_NUM_DBELL_DWORDS];
  118. };
  119. struct mthca_limits {
  120. int num_ports;
  121. int vl_cap;
  122. int mtu_cap;
  123. int gid_table_len;
  124. int pkey_table_len;
  125. int local_ca_ack_delay;
  126. int num_uars;
  127. int max_sg;
  128. int num_qps;
  129. int max_wqes;
  130. int max_desc_sz;
  131. int max_qp_init_rdma;
  132. int reserved_qps;
  133. int num_srqs;
  134. int max_srq_wqes;
  135. int max_srq_sge;
  136. int reserved_srqs;
  137. int num_eecs;
  138. int reserved_eecs;
  139. int num_cqs;
  140. int max_cqes;
  141. int reserved_cqs;
  142. int num_eqs;
  143. int reserved_eqs;
  144. int num_mpts;
  145. int num_mtt_segs;
  146. int mtt_seg_size;
  147. int fmr_reserved_mtts;
  148. int reserved_mtts;
  149. int reserved_mrws;
  150. int reserved_uars;
  151. int num_mgms;
  152. int num_amgms;
  153. int reserved_mcgs;
  154. int num_pds;
  155. int reserved_pds;
  156. u32 page_size_cap;
  157. u32 flags;
  158. u16 stat_rate_support;
  159. u8 port_width_cap;
  160. };
  161. struct mthca_alloc {
  162. u32 last;
  163. u32 top;
  164. u32 max;
  165. u32 mask;
  166. spinlock_t lock;
  167. unsigned long *table;
  168. };
  169. struct mthca_array {
  170. struct {
  171. void **page;
  172. int used;
  173. } *page_list;
  174. };
  175. struct mthca_uar_table {
  176. struct mthca_alloc alloc;
  177. u64 uarc_base;
  178. int uarc_size;
  179. };
  180. struct mthca_pd_table {
  181. struct mthca_alloc alloc;
  182. };
  183. struct mthca_buddy {
  184. unsigned long **bits;
  185. int *num_free;
  186. int max_order;
  187. spinlock_t lock;
  188. };
  189. struct mthca_mr_table {
  190. struct mthca_alloc mpt_alloc;
  191. struct mthca_buddy mtt_buddy;
  192. struct mthca_buddy *fmr_mtt_buddy;
  193. u64 mtt_base;
  194. u64 mpt_base;
  195. struct mthca_icm_table *mtt_table;
  196. struct mthca_icm_table *mpt_table;
  197. struct {
  198. void __iomem *mpt_base;
  199. void __iomem *mtt_base;
  200. struct mthca_buddy mtt_buddy;
  201. } tavor_fmr;
  202. };
  203. struct mthca_eq_table {
  204. struct mthca_alloc alloc;
  205. void __iomem *clr_int;
  206. u32 clr_mask;
  207. u32 arm_mask;
  208. struct mthca_eq eq[MTHCA_NUM_EQ];
  209. u64 icm_virt;
  210. struct page *icm_page;
  211. dma_addr_t icm_dma;
  212. int have_irq;
  213. u8 inta_pin;
  214. };
  215. struct mthca_cq_table {
  216. struct mthca_alloc alloc;
  217. spinlock_t lock;
  218. struct mthca_array cq;
  219. struct mthca_icm_table *table;
  220. };
  221. struct mthca_srq_table {
  222. struct mthca_alloc alloc;
  223. spinlock_t lock;
  224. struct mthca_array srq;
  225. struct mthca_icm_table *table;
  226. };
  227. struct mthca_qp_table {
  228. struct mthca_alloc alloc;
  229. u32 rdb_base;
  230. int rdb_shift;
  231. int sqp_start;
  232. spinlock_t lock;
  233. struct mthca_array qp;
  234. struct mthca_icm_table *qp_table;
  235. struct mthca_icm_table *eqp_table;
  236. struct mthca_icm_table *rdb_table;
  237. };
  238. struct mthca_av_table {
  239. struct pci_pool *pool;
  240. int num_ddr_avs;
  241. u64 ddr_av_base;
  242. void __iomem *av_map;
  243. struct mthca_alloc alloc;
  244. };
  245. struct mthca_mcg_table {
  246. struct mutex mutex;
  247. struct mthca_alloc alloc;
  248. struct mthca_icm_table *table;
  249. };
  250. struct mthca_catas_err {
  251. u64 addr;
  252. u32 __iomem *map;
  253. u32 size;
  254. struct timer_list timer;
  255. struct list_head list;
  256. };
  257. extern struct mutex mthca_device_mutex;
  258. struct mthca_dev {
  259. struct ib_device ib_dev;
  260. struct pci_dev *pdev;
  261. int hca_type;
  262. unsigned long mthca_flags;
  263. unsigned long device_cap_flags;
  264. u32 rev_id;
  265. char board_id[MTHCA_BOARD_ID_LEN];
  266. /* firmware info */
  267. u64 fw_ver;
  268. union {
  269. struct {
  270. u64 fw_start;
  271. u64 fw_end;
  272. } tavor;
  273. struct {
  274. u64 clr_int_base;
  275. u64 eq_arm_base;
  276. u64 eq_set_ci_base;
  277. struct mthca_icm *fw_icm;
  278. struct mthca_icm *aux_icm;
  279. u16 fw_pages;
  280. } arbel;
  281. } fw;
  282. u64 ddr_start;
  283. u64 ddr_end;
  284. MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)
  285. struct mutex cap_mask_mutex;
  286. void __iomem *hcr;
  287. void __iomem *kar;
  288. void __iomem *clr_base;
  289. union {
  290. struct {
  291. void __iomem *ecr_base;
  292. } tavor;
  293. struct {
  294. void __iomem *eq_arm;
  295. void __iomem *eq_set_ci_base;
  296. } arbel;
  297. } eq_regs;
  298. struct mthca_cmd cmd;
  299. struct mthca_limits limits;
  300. struct mthca_uar_table uar_table;
  301. struct mthca_pd_table pd_table;
  302. struct mthca_mr_table mr_table;
  303. struct mthca_eq_table eq_table;
  304. struct mthca_cq_table cq_table;
  305. struct mthca_srq_table srq_table;
  306. struct mthca_qp_table qp_table;
  307. struct mthca_av_table av_table;
  308. struct mthca_mcg_table mcg_table;
  309. struct mthca_catas_err catas_err;
  310. struct mthca_uar driver_uar;
  311. struct mthca_db_table *db_tab;
  312. struct mthca_pd driver_pd;
  313. struct mthca_mr driver_mr;
  314. struct ib_mad_agent *send_agent[MTHCA_MAX_PORTS][2];
  315. struct ib_ah *sm_ah[MTHCA_MAX_PORTS];
  316. spinlock_t sm_lock;
  317. u8 rate[MTHCA_MAX_PORTS];
  318. bool active;
  319. };
  320. #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
  321. extern int mthca_debug_level;
  322. #define mthca_dbg(mdev, format, arg...) \
  323. do { \
  324. if (mthca_debug_level) \
  325. dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \
  326. } while (0)
  327. #else /* CONFIG_INFINIBAND_MTHCA_DEBUG */
  328. #define mthca_dbg(mdev, format, arg...) do { (void) mdev; } while (0)
  329. #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
  330. #define mthca_err(mdev, format, arg...) \
  331. dev_err(&mdev->pdev->dev, format, ## arg)
  332. #define mthca_info(mdev, format, arg...) \
  333. dev_info(&mdev->pdev->dev, format, ## arg)
  334. #define mthca_warn(mdev, format, arg...) \
  335. dev_warn(&mdev->pdev->dev, format, ## arg)
  336. extern void __buggy_use_of_MTHCA_GET(void);
  337. extern void __buggy_use_of_MTHCA_PUT(void);
  338. #define MTHCA_GET(dest, source, offset) \
  339. do { \
  340. void *__p = (char *) (source) + (offset); \
  341. switch (sizeof (dest)) { \
  342. case 1: (dest) = *(u8 *) __p; break; \
  343. case 2: (dest) = be16_to_cpup(__p); break; \
  344. case 4: (dest) = be32_to_cpup(__p); break; \
  345. case 8: (dest) = be64_to_cpup(__p); break; \
  346. default: __buggy_use_of_MTHCA_GET(); \
  347. } \
  348. } while (0)
  349. #define MTHCA_PUT(dest, source, offset) \
  350. do { \
  351. void *__d = ((char *) (dest) + (offset)); \
  352. switch (sizeof(source)) { \
  353. case 1: *(u8 *) __d = (source); break; \
  354. case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
  355. case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
  356. case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
  357. default: __buggy_use_of_MTHCA_PUT(); \
  358. } \
  359. } while (0)
  360. int mthca_reset(struct mthca_dev *mdev);
  361. u32 mthca_alloc(struct mthca_alloc *alloc);
  362. void mthca_free(struct mthca_alloc *alloc, u32 obj);
  363. int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,
  364. u32 reserved);
  365. void mthca_alloc_cleanup(struct mthca_alloc *alloc);
  366. void *mthca_array_get(struct mthca_array *array, int index);
  367. int mthca_array_set(struct mthca_array *array, int index, void *value);
  368. void mthca_array_clear(struct mthca_array *array, int index);
  369. int mthca_array_init(struct mthca_array *array, int nent);
  370. void mthca_array_cleanup(struct mthca_array *array, int nent);
  371. int mthca_buf_alloc(struct mthca_dev *dev, int size, int max_direct,
  372. union mthca_buf *buf, int *is_direct, struct mthca_pd *pd,
  373. int hca_write, struct mthca_mr *mr);
  374. void mthca_buf_free(struct mthca_dev *dev, int size, union mthca_buf *buf,
  375. int is_direct, struct mthca_mr *mr);
  376. int mthca_init_uar_table(struct mthca_dev *dev);
  377. int mthca_init_pd_table(struct mthca_dev *dev);
  378. int mthca_init_mr_table(struct mthca_dev *dev);
  379. int mthca_init_eq_table(struct mthca_dev *dev);
  380. int mthca_init_cq_table(struct mthca_dev *dev);
  381. int mthca_init_srq_table(struct mthca_dev *dev);
  382. int mthca_init_qp_table(struct mthca_dev *dev);
  383. int mthca_init_av_table(struct mthca_dev *dev);
  384. int mthca_init_mcg_table(struct mthca_dev *dev);
  385. void mthca_cleanup_uar_table(struct mthca_dev *dev);
  386. void mthca_cleanup_pd_table(struct mthca_dev *dev);
  387. void mthca_cleanup_mr_table(struct mthca_dev *dev);
  388. void mthca_cleanup_eq_table(struct mthca_dev *dev);
  389. void mthca_cleanup_cq_table(struct mthca_dev *dev);
  390. void mthca_cleanup_srq_table(struct mthca_dev *dev);
  391. void mthca_cleanup_qp_table(struct mthca_dev *dev);
  392. void mthca_cleanup_av_table(struct mthca_dev *dev);
  393. void mthca_cleanup_mcg_table(struct mthca_dev *dev);
  394. int mthca_register_device(struct mthca_dev *dev);
  395. void mthca_unregister_device(struct mthca_dev *dev);
  396. void mthca_start_catas_poll(struct mthca_dev *dev);
  397. void mthca_stop_catas_poll(struct mthca_dev *dev);
  398. int __mthca_restart_one(struct pci_dev *pdev);
  399. int mthca_catas_init(void);
  400. void mthca_catas_cleanup(void);
  401. int mthca_uar_alloc(struct mthca_dev *dev, struct mthca_uar *uar);
  402. void mthca_uar_free(struct mthca_dev *dev, struct mthca_uar *uar);
  403. int mthca_pd_alloc(struct mthca_dev *dev, int privileged, struct mthca_pd *pd);
  404. void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd);
  405. int mthca_write_mtt_size(struct mthca_dev *dev);
  406. struct mthca_mtt *mthca_alloc_mtt(struct mthca_dev *dev, int size);
  407. void mthca_free_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt);
  408. int mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt,
  409. int start_index, u64 *buffer_list, int list_len);
  410. int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,
  411. u64 iova, u64 total_size, u32 access, struct mthca_mr *mr);
  412. int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
  413. u32 access, struct mthca_mr *mr);
  414. int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
  415. u64 *buffer_list, int buffer_size_shift,
  416. int list_len, u64 iova, u64 total_size,
  417. u32 access, struct mthca_mr *mr);
  418. void mthca_free_mr(struct mthca_dev *dev, struct mthca_mr *mr);
  419. int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
  420. u32 access, struct mthca_fmr *fmr);
  421. int mthca_tavor_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
  422. int list_len, u64 iova);
  423. void mthca_tavor_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
  424. int mthca_arbel_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
  425. int list_len, u64 iova);
  426. void mthca_arbel_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
  427. int mthca_free_fmr(struct mthca_dev *dev, struct mthca_fmr *fmr);
  428. int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);
  429. void mthca_unmap_eq_icm(struct mthca_dev *dev);
  430. int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
  431. struct ib_wc *entry);
  432. int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);
  433. int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);
  434. int mthca_init_cq(struct mthca_dev *dev, int nent,
  435. struct mthca_ucontext *ctx, u32 pdn,
  436. struct mthca_cq *cq);
  437. void mthca_free_cq(struct mthca_dev *dev,
  438. struct mthca_cq *cq);
  439. void mthca_cq_completion(struct mthca_dev *dev, u32 cqn);
  440. void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
  441. enum ib_event_type event_type);
  442. void mthca_cq_clean(struct mthca_dev *dev, struct mthca_cq *cq, u32 qpn,
  443. struct mthca_srq *srq);
  444. void mthca_cq_resize_copy_cqes(struct mthca_cq *cq);
  445. int mthca_alloc_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int nent);
  446. void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int cqe);
  447. int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd,
  448. struct ib_srq_attr *attr, struct mthca_srq *srq);
  449. void mthca_free_srq(struct mthca_dev *dev, struct mthca_srq *srq);
  450. int mthca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
  451. enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
  452. int mthca_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr);
  453. int mthca_max_srq_sge(struct mthca_dev *dev);
  454. void mthca_srq_event(struct mthca_dev *dev, u32 srqn,
  455. enum ib_event_type event_type);
  456. void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr);
  457. int mthca_tavor_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr,
  458. struct ib_recv_wr **bad_wr);
  459. int mthca_arbel_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr,
  460. struct ib_recv_wr **bad_wr);
  461. void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
  462. enum ib_event_type event_type);
  463. int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
  464. struct ib_qp_init_attr *qp_init_attr);
  465. int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
  466. struct ib_udata *udata);
  467. int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
  468. struct ib_send_wr **bad_wr);
  469. int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
  470. struct ib_recv_wr **bad_wr);
  471. int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
  472. struct ib_send_wr **bad_wr);
  473. int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
  474. struct ib_recv_wr **bad_wr);
  475. void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
  476. int index, int *dbd, __be32 *new_wqe);
  477. int mthca_alloc_qp(struct mthca_dev *dev,
  478. struct mthca_pd *pd,
  479. struct mthca_cq *send_cq,
  480. struct mthca_cq *recv_cq,
  481. enum ib_qp_type type,
  482. enum ib_sig_type send_policy,
  483. struct ib_qp_cap *cap,
  484. struct mthca_qp *qp);
  485. int mthca_alloc_sqp(struct mthca_dev *dev,
  486. struct mthca_pd *pd,
  487. struct mthca_cq *send_cq,
  488. struct mthca_cq *recv_cq,
  489. enum ib_sig_type send_policy,
  490. struct ib_qp_cap *cap,
  491. int qpn,
  492. int port,
  493. struct mthca_sqp *sqp);
  494. void mthca_free_qp(struct mthca_dev *dev, struct mthca_qp *qp);
  495. int mthca_create_ah(struct mthca_dev *dev,
  496. struct mthca_pd *pd,
  497. struct ib_ah_attr *ah_attr,
  498. struct mthca_ah *ah);
  499. int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah);
  500. int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,
  501. struct ib_ud_header *header);
  502. int mthca_ah_query(struct ib_ah *ibah, struct ib_ah_attr *attr);
  503. int mthca_ah_grh_present(struct mthca_ah *ah);
  504. u8 mthca_get_rate(struct mthca_dev *dev, int static_rate, u8 port);
  505. enum ib_rate mthca_rate_to_ib(struct mthca_dev *dev, u8 mthca_rate, u8 port);
  506. int mthca_multicast_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
  507. int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
  508. int mthca_process_mad(struct ib_device *ibdev,
  509. int mad_flags,
  510. u8 port_num,
  511. struct ib_wc *in_wc,
  512. struct ib_grh *in_grh,
  513. struct ib_mad *in_mad,
  514. struct ib_mad *out_mad);
  515. int mthca_create_agents(struct mthca_dev *dev);
  516. void mthca_free_agents(struct mthca_dev *dev);
  517. static inline struct mthca_dev *to_mdev(struct ib_device *ibdev)
  518. {
  519. return container_of(ibdev, struct mthca_dev, ib_dev);
  520. }
  521. static inline int mthca_is_memfree(struct mthca_dev *dev)
  522. {
  523. return dev->mthca_flags & MTHCA_FLAG_MEMFREE;
  524. }
  525. #endif /* MTHCA_DEV_H */