i2c-xiic.c 22 KB

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  1. /*
  2. * i2c-xiic.c
  3. * Copyright (c) 2002-2007 Xilinx Inc.
  4. * Copyright (c) 2009-2010 Intel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. *
  19. *
  20. * This code was implemented by Mocean Laboratories AB when porting linux
  21. * to the automotive development board Russellville. The copyright holder
  22. * as seen in the header is Intel corporation.
  23. * Mocean Laboratories forked off the GNU/Linux platform work into a
  24. * separate company called Pelagicore AB, which committed the code to the
  25. * kernel.
  26. */
  27. /* Supports:
  28. * Xilinx IIC
  29. */
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/init.h>
  33. #include <linux/errno.h>
  34. #include <linux/delay.h>
  35. #include <linux/platform_device.h>
  36. #include <linux/i2c.h>
  37. #include <linux/interrupt.h>
  38. #include <linux/wait.h>
  39. #include <linux/i2c-xiic.h>
  40. #include <linux/io.h>
  41. #include <linux/slab.h>
  42. #define DRIVER_NAME "xiic-i2c"
  43. enum xilinx_i2c_state {
  44. STATE_DONE,
  45. STATE_ERROR,
  46. STATE_START
  47. };
  48. /**
  49. * struct xiic_i2c - Internal representation of the XIIC I2C bus
  50. * @base: Memory base of the HW registers
  51. * @wait: Wait queue for callers
  52. * @adap: Kernel adapter representation
  53. * @tx_msg: Messages from above to be sent
  54. * @lock: Mutual exclusion
  55. * @tx_pos: Current pos in TX message
  56. * @nmsgs: Number of messages in tx_msg
  57. * @state: See STATE_
  58. * @rx_msg: Current RX message
  59. * @rx_pos: Position within current RX message
  60. */
  61. struct xiic_i2c {
  62. void __iomem *base;
  63. wait_queue_head_t wait;
  64. struct i2c_adapter adap;
  65. struct i2c_msg *tx_msg;
  66. spinlock_t lock;
  67. unsigned int tx_pos;
  68. unsigned int nmsgs;
  69. enum xilinx_i2c_state state;
  70. struct i2c_msg *rx_msg;
  71. int rx_pos;
  72. };
  73. #define XIIC_MSB_OFFSET 0
  74. #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
  75. /*
  76. * Register offsets in bytes from RegisterBase. Three is added to the
  77. * base offset to access LSB (IBM style) of the word
  78. */
  79. #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */
  80. #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */
  81. #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
  82. #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */
  83. #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */
  84. #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
  85. #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
  86. #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */
  87. #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
  88. #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */
  89. /* Control Register masks */
  90. #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
  91. #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
  92. #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
  93. #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
  94. #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
  95. #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
  96. #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
  97. /* Status Register masks */
  98. #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
  99. #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
  100. #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
  101. #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
  102. #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
  103. #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
  104. #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
  105. #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
  106. /* Interrupt Status Register masks Interrupt occurs when... */
  107. #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
  108. #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
  109. #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
  110. #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
  111. #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
  112. #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
  113. #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
  114. #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
  115. /* The following constants specify the depth of the FIFOs */
  116. #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
  117. #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
  118. /* The following constants specify groups of interrupts that are typically
  119. * enabled or disables at the same time
  120. */
  121. #define XIIC_TX_INTERRUPTS \
  122. (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
  123. #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
  124. /* The following constants are used with the following macros to specify the
  125. * operation, a read or write operation.
  126. */
  127. #define XIIC_READ_OPERATION 1
  128. #define XIIC_WRITE_OPERATION 0
  129. /*
  130. * Tx Fifo upper bit masks.
  131. */
  132. #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
  133. #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
  134. /*
  135. * The following constants define the register offsets for the Interrupt
  136. * registers. There are some holes in the memory map for reserved addresses
  137. * to allow other registers to be added and still match the memory map of the
  138. * interrupt controller registers
  139. */
  140. #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
  141. #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
  142. #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
  143. #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
  144. #define XIIC_RESET_MASK 0xAUL
  145. /*
  146. * The following constant is used for the device global interrupt enable
  147. * register, to enable all interrupts for the device, this is the only bit
  148. * in the register
  149. */
  150. #define XIIC_GINTR_ENABLE_MASK 0x80000000UL
  151. #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
  152. #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
  153. static void xiic_start_xfer(struct xiic_i2c *i2c);
  154. static void __xiic_start_xfer(struct xiic_i2c *i2c);
  155. static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
  156. {
  157. iowrite8(value, i2c->base + reg);
  158. }
  159. static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
  160. {
  161. return ioread8(i2c->base + reg);
  162. }
  163. static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
  164. {
  165. iowrite16(value, i2c->base + reg);
  166. }
  167. static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
  168. {
  169. iowrite32(value, i2c->base + reg);
  170. }
  171. static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
  172. {
  173. return ioread32(i2c->base + reg);
  174. }
  175. static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
  176. {
  177. u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
  178. xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
  179. }
  180. static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
  181. {
  182. u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
  183. xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
  184. }
  185. static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
  186. {
  187. u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
  188. xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
  189. }
  190. static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
  191. {
  192. xiic_irq_clr(i2c, mask);
  193. xiic_irq_en(i2c, mask);
  194. }
  195. static void xiic_clear_rx_fifo(struct xiic_i2c *i2c)
  196. {
  197. u8 sr;
  198. for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
  199. !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
  200. sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET))
  201. xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
  202. }
  203. static void xiic_reinit(struct xiic_i2c *i2c)
  204. {
  205. xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
  206. /* Set receive Fifo depth to maximum (zero based). */
  207. xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
  208. /* Reset Tx Fifo. */
  209. xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
  210. /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
  211. xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
  212. /* make sure RX fifo is empty */
  213. xiic_clear_rx_fifo(i2c);
  214. /* Enable interrupts */
  215. xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
  216. xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK | XIIC_INTR_ARB_LOST_MASK);
  217. }
  218. static void xiic_deinit(struct xiic_i2c *i2c)
  219. {
  220. u8 cr;
  221. xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
  222. /* Disable IIC Device. */
  223. cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
  224. xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
  225. }
  226. static void xiic_read_rx(struct xiic_i2c *i2c)
  227. {
  228. u8 bytes_in_fifo;
  229. int i;
  230. bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
  231. dev_dbg(i2c->adap.dev.parent, "%s entry, bytes in fifo: %d, msg: %d"
  232. ", SR: 0x%x, CR: 0x%x\n",
  233. __func__, bytes_in_fifo, xiic_rx_space(i2c),
  234. xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
  235. xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
  236. if (bytes_in_fifo > xiic_rx_space(i2c))
  237. bytes_in_fifo = xiic_rx_space(i2c);
  238. for (i = 0; i < bytes_in_fifo; i++)
  239. i2c->rx_msg->buf[i2c->rx_pos++] =
  240. xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
  241. xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET,
  242. (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ?
  243. IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1);
  244. }
  245. static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
  246. {
  247. /* return the actual space left in the FIFO */
  248. return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
  249. }
  250. static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
  251. {
  252. u8 fifo_space = xiic_tx_fifo_space(i2c);
  253. int len = xiic_tx_space(i2c);
  254. len = (len > fifo_space) ? fifo_space : len;
  255. dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
  256. __func__, len, fifo_space);
  257. while (len--) {
  258. u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
  259. if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {
  260. /* last message in transfer -> STOP */
  261. data |= XIIC_TX_DYN_STOP_MASK;
  262. dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
  263. }
  264. xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
  265. }
  266. }
  267. static void xiic_wakeup(struct xiic_i2c *i2c, int code)
  268. {
  269. i2c->tx_msg = NULL;
  270. i2c->rx_msg = NULL;
  271. i2c->nmsgs = 0;
  272. i2c->state = code;
  273. wake_up(&i2c->wait);
  274. }
  275. static void xiic_process(struct xiic_i2c *i2c)
  276. {
  277. u32 pend, isr, ier;
  278. u32 clr = 0;
  279. /* Get the interrupt Status from the IPIF. There is no clearing of
  280. * interrupts in the IPIF. Interrupts must be cleared at the source.
  281. * To find which interrupts are pending; AND interrupts pending with
  282. * interrupts masked.
  283. */
  284. isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
  285. ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
  286. pend = isr & ier;
  287. dev_dbg(i2c->adap.dev.parent, "%s entry, IER: 0x%x, ISR: 0x%x, "
  288. "pend: 0x%x, SR: 0x%x, msg: %p, nmsgs: %d\n",
  289. __func__, ier, isr, pend, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
  290. i2c->tx_msg, i2c->nmsgs);
  291. /* Do not processes a devices interrupts if the device has no
  292. * interrupts pending
  293. */
  294. if (!pend)
  295. return;
  296. /* Service requesting interrupt */
  297. if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
  298. ((pend & XIIC_INTR_TX_ERROR_MASK) &&
  299. !(pend & XIIC_INTR_RX_FULL_MASK))) {
  300. /* bus arbritration lost, or...
  301. * Transmit error _OR_ RX completed
  302. * if this happens when RX_FULL is not set
  303. * this is probably a TX error
  304. */
  305. dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
  306. /* dynamic mode seem to suffer from problems if we just flushes
  307. * fifos and the next message is a TX with len 0 (only addr)
  308. * reset the IP instead of just flush fifos
  309. */
  310. xiic_reinit(i2c);
  311. if (i2c->tx_msg)
  312. xiic_wakeup(i2c, STATE_ERROR);
  313. } else if (pend & XIIC_INTR_RX_FULL_MASK) {
  314. /* Receive register/FIFO is full */
  315. clr = XIIC_INTR_RX_FULL_MASK;
  316. if (!i2c->rx_msg) {
  317. dev_dbg(i2c->adap.dev.parent,
  318. "%s unexpexted RX IRQ\n", __func__);
  319. xiic_clear_rx_fifo(i2c);
  320. goto out;
  321. }
  322. xiic_read_rx(i2c);
  323. if (xiic_rx_space(i2c) == 0) {
  324. /* this is the last part of the message */
  325. i2c->rx_msg = NULL;
  326. /* also clear TX error if there (RX complete) */
  327. clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
  328. dev_dbg(i2c->adap.dev.parent,
  329. "%s end of message, nmsgs: %d\n",
  330. __func__, i2c->nmsgs);
  331. /* send next message if this wasn't the last,
  332. * otherwise the transfer will be finialise when
  333. * receiving the bus not busy interrupt
  334. */
  335. if (i2c->nmsgs > 1) {
  336. i2c->nmsgs--;
  337. i2c->tx_msg++;
  338. dev_dbg(i2c->adap.dev.parent,
  339. "%s will start next...\n", __func__);
  340. __xiic_start_xfer(i2c);
  341. }
  342. }
  343. } else if (pend & XIIC_INTR_BNB_MASK) {
  344. /* IIC bus has transitioned to not busy */
  345. clr = XIIC_INTR_BNB_MASK;
  346. /* The bus is not busy, disable BusNotBusy interrupt */
  347. xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
  348. if (!i2c->tx_msg)
  349. goto out;
  350. if ((i2c->nmsgs == 1) && !i2c->rx_msg &&
  351. xiic_tx_space(i2c) == 0)
  352. xiic_wakeup(i2c, STATE_DONE);
  353. else
  354. xiic_wakeup(i2c, STATE_ERROR);
  355. } else if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
  356. /* Transmit register/FIFO is empty or ½ empty */
  357. clr = pend &
  358. (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK);
  359. if (!i2c->tx_msg) {
  360. dev_dbg(i2c->adap.dev.parent,
  361. "%s unexpexted TX IRQ\n", __func__);
  362. goto out;
  363. }
  364. xiic_fill_tx_fifo(i2c);
  365. /* current message sent and there is space in the fifo */
  366. if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) {
  367. dev_dbg(i2c->adap.dev.parent,
  368. "%s end of message sent, nmsgs: %d\n",
  369. __func__, i2c->nmsgs);
  370. if (i2c->nmsgs > 1) {
  371. i2c->nmsgs--;
  372. i2c->tx_msg++;
  373. __xiic_start_xfer(i2c);
  374. } else {
  375. xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
  376. dev_dbg(i2c->adap.dev.parent,
  377. "%s Got TX IRQ but no more to do...\n",
  378. __func__);
  379. }
  380. } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))
  381. /* current frame is sent and is last,
  382. * make sure to disable tx half
  383. */
  384. xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
  385. } else {
  386. /* got IRQ which is not acked */
  387. dev_err(i2c->adap.dev.parent, "%s Got unexpected IRQ\n",
  388. __func__);
  389. clr = pend;
  390. }
  391. out:
  392. dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
  393. xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
  394. }
  395. static int xiic_bus_busy(struct xiic_i2c *i2c)
  396. {
  397. u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
  398. return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
  399. }
  400. static int xiic_busy(struct xiic_i2c *i2c)
  401. {
  402. int tries = 3;
  403. int err;
  404. if (i2c->tx_msg)
  405. return -EBUSY;
  406. /* for instance if previous transfer was terminated due to TX error
  407. * it might be that the bus is on it's way to become available
  408. * give it at most 3 ms to wake
  409. */
  410. err = xiic_bus_busy(i2c);
  411. while (err && tries--) {
  412. mdelay(1);
  413. err = xiic_bus_busy(i2c);
  414. }
  415. return err;
  416. }
  417. static void xiic_start_recv(struct xiic_i2c *i2c)
  418. {
  419. u8 rx_watermark;
  420. struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
  421. /* Clear and enable Rx full interrupt. */
  422. xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
  423. /* we want to get all but last byte, because the TX_ERROR IRQ is used
  424. * to inidicate error ACK on the address, and negative ack on the last
  425. * received byte, so to not mix them receive all but last.
  426. * In the case where there is only one byte to receive
  427. * we can check if ERROR and RX full is set at the same time
  428. */
  429. rx_watermark = msg->len;
  430. if (rx_watermark > IIC_RX_FIFO_DEPTH)
  431. rx_watermark = IIC_RX_FIFO_DEPTH;
  432. xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
  433. if (!(msg->flags & I2C_M_NOSTART))
  434. /* write the address */
  435. xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
  436. (msg->addr << 1) | XIIC_READ_OPERATION |
  437. XIIC_TX_DYN_START_MASK);
  438. xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
  439. xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
  440. msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
  441. if (i2c->nmsgs == 1)
  442. /* very last, enable bus not busy as well */
  443. xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
  444. /* the message is tx:ed */
  445. i2c->tx_pos = msg->len;
  446. }
  447. static void xiic_start_send(struct xiic_i2c *i2c)
  448. {
  449. struct i2c_msg *msg = i2c->tx_msg;
  450. xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK);
  451. dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d, "
  452. "ISR: 0x%x, CR: 0x%x\n",
  453. __func__, msg, msg->len, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
  454. xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
  455. if (!(msg->flags & I2C_M_NOSTART)) {
  456. /* write the address */
  457. u16 data = ((msg->addr << 1) & 0xfe) | XIIC_WRITE_OPERATION |
  458. XIIC_TX_DYN_START_MASK;
  459. if ((i2c->nmsgs == 1) && msg->len == 0)
  460. /* no data and last message -> add STOP */
  461. data |= XIIC_TX_DYN_STOP_MASK;
  462. xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
  463. }
  464. xiic_fill_tx_fifo(i2c);
  465. /* Clear any pending Tx empty, Tx Error and then enable them. */
  466. xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
  467. XIIC_INTR_BNB_MASK);
  468. }
  469. static irqreturn_t xiic_isr(int irq, void *dev_id)
  470. {
  471. struct xiic_i2c *i2c = dev_id;
  472. spin_lock(&i2c->lock);
  473. /* disable interrupts globally */
  474. xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
  475. dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);
  476. xiic_process(i2c);
  477. xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
  478. spin_unlock(&i2c->lock);
  479. return IRQ_HANDLED;
  480. }
  481. static void __xiic_start_xfer(struct xiic_i2c *i2c)
  482. {
  483. int first = 1;
  484. int fifo_space = xiic_tx_fifo_space(i2c);
  485. dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
  486. __func__, i2c->tx_msg, fifo_space);
  487. if (!i2c->tx_msg)
  488. return;
  489. i2c->rx_pos = 0;
  490. i2c->tx_pos = 0;
  491. i2c->state = STATE_START;
  492. while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) {
  493. if (!first) {
  494. i2c->nmsgs--;
  495. i2c->tx_msg++;
  496. i2c->tx_pos = 0;
  497. } else
  498. first = 0;
  499. if (i2c->tx_msg->flags & I2C_M_RD) {
  500. /* we dont date putting several reads in the FIFO */
  501. xiic_start_recv(i2c);
  502. return;
  503. } else {
  504. xiic_start_send(i2c);
  505. if (xiic_tx_space(i2c) != 0) {
  506. /* the message could not be completely sent */
  507. break;
  508. }
  509. }
  510. fifo_space = xiic_tx_fifo_space(i2c);
  511. }
  512. /* there are more messages or the current one could not be completely
  513. * put into the FIFO, also enable the half empty interrupt
  514. */
  515. if (i2c->nmsgs > 1 || xiic_tx_space(i2c))
  516. xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK);
  517. }
  518. static void xiic_start_xfer(struct xiic_i2c *i2c)
  519. {
  520. unsigned long flags;
  521. spin_lock_irqsave(&i2c->lock, flags);
  522. xiic_reinit(i2c);
  523. /* disable interrupts globally */
  524. xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
  525. spin_unlock_irqrestore(&i2c->lock, flags);
  526. __xiic_start_xfer(i2c);
  527. xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
  528. }
  529. static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
  530. {
  531. struct xiic_i2c *i2c = i2c_get_adapdata(adap);
  532. int err;
  533. dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
  534. xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
  535. err = xiic_busy(i2c);
  536. if (err)
  537. return err;
  538. i2c->tx_msg = msgs;
  539. i2c->nmsgs = num;
  540. xiic_start_xfer(i2c);
  541. if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
  542. (i2c->state == STATE_DONE), HZ))
  543. return (i2c->state == STATE_DONE) ? num : -EIO;
  544. else {
  545. i2c->tx_msg = NULL;
  546. i2c->rx_msg = NULL;
  547. i2c->nmsgs = 0;
  548. return -ETIMEDOUT;
  549. }
  550. }
  551. static u32 xiic_func(struct i2c_adapter *adap)
  552. {
  553. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  554. }
  555. static const struct i2c_algorithm xiic_algorithm = {
  556. .master_xfer = xiic_xfer,
  557. .functionality = xiic_func,
  558. };
  559. static struct i2c_adapter xiic_adapter = {
  560. .owner = THIS_MODULE,
  561. .name = DRIVER_NAME,
  562. .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
  563. .algo = &xiic_algorithm,
  564. };
  565. static int __devinit xiic_i2c_probe(struct platform_device *pdev)
  566. {
  567. struct xiic_i2c *i2c;
  568. struct xiic_i2c_platform_data *pdata;
  569. struct resource *res;
  570. int ret, irq;
  571. u8 i;
  572. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  573. if (!res)
  574. goto resource_missing;
  575. irq = platform_get_irq(pdev, 0);
  576. if (irq < 0)
  577. goto resource_missing;
  578. pdata = (struct xiic_i2c_platform_data *) pdev->dev.platform_data;
  579. if (!pdata)
  580. return -EINVAL;
  581. i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
  582. if (!i2c)
  583. return -ENOMEM;
  584. if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
  585. dev_err(&pdev->dev, "Memory region busy\n");
  586. ret = -EBUSY;
  587. goto request_mem_failed;
  588. }
  589. i2c->base = ioremap(res->start, resource_size(res));
  590. if (!i2c->base) {
  591. dev_err(&pdev->dev, "Unable to map registers\n");
  592. ret = -EIO;
  593. goto map_failed;
  594. }
  595. /* hook up driver to tree */
  596. platform_set_drvdata(pdev, i2c);
  597. i2c->adap = xiic_adapter;
  598. i2c_set_adapdata(&i2c->adap, i2c);
  599. i2c->adap.dev.parent = &pdev->dev;
  600. xiic_reinit(i2c);
  601. spin_lock_init(&i2c->lock);
  602. init_waitqueue_head(&i2c->wait);
  603. ret = request_irq(irq, xiic_isr, 0, pdev->name, i2c);
  604. if (ret) {
  605. dev_err(&pdev->dev, "Cannot claim IRQ\n");
  606. goto request_irq_failed;
  607. }
  608. /* add i2c adapter to i2c tree */
  609. ret = i2c_add_adapter(&i2c->adap);
  610. if (ret) {
  611. dev_err(&pdev->dev, "Failed to add adapter\n");
  612. goto add_adapter_failed;
  613. }
  614. /* add in known devices to the bus */
  615. for (i = 0; i < pdata->num_devices; i++)
  616. i2c_new_device(&i2c->adap, pdata->devices + i);
  617. return 0;
  618. add_adapter_failed:
  619. free_irq(irq, i2c);
  620. request_irq_failed:
  621. xiic_deinit(i2c);
  622. iounmap(i2c->base);
  623. map_failed:
  624. release_mem_region(res->start, resource_size(res));
  625. request_mem_failed:
  626. kfree(i2c);
  627. return ret;
  628. resource_missing:
  629. dev_err(&pdev->dev, "IRQ or Memory resource is missing\n");
  630. return -ENOENT;
  631. }
  632. static int __devexit xiic_i2c_remove(struct platform_device* pdev)
  633. {
  634. struct xiic_i2c *i2c = platform_get_drvdata(pdev);
  635. struct resource *res;
  636. /* remove adapter & data */
  637. i2c_del_adapter(&i2c->adap);
  638. xiic_deinit(i2c);
  639. platform_set_drvdata(pdev, NULL);
  640. free_irq(platform_get_irq(pdev, 0), i2c);
  641. iounmap(i2c->base);
  642. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  643. if (res)
  644. release_mem_region(res->start, resource_size(res));
  645. kfree(i2c);
  646. return 0;
  647. }
  648. static struct platform_driver xiic_i2c_driver = {
  649. .probe = xiic_i2c_probe,
  650. .remove = __devexit_p(xiic_i2c_remove),
  651. .driver = {
  652. .owner = THIS_MODULE,
  653. .name = DRIVER_NAME,
  654. },
  655. };
  656. module_platform_driver(xiic_i2c_driver);
  657. MODULE_AUTHOR("info@mocean-labs.com");
  658. MODULE_DESCRIPTION("Xilinx I2C bus driver");
  659. MODULE_LICENSE("GPL v2");
  660. MODULE_ALIAS("platform:"DRIVER_NAME);