i2c-amd8111.c 12 KB

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  1. /*
  2. * SMBus 2.0 driver for AMD-8111 IO-Hub.
  3. *
  4. * Copyright (c) 2002 Vojtech Pavlik
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation version 2.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/pci.h>
  12. #include <linux/kernel.h>
  13. #include <linux/stddef.h>
  14. #include <linux/ioport.h>
  15. #include <linux/init.h>
  16. #include <linux/i2c.h>
  17. #include <linux/delay.h>
  18. #include <linux/acpi.h>
  19. #include <linux/slab.h>
  20. #include <linux/io.h>
  21. MODULE_LICENSE("GPL");
  22. MODULE_AUTHOR ("Vojtech Pavlik <vojtech@suse.cz>");
  23. MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver");
  24. struct amd_smbus {
  25. struct pci_dev *dev;
  26. struct i2c_adapter adapter;
  27. int base;
  28. int size;
  29. };
  30. static struct pci_driver amd8111_driver;
  31. /*
  32. * AMD PCI control registers definitions.
  33. */
  34. #define AMD_PCI_MISC 0x48
  35. #define AMD_PCI_MISC_SCI 0x04 /* deliver SCI */
  36. #define AMD_PCI_MISC_INT 0x02 /* deliver PCI IRQ */
  37. #define AMD_PCI_MISC_SPEEDUP 0x01 /* 16x clock speedup */
  38. /*
  39. * ACPI 2.0 chapter 13 PCI interface definitions.
  40. */
  41. #define AMD_EC_DATA 0x00 /* data register */
  42. #define AMD_EC_SC 0x04 /* status of controller */
  43. #define AMD_EC_CMD 0x04 /* command register */
  44. #define AMD_EC_ICR 0x08 /* interrupt control register */
  45. #define AMD_EC_SC_SMI 0x04 /* smi event pending */
  46. #define AMD_EC_SC_SCI 0x02 /* sci event pending */
  47. #define AMD_EC_SC_BURST 0x01 /* burst mode enabled */
  48. #define AMD_EC_SC_CMD 0x08 /* byte in data reg is command */
  49. #define AMD_EC_SC_IBF 0x02 /* data ready for embedded controller */
  50. #define AMD_EC_SC_OBF 0x01 /* data ready for host */
  51. #define AMD_EC_CMD_RD 0x80 /* read EC */
  52. #define AMD_EC_CMD_WR 0x81 /* write EC */
  53. #define AMD_EC_CMD_BE 0x82 /* enable burst mode */
  54. #define AMD_EC_CMD_BD 0x83 /* disable burst mode */
  55. #define AMD_EC_CMD_QR 0x84 /* query EC */
  56. /*
  57. * ACPI 2.0 chapter 13 access of registers of the EC
  58. */
  59. static int amd_ec_wait_write(struct amd_smbus *smbus)
  60. {
  61. int timeout = 500;
  62. while ((inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF) && --timeout)
  63. udelay(1);
  64. if (!timeout) {
  65. dev_warn(&smbus->dev->dev,
  66. "Timeout while waiting for IBF to clear\n");
  67. return -ETIMEDOUT;
  68. }
  69. return 0;
  70. }
  71. static int amd_ec_wait_read(struct amd_smbus *smbus)
  72. {
  73. int timeout = 500;
  74. while ((~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF) && --timeout)
  75. udelay(1);
  76. if (!timeout) {
  77. dev_warn(&smbus->dev->dev,
  78. "Timeout while waiting for OBF to set\n");
  79. return -ETIMEDOUT;
  80. }
  81. return 0;
  82. }
  83. static int amd_ec_read(struct amd_smbus *smbus, unsigned char address,
  84. unsigned char *data)
  85. {
  86. int status;
  87. status = amd_ec_wait_write(smbus);
  88. if (status)
  89. return status;
  90. outb(AMD_EC_CMD_RD, smbus->base + AMD_EC_CMD);
  91. status = amd_ec_wait_write(smbus);
  92. if (status)
  93. return status;
  94. outb(address, smbus->base + AMD_EC_DATA);
  95. status = amd_ec_wait_read(smbus);
  96. if (status)
  97. return status;
  98. *data = inb(smbus->base + AMD_EC_DATA);
  99. return 0;
  100. }
  101. static int amd_ec_write(struct amd_smbus *smbus, unsigned char address,
  102. unsigned char data)
  103. {
  104. int status;
  105. status = amd_ec_wait_write(smbus);
  106. if (status)
  107. return status;
  108. outb(AMD_EC_CMD_WR, smbus->base + AMD_EC_CMD);
  109. status = amd_ec_wait_write(smbus);
  110. if (status)
  111. return status;
  112. outb(address, smbus->base + AMD_EC_DATA);
  113. status = amd_ec_wait_write(smbus);
  114. if (status)
  115. return status;
  116. outb(data, smbus->base + AMD_EC_DATA);
  117. return 0;
  118. }
  119. /*
  120. * ACPI 2.0 chapter 13 SMBus 2.0 EC register model
  121. */
  122. #define AMD_SMB_PRTCL 0x00 /* protocol, PEC */
  123. #define AMD_SMB_STS 0x01 /* status */
  124. #define AMD_SMB_ADDR 0x02 /* address */
  125. #define AMD_SMB_CMD 0x03 /* command */
  126. #define AMD_SMB_DATA 0x04 /* 32 data registers */
  127. #define AMD_SMB_BCNT 0x24 /* number of data bytes */
  128. #define AMD_SMB_ALRM_A 0x25 /* alarm address */
  129. #define AMD_SMB_ALRM_D 0x26 /* 2 bytes alarm data */
  130. #define AMD_SMB_STS_DONE 0x80
  131. #define AMD_SMB_STS_ALRM 0x40
  132. #define AMD_SMB_STS_RES 0x20
  133. #define AMD_SMB_STS_STATUS 0x1f
  134. #define AMD_SMB_STATUS_OK 0x00
  135. #define AMD_SMB_STATUS_FAIL 0x07
  136. #define AMD_SMB_STATUS_DNAK 0x10
  137. #define AMD_SMB_STATUS_DERR 0x11
  138. #define AMD_SMB_STATUS_CMD_DENY 0x12
  139. #define AMD_SMB_STATUS_UNKNOWN 0x13
  140. #define AMD_SMB_STATUS_ACC_DENY 0x17
  141. #define AMD_SMB_STATUS_TIMEOUT 0x18
  142. #define AMD_SMB_STATUS_NOTSUP 0x19
  143. #define AMD_SMB_STATUS_BUSY 0x1A
  144. #define AMD_SMB_STATUS_PEC 0x1F
  145. #define AMD_SMB_PRTCL_WRITE 0x00
  146. #define AMD_SMB_PRTCL_READ 0x01
  147. #define AMD_SMB_PRTCL_QUICK 0x02
  148. #define AMD_SMB_PRTCL_BYTE 0x04
  149. #define AMD_SMB_PRTCL_BYTE_DATA 0x06
  150. #define AMD_SMB_PRTCL_WORD_DATA 0x08
  151. #define AMD_SMB_PRTCL_BLOCK_DATA 0x0a
  152. #define AMD_SMB_PRTCL_PROC_CALL 0x0c
  153. #define AMD_SMB_PRTCL_BLOCK_PROC_CALL 0x0d
  154. #define AMD_SMB_PRTCL_I2C_BLOCK_DATA 0x4a
  155. #define AMD_SMB_PRTCL_PEC 0x80
  156. static s32 amd8111_access(struct i2c_adapter * adap, u16 addr,
  157. unsigned short flags, char read_write, u8 command, int size,
  158. union i2c_smbus_data * data)
  159. {
  160. struct amd_smbus *smbus = adap->algo_data;
  161. unsigned char protocol, len, pec, temp[2];
  162. int i, status;
  163. protocol = (read_write == I2C_SMBUS_READ) ? AMD_SMB_PRTCL_READ
  164. : AMD_SMB_PRTCL_WRITE;
  165. pec = (flags & I2C_CLIENT_PEC) ? AMD_SMB_PRTCL_PEC : 0;
  166. switch (size) {
  167. case I2C_SMBUS_QUICK:
  168. protocol |= AMD_SMB_PRTCL_QUICK;
  169. read_write = I2C_SMBUS_WRITE;
  170. break;
  171. case I2C_SMBUS_BYTE:
  172. if (read_write == I2C_SMBUS_WRITE) {
  173. status = amd_ec_write(smbus, AMD_SMB_CMD,
  174. command);
  175. if (status)
  176. return status;
  177. }
  178. protocol |= AMD_SMB_PRTCL_BYTE;
  179. break;
  180. case I2C_SMBUS_BYTE_DATA:
  181. status = amd_ec_write(smbus, AMD_SMB_CMD, command);
  182. if (status)
  183. return status;
  184. if (read_write == I2C_SMBUS_WRITE) {
  185. status = amd_ec_write(smbus, AMD_SMB_DATA,
  186. data->byte);
  187. if (status)
  188. return status;
  189. }
  190. protocol |= AMD_SMB_PRTCL_BYTE_DATA;
  191. break;
  192. case I2C_SMBUS_WORD_DATA:
  193. status = amd_ec_write(smbus, AMD_SMB_CMD, command);
  194. if (status)
  195. return status;
  196. if (read_write == I2C_SMBUS_WRITE) {
  197. status = amd_ec_write(smbus, AMD_SMB_DATA,
  198. data->word & 0xff);
  199. if (status)
  200. return status;
  201. status = amd_ec_write(smbus, AMD_SMB_DATA + 1,
  202. data->word >> 8);
  203. if (status)
  204. return status;
  205. }
  206. protocol |= AMD_SMB_PRTCL_WORD_DATA | pec;
  207. break;
  208. case I2C_SMBUS_BLOCK_DATA:
  209. status = amd_ec_write(smbus, AMD_SMB_CMD, command);
  210. if (status)
  211. return status;
  212. if (read_write == I2C_SMBUS_WRITE) {
  213. len = min_t(u8, data->block[0],
  214. I2C_SMBUS_BLOCK_MAX);
  215. status = amd_ec_write(smbus, AMD_SMB_BCNT, len);
  216. if (status)
  217. return status;
  218. for (i = 0; i < len; i++) {
  219. status =
  220. amd_ec_write(smbus, AMD_SMB_DATA + i,
  221. data->block[i + 1]);
  222. if (status)
  223. return status;
  224. }
  225. }
  226. protocol |= AMD_SMB_PRTCL_BLOCK_DATA | pec;
  227. break;
  228. case I2C_SMBUS_I2C_BLOCK_DATA:
  229. len = min_t(u8, data->block[0],
  230. I2C_SMBUS_BLOCK_MAX);
  231. status = amd_ec_write(smbus, AMD_SMB_CMD, command);
  232. if (status)
  233. return status;
  234. status = amd_ec_write(smbus, AMD_SMB_BCNT, len);
  235. if (status)
  236. return status;
  237. if (read_write == I2C_SMBUS_WRITE)
  238. for (i = 0; i < len; i++) {
  239. status =
  240. amd_ec_write(smbus, AMD_SMB_DATA + i,
  241. data->block[i + 1]);
  242. if (status)
  243. return status;
  244. }
  245. protocol |= AMD_SMB_PRTCL_I2C_BLOCK_DATA;
  246. break;
  247. case I2C_SMBUS_PROC_CALL:
  248. status = amd_ec_write(smbus, AMD_SMB_CMD, command);
  249. if (status)
  250. return status;
  251. status = amd_ec_write(smbus, AMD_SMB_DATA,
  252. data->word & 0xff);
  253. if (status)
  254. return status;
  255. status = amd_ec_write(smbus, AMD_SMB_DATA + 1,
  256. data->word >> 8);
  257. if (status)
  258. return status;
  259. protocol = AMD_SMB_PRTCL_PROC_CALL | pec;
  260. read_write = I2C_SMBUS_READ;
  261. break;
  262. case I2C_SMBUS_BLOCK_PROC_CALL:
  263. len = min_t(u8, data->block[0],
  264. I2C_SMBUS_BLOCK_MAX - 1);
  265. status = amd_ec_write(smbus, AMD_SMB_CMD, command);
  266. if (status)
  267. return status;
  268. status = amd_ec_write(smbus, AMD_SMB_BCNT, len);
  269. if (status)
  270. return status;
  271. for (i = 0; i < len; i++) {
  272. status = amd_ec_write(smbus, AMD_SMB_DATA + i,
  273. data->block[i + 1]);
  274. if (status)
  275. return status;
  276. }
  277. protocol = AMD_SMB_PRTCL_BLOCK_PROC_CALL | pec;
  278. read_write = I2C_SMBUS_READ;
  279. break;
  280. default:
  281. dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
  282. return -EOPNOTSUPP;
  283. }
  284. status = amd_ec_write(smbus, AMD_SMB_ADDR, addr << 1);
  285. if (status)
  286. return status;
  287. status = amd_ec_write(smbus, AMD_SMB_PRTCL, protocol);
  288. if (status)
  289. return status;
  290. status = amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
  291. if (status)
  292. return status;
  293. if (~temp[0] & AMD_SMB_STS_DONE) {
  294. udelay(500);
  295. status = amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
  296. if (status)
  297. return status;
  298. }
  299. if (~temp[0] & AMD_SMB_STS_DONE) {
  300. msleep(1);
  301. status = amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
  302. if (status)
  303. return status;
  304. }
  305. if ((~temp[0] & AMD_SMB_STS_DONE) || (temp[0] & AMD_SMB_STS_STATUS))
  306. return -EIO;
  307. if (read_write == I2C_SMBUS_WRITE)
  308. return 0;
  309. switch (size) {
  310. case I2C_SMBUS_BYTE:
  311. case I2C_SMBUS_BYTE_DATA:
  312. status = amd_ec_read(smbus, AMD_SMB_DATA, &data->byte);
  313. if (status)
  314. return status;
  315. break;
  316. case I2C_SMBUS_WORD_DATA:
  317. case I2C_SMBUS_PROC_CALL:
  318. status = amd_ec_read(smbus, AMD_SMB_DATA, temp + 0);
  319. if (status)
  320. return status;
  321. status = amd_ec_read(smbus, AMD_SMB_DATA + 1, temp + 1);
  322. if (status)
  323. return status;
  324. data->word = (temp[1] << 8) | temp[0];
  325. break;
  326. case I2C_SMBUS_BLOCK_DATA:
  327. case I2C_SMBUS_BLOCK_PROC_CALL:
  328. status = amd_ec_read(smbus, AMD_SMB_BCNT, &len);
  329. if (status)
  330. return status;
  331. len = min_t(u8, len, I2C_SMBUS_BLOCK_MAX);
  332. case I2C_SMBUS_I2C_BLOCK_DATA:
  333. for (i = 0; i < len; i++) {
  334. status = amd_ec_read(smbus, AMD_SMB_DATA + i,
  335. data->block + i + 1);
  336. if (status)
  337. return status;
  338. }
  339. data->block[0] = len;
  340. break;
  341. }
  342. return 0;
  343. }
  344. static u32 amd8111_func(struct i2c_adapter *adapter)
  345. {
  346. return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
  347. I2C_FUNC_SMBUS_BYTE_DATA |
  348. I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA |
  349. I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
  350. I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_PEC;
  351. }
  352. static const struct i2c_algorithm smbus_algorithm = {
  353. .smbus_xfer = amd8111_access,
  354. .functionality = amd8111_func,
  355. };
  356. static DEFINE_PCI_DEVICE_TABLE(amd8111_ids) = {
  357. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS2) },
  358. { 0, }
  359. };
  360. MODULE_DEVICE_TABLE (pci, amd8111_ids);
  361. static int __devinit amd8111_probe(struct pci_dev *dev,
  362. const struct pci_device_id *id)
  363. {
  364. struct amd_smbus *smbus;
  365. int error;
  366. if (!(pci_resource_flags(dev, 0) & IORESOURCE_IO))
  367. return -ENODEV;
  368. smbus = kzalloc(sizeof(struct amd_smbus), GFP_KERNEL);
  369. if (!smbus)
  370. return -ENOMEM;
  371. smbus->dev = dev;
  372. smbus->base = pci_resource_start(dev, 0);
  373. smbus->size = pci_resource_len(dev, 0);
  374. error = acpi_check_resource_conflict(&dev->resource[0]);
  375. if (error) {
  376. error = -ENODEV;
  377. goto out_kfree;
  378. }
  379. if (!request_region(smbus->base, smbus->size, amd8111_driver.name)) {
  380. error = -EBUSY;
  381. goto out_kfree;
  382. }
  383. smbus->adapter.owner = THIS_MODULE;
  384. snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
  385. "SMBus2 AMD8111 adapter at %04x", smbus->base);
  386. smbus->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
  387. smbus->adapter.algo = &smbus_algorithm;
  388. smbus->adapter.algo_data = smbus;
  389. /* set up the sysfs linkage to our parent device */
  390. smbus->adapter.dev.parent = &dev->dev;
  391. pci_write_config_dword(smbus->dev, AMD_PCI_MISC, 0);
  392. error = i2c_add_adapter(&smbus->adapter);
  393. if (error)
  394. goto out_release_region;
  395. pci_set_drvdata(dev, smbus);
  396. return 0;
  397. out_release_region:
  398. release_region(smbus->base, smbus->size);
  399. out_kfree:
  400. kfree(smbus);
  401. return error;
  402. }
  403. static void __devexit amd8111_remove(struct pci_dev *dev)
  404. {
  405. struct amd_smbus *smbus = pci_get_drvdata(dev);
  406. i2c_del_adapter(&smbus->adapter);
  407. release_region(smbus->base, smbus->size);
  408. kfree(smbus);
  409. }
  410. static struct pci_driver amd8111_driver = {
  411. .name = "amd8111_smbus2",
  412. .id_table = amd8111_ids,
  413. .probe = amd8111_probe,
  414. .remove = __devexit_p(amd8111_remove),
  415. };
  416. static int __init i2c_amd8111_init(void)
  417. {
  418. return pci_register_driver(&amd8111_driver);
  419. }
  420. static void __exit i2c_amd8111_exit(void)
  421. {
  422. pci_unregister_driver(&amd8111_driver);
  423. }
  424. module_init(i2c_amd8111_init);
  425. module_exit(i2c_amd8111_exit);