nv04_fb.c 1.2 KB

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  1. #include "drmP.h"
  2. #include "drm.h"
  3. #include "nouveau_drv.h"
  4. #include "nouveau_drm.h"
  5. int
  6. nv04_fb_vram_init(struct drm_device *dev)
  7. {
  8. struct drm_nouveau_private *dev_priv = dev->dev_private;
  9. u32 boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
  10. if (boot0 & 0x00000100) {
  11. dev_priv->vram_size = ((boot0 >> 12) & 0xf) * 2 + 2;
  12. dev_priv->vram_size *= 1024 * 1024;
  13. } else {
  14. switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
  15. case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
  16. dev_priv->vram_size = 32 * 1024 * 1024;
  17. break;
  18. case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
  19. dev_priv->vram_size = 16 * 1024 * 1024;
  20. break;
  21. case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
  22. dev_priv->vram_size = 8 * 1024 * 1024;
  23. break;
  24. case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
  25. dev_priv->vram_size = 4 * 1024 * 1024;
  26. break;
  27. }
  28. }
  29. if ((boot0 & 0x00000038) <= 0x10)
  30. dev_priv->vram_type = NV_MEM_TYPE_SGRAM;
  31. else
  32. dev_priv->vram_type = NV_MEM_TYPE_SDRAM;
  33. return 0;
  34. }
  35. int
  36. nv04_fb_init(struct drm_device *dev)
  37. {
  38. /* This is what the DDX did for NV_ARCH_04, but a mmio-trace shows
  39. * nvidia reading PFB_CFG_0, then writing back its original value.
  40. * (which was 0x701114 in this case)
  41. */
  42. nv_wr32(dev, NV04_PFB_CFG0, 0x1114);
  43. return 0;
  44. }
  45. void
  46. nv04_fb_takedown(struct drm_device *dev)
  47. {
  48. }