nouveau_drv.c 14 KB

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  1. /*
  2. * Copyright 2005 Stephane Marchesin.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. */
  24. #include <linux/console.h>
  25. #include <linux/module.h>
  26. #include "drmP.h"
  27. #include "drm.h"
  28. #include "drm_crtc_helper.h"
  29. #include "nouveau_drv.h"
  30. #include "nouveau_hw.h"
  31. #include "nouveau_fb.h"
  32. #include "nouveau_fbcon.h"
  33. #include "nouveau_pm.h"
  34. #include "nv50_display.h"
  35. #include "drm_pciids.h"
  36. MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
  37. int nouveau_agpmode = -1;
  38. module_param_named(agpmode, nouveau_agpmode, int, 0400);
  39. MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
  40. int nouveau_modeset = -1;
  41. module_param_named(modeset, nouveau_modeset, int, 0400);
  42. MODULE_PARM_DESC(vbios, "Override default VBIOS location");
  43. char *nouveau_vbios;
  44. module_param_named(vbios, nouveau_vbios, charp, 0400);
  45. MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
  46. int nouveau_vram_pushbuf;
  47. module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
  48. MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
  49. int nouveau_vram_notify = 0;
  50. module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
  51. MODULE_PARM_DESC(vram_type, "Override detected VRAM type");
  52. char *nouveau_vram_type;
  53. module_param_named(vram_type, nouveau_vram_type, charp, 0400);
  54. MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
  55. int nouveau_duallink = 1;
  56. module_param_named(duallink, nouveau_duallink, int, 0400);
  57. MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
  58. int nouveau_uscript_lvds = -1;
  59. module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
  60. MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
  61. int nouveau_uscript_tmds = -1;
  62. module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
  63. MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
  64. int nouveau_ignorelid = 0;
  65. module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
  66. MODULE_PARM_DESC(noaccel, "Disable all acceleration");
  67. int nouveau_noaccel = -1;
  68. module_param_named(noaccel, nouveau_noaccel, int, 0400);
  69. MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
  70. int nouveau_nofbaccel = 0;
  71. module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
  72. MODULE_PARM_DESC(force_post, "Force POST");
  73. int nouveau_force_post = 0;
  74. module_param_named(force_post, nouveau_force_post, int, 0400);
  75. MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
  76. int nouveau_override_conntype = 0;
  77. module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
  78. MODULE_PARM_DESC(tv_disable, "Disable TV-out detection");
  79. int nouveau_tv_disable = 0;
  80. module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
  81. MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
  82. "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
  83. "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
  84. "\t\tDefault: PAL\n"
  85. "\t\t*NOTE* Ignored for cards with external TV encoders.");
  86. char *nouveau_tv_norm;
  87. module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
  88. MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
  89. "\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
  90. "\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
  91. "\t\t0x100 vgaattr, 0x200 EVO (G80+)");
  92. int nouveau_reg_debug;
  93. module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
  94. MODULE_PARM_DESC(perflvl, "Performance level (default: boot)");
  95. char *nouveau_perflvl;
  96. module_param_named(perflvl, nouveau_perflvl, charp, 0400);
  97. MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)");
  98. int nouveau_perflvl_wr;
  99. module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);
  100. MODULE_PARM_DESC(msi, "Enable MSI (default: off)");
  101. int nouveau_msi;
  102. module_param_named(msi, nouveau_msi, int, 0400);
  103. MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)");
  104. int nouveau_ctxfw;
  105. module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
  106. MODULE_PARM_DESC(mxmdcb, "Santise DCB table according to MXM-SIS");
  107. int nouveau_mxmdcb = 1;
  108. module_param_named(mxmdcb, nouveau_mxmdcb, int, 0400);
  109. int nouveau_fbpercrtc;
  110. #if 0
  111. module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
  112. #endif
  113. static struct pci_device_id pciidlist[] = {
  114. {
  115. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
  116. .class = PCI_BASE_CLASS_DISPLAY << 16,
  117. .class_mask = 0xff << 16,
  118. },
  119. {
  120. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
  121. .class = PCI_BASE_CLASS_DISPLAY << 16,
  122. .class_mask = 0xff << 16,
  123. },
  124. {}
  125. };
  126. MODULE_DEVICE_TABLE(pci, pciidlist);
  127. static struct drm_driver driver;
  128. static int __devinit
  129. nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  130. {
  131. return drm_get_pci_dev(pdev, ent, &driver);
  132. }
  133. static void
  134. nouveau_pci_remove(struct pci_dev *pdev)
  135. {
  136. struct drm_device *dev = pci_get_drvdata(pdev);
  137. drm_put_dev(dev);
  138. }
  139. int
  140. nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
  141. {
  142. struct drm_device *dev = pci_get_drvdata(pdev);
  143. struct drm_nouveau_private *dev_priv = dev->dev_private;
  144. struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
  145. struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  146. struct nouveau_channel *chan;
  147. struct drm_crtc *crtc;
  148. int ret, i, e;
  149. if (pm_state.event == PM_EVENT_PRETHAW)
  150. return 0;
  151. if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  152. return 0;
  153. if (dev->mode_config.num_crtc) {
  154. NV_INFO(dev, "Disabling display...\n");
  155. nouveau_display_fini(dev);
  156. NV_INFO(dev, "Disabling fbcon...\n");
  157. nouveau_fbcon_set_suspend(dev, 1);
  158. }
  159. NV_INFO(dev, "Unpinning framebuffer(s)...\n");
  160. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  161. struct nouveau_framebuffer *nouveau_fb;
  162. nouveau_fb = nouveau_framebuffer(crtc->fb);
  163. if (!nouveau_fb || !nouveau_fb->nvbo)
  164. continue;
  165. nouveau_bo_unpin(nouveau_fb->nvbo);
  166. }
  167. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  168. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  169. nouveau_bo_unmap(nv_crtc->cursor.nvbo);
  170. nouveau_bo_unpin(nv_crtc->cursor.nvbo);
  171. }
  172. NV_INFO(dev, "Evicting buffers...\n");
  173. ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
  174. NV_INFO(dev, "Idling channels...\n");
  175. for (i = 0; i < pfifo->channels; i++) {
  176. chan = dev_priv->channels.ptr[i];
  177. if (chan && chan->pushbuf_bo)
  178. nouveau_channel_idle(chan);
  179. }
  180. pfifo->reassign(dev, false);
  181. pfifo->disable(dev);
  182. pfifo->unload_context(dev);
  183. for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
  184. if (!dev_priv->eng[e])
  185. continue;
  186. ret = dev_priv->eng[e]->fini(dev, e, true);
  187. if (ret) {
  188. NV_ERROR(dev, "... engine %d failed: %d\n", e, ret);
  189. goto out_abort;
  190. }
  191. }
  192. ret = pinstmem->suspend(dev);
  193. if (ret) {
  194. NV_ERROR(dev, "... failed: %d\n", ret);
  195. goto out_abort;
  196. }
  197. NV_INFO(dev, "Suspending GPU objects...\n");
  198. ret = nouveau_gpuobj_suspend(dev);
  199. if (ret) {
  200. NV_ERROR(dev, "... failed: %d\n", ret);
  201. pinstmem->resume(dev);
  202. goto out_abort;
  203. }
  204. NV_INFO(dev, "And we're gone!\n");
  205. pci_save_state(pdev);
  206. if (pm_state.event == PM_EVENT_SUSPEND) {
  207. pci_disable_device(pdev);
  208. pci_set_power_state(pdev, PCI_D3hot);
  209. }
  210. return 0;
  211. out_abort:
  212. NV_INFO(dev, "Re-enabling acceleration..\n");
  213. for (e = e + 1; e < NVOBJ_ENGINE_NR; e++) {
  214. if (dev_priv->eng[e])
  215. dev_priv->eng[e]->init(dev, e);
  216. }
  217. pfifo->enable(dev);
  218. pfifo->reassign(dev, true);
  219. return ret;
  220. }
  221. int
  222. nouveau_pci_resume(struct pci_dev *pdev)
  223. {
  224. struct drm_device *dev = pci_get_drvdata(pdev);
  225. struct drm_nouveau_private *dev_priv = dev->dev_private;
  226. struct nouveau_engine *engine = &dev_priv->engine;
  227. struct drm_crtc *crtc;
  228. int ret, i;
  229. if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  230. return 0;
  231. NV_INFO(dev, "We're back, enabling device...\n");
  232. pci_set_power_state(pdev, PCI_D0);
  233. pci_restore_state(pdev);
  234. if (pci_enable_device(pdev))
  235. return -1;
  236. pci_set_master(dev->pdev);
  237. /* Make sure the AGP controller is in a consistent state */
  238. if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
  239. nouveau_mem_reset_agp(dev);
  240. /* Make the CRTCs accessible */
  241. engine->display.early_init(dev);
  242. NV_INFO(dev, "POSTing device...\n");
  243. ret = nouveau_run_vbios_init(dev);
  244. if (ret)
  245. return ret;
  246. if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
  247. ret = nouveau_mem_init_agp(dev);
  248. if (ret) {
  249. NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
  250. return ret;
  251. }
  252. }
  253. NV_INFO(dev, "Restoring GPU objects...\n");
  254. nouveau_gpuobj_resume(dev);
  255. NV_INFO(dev, "Reinitialising engines...\n");
  256. engine->instmem.resume(dev);
  257. engine->mc.init(dev);
  258. engine->timer.init(dev);
  259. engine->fb.init(dev);
  260. for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
  261. if (dev_priv->eng[i])
  262. dev_priv->eng[i]->init(dev, i);
  263. }
  264. engine->fifo.init(dev);
  265. nouveau_irq_postinstall(dev);
  266. /* Re-write SKIPS, they'll have been lost over the suspend */
  267. if (nouveau_vram_pushbuf) {
  268. struct nouveau_channel *chan;
  269. int j;
  270. for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
  271. chan = dev_priv->channels.ptr[i];
  272. if (!chan || !chan->pushbuf_bo)
  273. continue;
  274. for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
  275. nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
  276. }
  277. }
  278. nouveau_pm_resume(dev);
  279. NV_INFO(dev, "Restoring mode...\n");
  280. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  281. struct nouveau_framebuffer *nouveau_fb;
  282. nouveau_fb = nouveau_framebuffer(crtc->fb);
  283. if (!nouveau_fb || !nouveau_fb->nvbo)
  284. continue;
  285. nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
  286. }
  287. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  288. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  289. ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
  290. if (!ret)
  291. ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
  292. if (ret)
  293. NV_ERROR(dev, "Could not pin/map cursor.\n");
  294. }
  295. if (dev->mode_config.num_crtc) {
  296. nouveau_fbcon_set_suspend(dev, 0);
  297. nouveau_fbcon_zfill_all(dev);
  298. nouveau_display_init(dev);
  299. }
  300. /* Force CLUT to get re-loaded during modeset */
  301. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  302. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  303. nv_crtc->lut.depth = 0;
  304. }
  305. drm_helper_resume_force_mode(dev);
  306. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  307. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  308. u32 offset = nv_crtc->cursor.nvbo->bo.offset;
  309. nv_crtc->cursor.set_offset(nv_crtc, offset);
  310. nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
  311. nv_crtc->cursor_saved_y);
  312. }
  313. return 0;
  314. }
  315. static const struct file_operations nouveau_driver_fops = {
  316. .owner = THIS_MODULE,
  317. .open = drm_open,
  318. .release = drm_release,
  319. .unlocked_ioctl = drm_ioctl,
  320. .mmap = nouveau_ttm_mmap,
  321. .poll = drm_poll,
  322. .fasync = drm_fasync,
  323. .read = drm_read,
  324. #if defined(CONFIG_COMPAT)
  325. .compat_ioctl = nouveau_compat_ioctl,
  326. #endif
  327. .llseek = noop_llseek,
  328. };
  329. static struct drm_driver driver = {
  330. .driver_features =
  331. DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
  332. DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
  333. DRIVER_MODESET,
  334. .load = nouveau_load,
  335. .firstopen = nouveau_firstopen,
  336. .lastclose = nouveau_lastclose,
  337. .unload = nouveau_unload,
  338. .open = nouveau_open,
  339. .preclose = nouveau_preclose,
  340. .postclose = nouveau_postclose,
  341. #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
  342. .debugfs_init = nouveau_debugfs_init,
  343. .debugfs_cleanup = nouveau_debugfs_takedown,
  344. #endif
  345. .irq_preinstall = nouveau_irq_preinstall,
  346. .irq_postinstall = nouveau_irq_postinstall,
  347. .irq_uninstall = nouveau_irq_uninstall,
  348. .irq_handler = nouveau_irq_handler,
  349. .get_vblank_counter = drm_vblank_count,
  350. .enable_vblank = nouveau_vblank_enable,
  351. .disable_vblank = nouveau_vblank_disable,
  352. .reclaim_buffers = drm_core_reclaim_buffers,
  353. .ioctls = nouveau_ioctls,
  354. .fops = &nouveau_driver_fops,
  355. .gem_init_object = nouveau_gem_object_new,
  356. .gem_free_object = nouveau_gem_object_del,
  357. .gem_open_object = nouveau_gem_object_open,
  358. .gem_close_object = nouveau_gem_object_close,
  359. .dumb_create = nouveau_display_dumb_create,
  360. .dumb_map_offset = nouveau_display_dumb_map_offset,
  361. .dumb_destroy = nouveau_display_dumb_destroy,
  362. .name = DRIVER_NAME,
  363. .desc = DRIVER_DESC,
  364. #ifdef GIT_REVISION
  365. .date = GIT_REVISION,
  366. #else
  367. .date = DRIVER_DATE,
  368. #endif
  369. .major = DRIVER_MAJOR,
  370. .minor = DRIVER_MINOR,
  371. .patchlevel = DRIVER_PATCHLEVEL,
  372. };
  373. static struct pci_driver nouveau_pci_driver = {
  374. .name = DRIVER_NAME,
  375. .id_table = pciidlist,
  376. .probe = nouveau_pci_probe,
  377. .remove = nouveau_pci_remove,
  378. .suspend = nouveau_pci_suspend,
  379. .resume = nouveau_pci_resume
  380. };
  381. static int __init nouveau_init(void)
  382. {
  383. driver.num_ioctls = nouveau_max_ioctl;
  384. if (nouveau_modeset == -1) {
  385. #ifdef CONFIG_VGA_CONSOLE
  386. if (vgacon_text_force())
  387. nouveau_modeset = 0;
  388. #endif
  389. }
  390. if (!nouveau_modeset)
  391. return 0;
  392. nouveau_register_dsm_handler();
  393. return drm_pci_init(&driver, &nouveau_pci_driver);
  394. }
  395. static void __exit nouveau_exit(void)
  396. {
  397. if (!nouveau_modeset)
  398. return;
  399. drm_pci_exit(&driver, &nouveau_pci_driver);
  400. nouveau_unregister_dsm_handler();
  401. }
  402. module_init(nouveau_init);
  403. module_exit(nouveau_exit);
  404. MODULE_AUTHOR(DRIVER_AUTHOR);
  405. MODULE_DESCRIPTION(DRIVER_DESC);
  406. MODULE_LICENSE("GPL and additional rights");