coresight-tmc.c 47 KB

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  1. /* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/types.h>
  16. #include <linux/device.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/io.h>
  19. #include <linux/err.h>
  20. #include <linux/fs.h>
  21. #include <linux/miscdevice.h>
  22. #include <linux/uaccess.h>
  23. #include <linux/slab.h>
  24. #include <linux/delay.h>
  25. #include <linux/spinlock.h>
  26. #include <linux/clk.h>
  27. #include <linux/of.h>
  28. #include <linux/of_coresight.h>
  29. #include <linux/coresight.h>
  30. #include <linux/coresight-cti.h>
  31. #include <linux/wait.h>
  32. #include <linux/sched.h>
  33. #include <linux/interrupt.h>
  34. #include <linux/cdev.h>
  35. #include <linux/usb/usb_qdss.h>
  36. #include <linux/dma-mapping.h>
  37. #include <mach/sps.h>
  38. #include <mach/usb_bam.h>
  39. #include <mach/msm_memory_dump.h>
  40. #include "coresight-priv.h"
  41. #define tmc_writel(drvdata, val, off) __raw_writel((val), drvdata->base + off)
  42. #define tmc_readl(drvdata, off) __raw_readl(drvdata->base + off)
  43. #define tmc_readl_no_log(drvdata, off) __raw_readl_no_log(drvdata->base + off)
  44. #define TMC_LOCK(drvdata) \
  45. do { \
  46. mb(); \
  47. tmc_writel(drvdata, 0x0, CORESIGHT_LAR); \
  48. } while (0)
  49. #define TMC_UNLOCK(drvdata) \
  50. do { \
  51. tmc_writel(drvdata, CORESIGHT_UNLOCK, CORESIGHT_LAR); \
  52. mb(); \
  53. } while (0)
  54. #define TMC_RSZ (0x004)
  55. #define TMC_STS (0x00C)
  56. #define TMC_RRD (0x010)
  57. #define TMC_RRP (0x014)
  58. #define TMC_RWP (0x018)
  59. #define TMC_TRG (0x01C)
  60. #define TMC_CTL (0x020)
  61. #define TMC_RWD (0x024)
  62. #define TMC_MODE (0x028)
  63. #define TMC_LBUFLEVEL (0x02C)
  64. #define TMC_CBUFLEVEL (0x030)
  65. #define TMC_BUFWM (0x034)
  66. #define TMC_RRPHI (0x038)
  67. #define TMC_RWPHI (0x03C)
  68. #define TMC_AXICTL (0x110)
  69. #define TMC_DBALO (0x118)
  70. #define TMC_DBAHI (0x11C)
  71. #define TMC_FFSR (0x300)
  72. #define TMC_FFCR (0x304)
  73. #define TMC_PSCR (0x308)
  74. #define TMC_ITMISCOP0 (0xEE0)
  75. #define TMC_ITTRFLIN (0xEE8)
  76. #define TMC_ITATBDATA0 (0xEEC)
  77. #define TMC_ITATBCTR2 (0xEF0)
  78. #define TMC_ITATBCTR1 (0xEF4)
  79. #define TMC_ITATBCTR0 (0xEF8)
  80. #define BYTES_PER_WORD 4
  81. #define TMC_ETR_BAM_PIPE_INDEX 0
  82. #define TMC_ETR_BAM_NR_PIPES 2
  83. #define TMC_ETFETB_DUMP_MAGIC_OFF (0)
  84. #define TMC_ETFETB_DUMP_MAGIC (0x5D1DB1BF)
  85. #define TMC_ETFETB_DUMP_VER_OFF (4)
  86. #define TMC_ETFETB_DUMP_VER (1)
  87. #define TMC_REG_DUMP_MAGIC_OFF (0)
  88. #define TMC_REG_DUMP_MAGIC (0x5D1DB1BF)
  89. #define TMC_REG_DUMP_VER_OFF (4)
  90. #define TMC_REG_DUMP_VER (1)
  91. enum tmc_config_type {
  92. TMC_CONFIG_TYPE_ETB,
  93. TMC_CONFIG_TYPE_ETR,
  94. TMC_CONFIG_TYPE_ETF,
  95. };
  96. enum tmc_mode {
  97. TMC_MODE_CIRCULAR_BUFFER,
  98. TMC_MODE_SOFTWARE_FIFO,
  99. TMC_MODE_HARDWARE_FIFO,
  100. };
  101. enum tmc_etr_out_mode {
  102. TMC_ETR_OUT_MODE_NONE,
  103. TMC_ETR_OUT_MODE_MEM,
  104. TMC_ETR_OUT_MODE_USB,
  105. };
  106. enum tmc_mem_intf_width {
  107. TMC_MEM_INTF_WIDTH_32BITS = 0x2,
  108. TMC_MEM_INTF_WIDTH_64BITS = 0x3,
  109. TMC_MEM_INTF_WIDTH_128BITS = 0x4,
  110. TMC_MEM_INTF_WIDTH_256BITS = 0x5,
  111. };
  112. struct tmc_etr_bam_data {
  113. struct sps_bam_props props;
  114. uint32_t handle;
  115. struct sps_pipe *pipe;
  116. struct sps_connect connect;
  117. uint32_t src_pipe_idx;
  118. uint32_t dest;
  119. uint32_t dest_pipe_idx;
  120. struct sps_mem_buffer desc_fifo;
  121. struct sps_mem_buffer data_fifo;
  122. bool enable;
  123. };
  124. struct tmc_drvdata {
  125. void __iomem *base;
  126. struct device *dev;
  127. struct coresight_device *csdev;
  128. struct miscdevice miscdev;
  129. struct cdev byte_cntr_dev;
  130. struct class *byte_cntr_class;
  131. struct clk *clk;
  132. spinlock_t spinlock;
  133. bool reset_flush_race;
  134. struct coresight_cti *cti_flush;
  135. struct coresight_cti *cti_reset;
  136. struct mutex read_lock;
  137. int read_count;
  138. bool reading;
  139. bool aborting;
  140. char *reg_buf;
  141. char *buf;
  142. dma_addr_t paddr;
  143. void __iomem *vaddr;
  144. uint32_t size;
  145. struct mutex usb_lock;
  146. struct usb_qdss_ch *usbch;
  147. struct tmc_etr_bam_data *bamdata;
  148. enum tmc_etr_out_mode out_mode;
  149. bool enable_to_bam;
  150. bool enable;
  151. enum tmc_config_type config_type;
  152. uint32_t trigger_cntr;
  153. int byte_cntr_irq;
  154. atomic_t byte_cntr_irq_cnt;
  155. uint32_t byte_cntr_value;
  156. struct mutex byte_cntr_read_lock;
  157. struct mutex byte_cntr_lock;
  158. uint32_t byte_cntr_block_size;
  159. bool byte_cntr_overflow;
  160. bool byte_cntr_present;
  161. bool byte_cntr_enable;
  162. uint32_t byte_cntr_overflow_cnt;
  163. bool byte_cntr_read_active;
  164. wait_queue_head_t wq;
  165. char *byte_cntr_node;
  166. uint32_t mem_size;
  167. };
  168. static void tmc_wait_for_flush(struct tmc_drvdata *drvdata)
  169. {
  170. int count;
  171. /* Ensure no flush is in progress */
  172. for (count = TIMEOUT_US; BVAL(tmc_readl(drvdata, TMC_FFSR), 0) != 0
  173. && count > 0; count--)
  174. udelay(1);
  175. WARN(count == 0, "timeout while waiting for TMC flush, TMC_FFSR: %#x\n",
  176. tmc_readl(drvdata, TMC_FFSR));
  177. }
  178. static void tmc_wait_for_ready(struct tmc_drvdata *drvdata)
  179. {
  180. int count;
  181. /* Ensure formatter, unformatter and hardware fifo are empty */
  182. for (count = TIMEOUT_US; BVAL(tmc_readl(drvdata, TMC_STS), 2) != 1
  183. && count > 0; count--)
  184. udelay(1);
  185. WARN(count == 0, "timeout while waiting for TMC ready, TMC_STS: %#x\n",
  186. tmc_readl(drvdata, TMC_STS));
  187. }
  188. static void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
  189. {
  190. int count;
  191. uint32_t ffcr;
  192. ffcr = tmc_readl(drvdata, TMC_FFCR);
  193. ffcr |= BIT(12);
  194. tmc_writel(drvdata, ffcr, TMC_FFCR);
  195. ffcr |= BIT(6);
  196. tmc_writel(drvdata, ffcr, TMC_FFCR);
  197. /* Ensure flush completes */
  198. for (count = TIMEOUT_US; BVAL(tmc_readl(drvdata, TMC_FFCR), 6) != 0
  199. && count > 0; count--)
  200. udelay(1);
  201. WARN(count == 0, "timeout while flushing TMC, TMC_FFCR: %#x\n",
  202. tmc_readl(drvdata, TMC_FFCR));
  203. tmc_wait_for_ready(drvdata);
  204. }
  205. static void __tmc_enable(struct tmc_drvdata *drvdata)
  206. {
  207. tmc_writel(drvdata, 0x1, TMC_CTL);
  208. }
  209. static void __tmc_disable(struct tmc_drvdata *drvdata)
  210. {
  211. tmc_writel(drvdata, 0x0, TMC_CTL);
  212. }
  213. static void tmc_etr_fill_usb_bam_data(struct tmc_drvdata *drvdata)
  214. {
  215. struct tmc_etr_bam_data *bamdata = drvdata->bamdata;
  216. get_bam2bam_connection_info(usb_bam_get_qdss_idx(0),
  217. &bamdata->dest,
  218. &bamdata->dest_pipe_idx,
  219. &bamdata->src_pipe_idx,
  220. &bamdata->desc_fifo,
  221. &bamdata->data_fifo);
  222. }
  223. static void __tmc_etr_enable_to_bam(struct tmc_drvdata *drvdata)
  224. {
  225. struct tmc_etr_bam_data *bamdata = drvdata->bamdata;
  226. uint32_t axictl;
  227. if (drvdata->enable_to_bam)
  228. return;
  229. /* Configure and enable required CSR registers */
  230. msm_qdss_csr_enable_bam_to_usb();
  231. /* Configure and enable ETR for usb bam output */
  232. TMC_UNLOCK(drvdata);
  233. tmc_writel(drvdata, bamdata->data_fifo.size / BYTES_PER_WORD,
  234. TMC_RSZ);
  235. tmc_writel(drvdata, TMC_MODE_CIRCULAR_BUFFER, TMC_MODE);
  236. axictl = tmc_readl(drvdata, TMC_AXICTL);
  237. axictl |= (0xF << 8);
  238. tmc_writel(drvdata, axictl, TMC_AXICTL);
  239. axictl &= ~(0x1 << 7);
  240. tmc_writel(drvdata, axictl, TMC_AXICTL);
  241. axictl = (axictl & ~0x3) | 0x2;
  242. tmc_writel(drvdata, axictl, TMC_AXICTL);
  243. tmc_writel(drvdata, (uint32_t)bamdata->data_fifo.phys_base, TMC_DBALO);
  244. tmc_writel(drvdata, (((uint64_t)bamdata->data_fifo.phys_base) >> 32)
  245. & 0xFF, TMC_DBAHI);
  246. /* Set FOnFlIn for periodic flush */
  247. tmc_writel(drvdata, 0x133, TMC_FFCR);
  248. tmc_writel(drvdata, drvdata->trigger_cntr, TMC_TRG);
  249. __tmc_enable(drvdata);
  250. TMC_LOCK(drvdata);
  251. drvdata->enable_to_bam = true;
  252. }
  253. static int tmc_etr_bam_enable(struct tmc_drvdata *drvdata)
  254. {
  255. struct tmc_etr_bam_data *bamdata = drvdata->bamdata;
  256. int ret;
  257. if (bamdata->enable)
  258. return 0;
  259. /* Reset bam to start with */
  260. ret = sps_device_reset(bamdata->handle);
  261. if (ret)
  262. goto err0;
  263. /* Now configure and enable bam */
  264. bamdata->pipe = sps_alloc_endpoint();
  265. if (!bamdata->pipe)
  266. return -ENOMEM;
  267. ret = sps_get_config(bamdata->pipe, &bamdata->connect);
  268. if (ret)
  269. goto err1;
  270. bamdata->connect.mode = SPS_MODE_SRC;
  271. bamdata->connect.source = bamdata->handle;
  272. bamdata->connect.event_thresh = 0x4;
  273. bamdata->connect.src_pipe_index = TMC_ETR_BAM_PIPE_INDEX;
  274. bamdata->connect.options = SPS_O_AUTO_ENABLE;
  275. bamdata->connect.destination = bamdata->dest;
  276. bamdata->connect.dest_pipe_index = bamdata->dest_pipe_idx;
  277. bamdata->connect.desc = bamdata->desc_fifo;
  278. bamdata->connect.data = bamdata->data_fifo;
  279. ret = sps_connect(bamdata->pipe, &bamdata->connect);
  280. if (ret)
  281. goto err1;
  282. bamdata->enable = true;
  283. return 0;
  284. err1:
  285. sps_free_endpoint(bamdata->pipe);
  286. err0:
  287. return ret;
  288. }
  289. static void __tmc_etr_disable_to_bam(struct tmc_drvdata *drvdata)
  290. {
  291. if (!drvdata->enable_to_bam)
  292. return;
  293. /* Ensure periodic flush is disabled in CSR block */
  294. msm_qdss_csr_disable_flush();
  295. TMC_UNLOCK(drvdata);
  296. tmc_wait_for_flush(drvdata);
  297. __tmc_disable(drvdata);
  298. TMC_LOCK(drvdata);
  299. /* Disable CSR configuration */
  300. msm_qdss_csr_disable_bam_to_usb();
  301. drvdata->enable_to_bam = false;
  302. }
  303. static void tmc_etr_bam_disable(struct tmc_drvdata *drvdata)
  304. {
  305. struct tmc_etr_bam_data *bamdata = drvdata->bamdata;
  306. if (!bamdata->enable)
  307. return;
  308. sps_disconnect(bamdata->pipe);
  309. sps_free_endpoint(bamdata->pipe);
  310. bamdata->enable = false;
  311. }
  312. static void usb_notifier(void *priv, unsigned int event,
  313. struct qdss_request *d_req, struct usb_qdss_ch *ch)
  314. {
  315. struct tmc_drvdata *drvdata = priv;
  316. unsigned long flags;
  317. int ret = 0;
  318. mutex_lock(&drvdata->usb_lock);
  319. if (event == USB_QDSS_CONNECT) {
  320. tmc_etr_fill_usb_bam_data(drvdata);
  321. ret = tmc_etr_bam_enable(drvdata);
  322. if (ret)
  323. dev_err(drvdata->dev, "ETR BAM enable failed\n");
  324. spin_lock_irqsave(&drvdata->spinlock, flags);
  325. __tmc_etr_enable_to_bam(drvdata);
  326. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  327. } else if (event == USB_QDSS_DISCONNECT) {
  328. spin_lock_irqsave(&drvdata->spinlock, flags);
  329. __tmc_etr_disable_to_bam(drvdata);
  330. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  331. tmc_etr_bam_disable(drvdata);
  332. }
  333. mutex_unlock(&drvdata->usb_lock);
  334. }
  335. static uint32_t tmc_etr_get_write_ptr(struct tmc_drvdata *drvdata)
  336. {
  337. uint32_t rwp = 0;
  338. TMC_UNLOCK(drvdata);
  339. rwp = tmc_readl(drvdata, TMC_RWP);
  340. TMC_LOCK(drvdata);
  341. return rwp;
  342. }
  343. static void tmc_etr_byte_cntr_start(struct tmc_drvdata *drvdata)
  344. {
  345. if (!drvdata->byte_cntr_present)
  346. return;
  347. mutex_lock(&drvdata->byte_cntr_lock);
  348. atomic_set(&drvdata->byte_cntr_irq_cnt, 0);
  349. drvdata->byte_cntr_overflow = false;
  350. drvdata->byte_cntr_read_active = false;
  351. drvdata->byte_cntr_enable = true;
  352. if (drvdata->byte_cntr_value != 0)
  353. drvdata->byte_cntr_overflow_cnt = drvdata->size /
  354. (drvdata->byte_cntr_value * 8);
  355. else
  356. drvdata->byte_cntr_overflow_cnt = 0;
  357. coresight_csr_set_byte_cntr(drvdata->byte_cntr_value);
  358. mutex_unlock(&drvdata->byte_cntr_lock);
  359. }
  360. static void tmc_etr_byte_cntr_stop(struct tmc_drvdata *drvdata)
  361. {
  362. if (!drvdata->byte_cntr_present)
  363. return;
  364. mutex_lock(&drvdata->byte_cntr_lock);
  365. coresight_csr_set_byte_cntr(0);
  366. drvdata->byte_cntr_value = 0;
  367. drvdata->byte_cntr_enable = false;
  368. mutex_unlock(&drvdata->byte_cntr_lock);
  369. wake_up(&drvdata->wq);
  370. }
  371. static void __tmc_etb_enable(struct tmc_drvdata *drvdata)
  372. {
  373. /* Zero out the memory to help with debug */
  374. memset(drvdata->buf, 0, drvdata->size);
  375. TMC_UNLOCK(drvdata);
  376. tmc_writel(drvdata, TMC_MODE_CIRCULAR_BUFFER, TMC_MODE);
  377. tmc_writel(drvdata, 0x1133, TMC_FFCR);
  378. tmc_writel(drvdata, drvdata->trigger_cntr, TMC_TRG);
  379. __tmc_enable(drvdata);
  380. TMC_LOCK(drvdata);
  381. }
  382. static void __tmc_etr_enable_to_mem(struct tmc_drvdata *drvdata)
  383. {
  384. uint32_t axictl;
  385. /* Zero out the memory to help with debug */
  386. memset(drvdata->vaddr, 0, drvdata->size);
  387. TMC_UNLOCK(drvdata);
  388. tmc_writel(drvdata, drvdata->size / BYTES_PER_WORD, TMC_RSZ);
  389. tmc_writel(drvdata, TMC_MODE_CIRCULAR_BUFFER, TMC_MODE);
  390. axictl = tmc_readl(drvdata, TMC_AXICTL);
  391. axictl |= (0xF << 8);
  392. tmc_writel(drvdata, axictl, TMC_AXICTL);
  393. axictl &= ~(0x1 << 7);
  394. tmc_writel(drvdata, axictl, TMC_AXICTL);
  395. axictl = (axictl & ~0x3) | 0x2;
  396. tmc_writel(drvdata, axictl, TMC_AXICTL);
  397. tmc_writel(drvdata, (uint32_t)drvdata->paddr, TMC_DBALO);
  398. tmc_writel(drvdata, (((uint64_t)drvdata->paddr) >> 32) & 0xFF,
  399. TMC_DBAHI);
  400. tmc_writel(drvdata, 0x1133, TMC_FFCR);
  401. tmc_writel(drvdata, drvdata->trigger_cntr, TMC_TRG);
  402. __tmc_enable(drvdata);
  403. TMC_LOCK(drvdata);
  404. }
  405. static void __tmc_etf_enable(struct tmc_drvdata *drvdata)
  406. {
  407. TMC_UNLOCK(drvdata);
  408. tmc_writel(drvdata, TMC_MODE_HARDWARE_FIFO, TMC_MODE);
  409. tmc_writel(drvdata, 0x3, TMC_FFCR);
  410. tmc_writel(drvdata, 0x0, TMC_BUFWM);
  411. __tmc_enable(drvdata);
  412. TMC_LOCK(drvdata);
  413. }
  414. static int tmc_enable(struct tmc_drvdata *drvdata, enum tmc_mode mode)
  415. {
  416. int ret;
  417. unsigned long flags;
  418. ret = clk_prepare_enable(drvdata->clk);
  419. if (ret)
  420. return ret;
  421. mutex_lock(&drvdata->usb_lock);
  422. spin_lock_irqsave(&drvdata->spinlock, flags);
  423. if (drvdata->reading) {
  424. ret = -EBUSY;
  425. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  426. goto err0;
  427. }
  428. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  429. if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
  430. coresight_cti_map_trigout(drvdata->cti_flush, 1, 0);
  431. coresight_cti_map_trigin(drvdata->cti_reset, 0, 0);
  432. } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
  433. if (drvdata->out_mode == TMC_ETR_OUT_MODE_MEM) {
  434. tmc_etr_byte_cntr_start(drvdata);
  435. if (!drvdata->reset_flush_race) {
  436. coresight_cti_map_trigout(drvdata->cti_flush,
  437. 3, 0);
  438. coresight_cti_map_trigin(drvdata->cti_reset,
  439. 2, 0);
  440. }
  441. } else if (drvdata->out_mode == TMC_ETR_OUT_MODE_USB) {
  442. drvdata->usbch = usb_qdss_open("qdss", drvdata,
  443. usb_notifier);
  444. if (IS_ERR(drvdata->usbch)) {
  445. dev_err(drvdata->dev, "usb_qdss_open failed\n");
  446. ret = PTR_ERR(drvdata->usbch);
  447. goto err0;
  448. }
  449. }
  450. } else {
  451. if (mode == TMC_MODE_CIRCULAR_BUFFER) {
  452. coresight_cti_map_trigout(drvdata->cti_flush, 1, 0);
  453. coresight_cti_map_trigin(drvdata->cti_reset, 0, 0);
  454. }
  455. }
  456. spin_lock_irqsave(&drvdata->spinlock, flags);
  457. if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
  458. __tmc_etb_enable(drvdata);
  459. } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
  460. if (drvdata->out_mode == TMC_ETR_OUT_MODE_MEM)
  461. __tmc_etr_enable_to_mem(drvdata);
  462. } else {
  463. if (mode == TMC_MODE_CIRCULAR_BUFFER)
  464. __tmc_etb_enable(drvdata);
  465. else
  466. __tmc_etf_enable(drvdata);
  467. }
  468. drvdata->enable = true;
  469. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  470. mutex_unlock(&drvdata->usb_lock);
  471. dev_info(drvdata->dev, "TMC enabled\n");
  472. return 0;
  473. err0:
  474. mutex_unlock(&drvdata->usb_lock);
  475. clk_disable_unprepare(drvdata->clk);
  476. return ret;
  477. }
  478. static int tmc_enable_sink(struct coresight_device *csdev)
  479. {
  480. struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  481. return tmc_enable(drvdata, TMC_MODE_CIRCULAR_BUFFER);
  482. }
  483. static int tmc_enable_link(struct coresight_device *csdev, int inport,
  484. int outport)
  485. {
  486. struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  487. return tmc_enable(drvdata, TMC_MODE_HARDWARE_FIFO);
  488. }
  489. static void __tmc_reg_dump(struct tmc_drvdata *drvdata)
  490. {
  491. char *reg_hdr;
  492. uint32_t *reg_buf;
  493. if (!drvdata->reg_buf || !drvdata->aborting)
  494. return;
  495. reg_hdr = drvdata->reg_buf - PAGE_SIZE;
  496. reg_buf = (uint32_t *)drvdata->reg_buf;
  497. reg_buf[1] = tmc_readl(drvdata, TMC_RSZ);
  498. reg_buf[3] = tmc_readl(drvdata, TMC_STS);
  499. reg_buf[5] = tmc_readl(drvdata, TMC_RRP);
  500. reg_buf[6] = tmc_readl(drvdata, TMC_RWP);
  501. reg_buf[7] = tmc_readl(drvdata, TMC_TRG);
  502. reg_buf[8] = tmc_readl(drvdata, TMC_CTL);
  503. reg_buf[10] = tmc_readl(drvdata, TMC_MODE);
  504. reg_buf[11] = tmc_readl(drvdata, TMC_LBUFLEVEL);
  505. reg_buf[12] = tmc_readl(drvdata, TMC_CBUFLEVEL);
  506. reg_buf[13] = tmc_readl(drvdata, TMC_BUFWM);
  507. if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
  508. reg_buf[14] = tmc_readl(drvdata, TMC_RRPHI);
  509. reg_buf[15] = tmc_readl(drvdata, TMC_RWPHI);
  510. reg_buf[68] = tmc_readl(drvdata, TMC_AXICTL);
  511. reg_buf[70] = tmc_readl(drvdata, TMC_DBALO);
  512. reg_buf[71] = tmc_readl(drvdata, TMC_DBAHI);
  513. }
  514. reg_buf[192] = tmc_readl(drvdata, TMC_FFSR);
  515. reg_buf[193] = tmc_readl(drvdata, TMC_FFCR);
  516. reg_buf[194] = tmc_readl(drvdata, TMC_PSCR);
  517. reg_buf[1000] = tmc_readl(drvdata, CORESIGHT_CLAIMSET);
  518. reg_buf[1001] = tmc_readl(drvdata, CORESIGHT_CLAIMCLR);
  519. reg_buf[1005] = tmc_readl(drvdata, CORESIGHT_LSR);
  520. reg_buf[1006] = tmc_readl(drvdata, CORESIGHT_AUTHSTATUS);
  521. reg_buf[1010] = tmc_readl(drvdata, CORESIGHT_DEVID);
  522. reg_buf[1011] = tmc_readl(drvdata, CORESIGHT_DEVTYPE);
  523. reg_buf[1012] = tmc_readl(drvdata, CORESIGHT_PERIPHIDR4);
  524. reg_buf[1013] = tmc_readl(drvdata, CORESIGHT_PERIPHIDR5);
  525. reg_buf[1014] = tmc_readl(drvdata, CORESIGHT_PERIPHIDR6);
  526. reg_buf[1015] = tmc_readl(drvdata, CORESIGHT_PERIPHIDR7);
  527. reg_buf[1016] = tmc_readl(drvdata, CORESIGHT_PERIPHIDR0);
  528. reg_buf[1017] = tmc_readl(drvdata, CORESIGHT_PERIPHIDR1);
  529. reg_buf[1018] = tmc_readl(drvdata, CORESIGHT_PERIPHIDR2);
  530. reg_buf[1019] = tmc_readl(drvdata, CORESIGHT_PERIPHIDR3);
  531. reg_buf[1020] = tmc_readl(drvdata, CORESIGHT_COMPIDR0);
  532. reg_buf[1021] = tmc_readl(drvdata, CORESIGHT_COMPIDR1);
  533. reg_buf[1022] = tmc_readl(drvdata, CORESIGHT_COMPIDR2);
  534. reg_buf[1023] = tmc_readl(drvdata, CORESIGHT_COMPIDR3);
  535. *(uint32_t *)(reg_hdr + TMC_REG_DUMP_MAGIC_OFF) = TMC_REG_DUMP_MAGIC;
  536. }
  537. static void __tmc_etb_dump(struct tmc_drvdata *drvdata)
  538. {
  539. enum tmc_mem_intf_width memwidth;
  540. uint8_t memwords;
  541. char *hdr;
  542. char *bufp;
  543. uint32_t read_data;
  544. memwidth = BMVAL(tmc_readl(drvdata, CORESIGHT_DEVID), 8, 10);
  545. if (memwidth == TMC_MEM_INTF_WIDTH_32BITS)
  546. memwords = 1;
  547. else if (memwidth == TMC_MEM_INTF_WIDTH_64BITS)
  548. memwords = 2;
  549. else if (memwidth == TMC_MEM_INTF_WIDTH_128BITS)
  550. memwords = 4;
  551. else
  552. memwords = 8;
  553. bufp = drvdata->buf;
  554. while (1) {
  555. read_data = tmc_readl_no_log(drvdata, TMC_RRD);
  556. if (read_data == 0xFFFFFFFF)
  557. goto out;
  558. if ((bufp - drvdata->buf) >= drvdata->size) {
  559. dev_err(drvdata->dev, "ETF-ETB end marker missing\n");
  560. goto out;
  561. }
  562. memcpy(bufp, &read_data, BYTES_PER_WORD);
  563. bufp += BYTES_PER_WORD;
  564. }
  565. out:
  566. if ((bufp - drvdata->buf) % (memwords * BYTES_PER_WORD))
  567. dev_dbg(drvdata->dev, "ETF-ETB data is not %lx bytes aligned\n",
  568. (unsigned long) memwords * BYTES_PER_WORD);
  569. if (drvdata->aborting) {
  570. hdr = drvdata->buf - PAGE_SIZE;
  571. *(uint32_t *)(hdr + TMC_ETFETB_DUMP_MAGIC_OFF) =
  572. TMC_ETFETB_DUMP_MAGIC;
  573. }
  574. }
  575. static void __tmc_etb_disable(struct tmc_drvdata *drvdata)
  576. {
  577. TMC_UNLOCK(drvdata);
  578. tmc_flush_and_stop(drvdata);
  579. __tmc_etb_dump(drvdata);
  580. __tmc_reg_dump(drvdata);
  581. __tmc_disable(drvdata);
  582. TMC_LOCK(drvdata);
  583. }
  584. static void __tmc_etr_dump(struct tmc_drvdata *drvdata)
  585. {
  586. uint32_t rwp, rwphi;
  587. rwp = tmc_readl(drvdata, TMC_RWP);
  588. rwphi = tmc_readl(drvdata, TMC_RWPHI);
  589. if (BVAL(tmc_readl(drvdata, TMC_STS), 0))
  590. drvdata->buf = drvdata->vaddr + rwp - drvdata->paddr;
  591. else
  592. drvdata->buf = drvdata->vaddr;
  593. }
  594. static void __tmc_etr_disable_to_mem(struct tmc_drvdata *drvdata)
  595. {
  596. TMC_UNLOCK(drvdata);
  597. tmc_flush_and_stop(drvdata);
  598. __tmc_etr_dump(drvdata);
  599. __tmc_reg_dump(drvdata);
  600. __tmc_disable(drvdata);
  601. TMC_LOCK(drvdata);
  602. }
  603. static void __tmc_etf_disable(struct tmc_drvdata *drvdata)
  604. {
  605. TMC_UNLOCK(drvdata);
  606. tmc_flush_and_stop(drvdata);
  607. __tmc_disable(drvdata);
  608. TMC_LOCK(drvdata);
  609. }
  610. static void tmc_disable(struct tmc_drvdata *drvdata, enum tmc_mode mode)
  611. {
  612. unsigned long flags;
  613. mutex_lock(&drvdata->usb_lock);
  614. spin_lock_irqsave(&drvdata->spinlock, flags);
  615. if (drvdata->reading)
  616. goto out;
  617. if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
  618. __tmc_etb_disable(drvdata);
  619. } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
  620. if (drvdata->out_mode == TMC_ETR_OUT_MODE_MEM)
  621. __tmc_etr_disable_to_mem(drvdata);
  622. else if (drvdata->out_mode == TMC_ETR_OUT_MODE_USB)
  623. __tmc_etr_disable_to_bam(drvdata);
  624. } else {
  625. if (mode == TMC_MODE_CIRCULAR_BUFFER)
  626. __tmc_etb_disable(drvdata);
  627. else
  628. __tmc_etf_disable(drvdata);
  629. }
  630. drvdata->enable = false;
  631. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  632. if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
  633. coresight_cti_unmap_trigin(drvdata->cti_reset, 0, 0);
  634. coresight_cti_unmap_trigout(drvdata->cti_flush, 1, 0);
  635. } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
  636. if (drvdata->out_mode == TMC_ETR_OUT_MODE_MEM) {
  637. tmc_etr_byte_cntr_stop(drvdata);
  638. if (!drvdata->reset_flush_race) {
  639. coresight_cti_unmap_trigin(drvdata->cti_reset,
  640. 2, 0);
  641. coresight_cti_unmap_trigout(drvdata->cti_flush,
  642. 3, 0);
  643. }
  644. } else if (drvdata->out_mode == TMC_ETR_OUT_MODE_USB) {
  645. tmc_etr_bam_disable(drvdata);
  646. usb_qdss_close(drvdata->usbch);
  647. }
  648. } else {
  649. if (mode == TMC_MODE_CIRCULAR_BUFFER) {
  650. coresight_cti_unmap_trigin(drvdata->cti_reset, 0, 0);
  651. coresight_cti_unmap_trigout(drvdata->cti_flush, 1, 0);
  652. }
  653. }
  654. mutex_unlock(&drvdata->usb_lock);
  655. clk_disable_unprepare(drvdata->clk);
  656. dev_info(drvdata->dev, "TMC disabled\n");
  657. return;
  658. out:
  659. drvdata->enable = false;
  660. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  661. mutex_unlock(&drvdata->usb_lock);
  662. clk_disable_unprepare(drvdata->clk);
  663. dev_info(drvdata->dev, "TMC disabled\n");
  664. }
  665. static void tmc_disable_sink(struct coresight_device *csdev)
  666. {
  667. struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  668. tmc_disable(drvdata, TMC_MODE_CIRCULAR_BUFFER);
  669. }
  670. static void tmc_disable_link(struct coresight_device *csdev, int inport,
  671. int outport)
  672. {
  673. struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  674. tmc_disable(drvdata, TMC_MODE_HARDWARE_FIFO);
  675. }
  676. static void tmc_abort(struct coresight_device *csdev)
  677. {
  678. struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  679. unsigned long flags;
  680. enum tmc_mode mode;
  681. drvdata->aborting = true;
  682. spin_lock_irqsave(&drvdata->spinlock, flags);
  683. if (drvdata->reading)
  684. goto out0;
  685. if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
  686. __tmc_etb_disable(drvdata);
  687. } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
  688. if (drvdata->out_mode == TMC_ETR_OUT_MODE_MEM)
  689. __tmc_etr_disable_to_mem(drvdata);
  690. else if (drvdata->out_mode == TMC_ETR_OUT_MODE_USB)
  691. __tmc_etr_disable_to_bam(drvdata);
  692. } else {
  693. mode = tmc_readl(drvdata, TMC_MODE);
  694. if (mode == TMC_MODE_CIRCULAR_BUFFER)
  695. __tmc_etb_disable(drvdata);
  696. else
  697. goto out1;
  698. }
  699. out0:
  700. drvdata->enable = false;
  701. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  702. dev_info(drvdata->dev, "TMC aborted\n");
  703. return;
  704. out1:
  705. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  706. }
  707. static const struct coresight_ops_sink tmc_sink_ops = {
  708. .enable = tmc_enable_sink,
  709. .disable = tmc_disable_sink,
  710. .abort = tmc_abort,
  711. };
  712. static const struct coresight_ops_link tmc_link_ops = {
  713. .enable = tmc_enable_link,
  714. .disable = tmc_disable_link,
  715. };
  716. static const struct coresight_ops tmc_etb_cs_ops = {
  717. .sink_ops = &tmc_sink_ops,
  718. };
  719. static const struct coresight_ops tmc_etr_cs_ops = {
  720. .sink_ops = &tmc_sink_ops,
  721. };
  722. static const struct coresight_ops tmc_etf_cs_ops = {
  723. .sink_ops = &tmc_sink_ops,
  724. .link_ops = &tmc_link_ops,
  725. };
  726. static int tmc_read_prepare(struct tmc_drvdata *drvdata)
  727. {
  728. int ret;
  729. unsigned long flags;
  730. enum tmc_mode mode;
  731. spin_lock_irqsave(&drvdata->spinlock, flags);
  732. if (!drvdata->enable)
  733. goto out;
  734. if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
  735. __tmc_etb_disable(drvdata);
  736. } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
  737. if (drvdata->out_mode == TMC_ETR_OUT_MODE_MEM) {
  738. __tmc_etr_disable_to_mem(drvdata);
  739. } else {
  740. ret = -ENODEV;
  741. goto err;
  742. }
  743. } else {
  744. mode = tmc_readl(drvdata, TMC_MODE);
  745. if (mode == TMC_MODE_CIRCULAR_BUFFER) {
  746. __tmc_etb_disable(drvdata);
  747. } else {
  748. ret = -ENODEV;
  749. goto err;
  750. }
  751. }
  752. out:
  753. drvdata->reading = true;
  754. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  755. mutex_unlock(&drvdata->usb_lock);
  756. dev_info(drvdata->dev, "TMC read start\n");
  757. return 0;
  758. err:
  759. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  760. mutex_unlock(&drvdata->usb_lock);
  761. return ret;
  762. }
  763. static void tmc_read_unprepare(struct tmc_drvdata *drvdata)
  764. {
  765. unsigned long flags;
  766. enum tmc_mode mode;
  767. mutex_lock(&drvdata->usb_lock);
  768. spin_lock_irqsave(&drvdata->spinlock, flags);
  769. if (!drvdata->enable)
  770. goto out;
  771. if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
  772. __tmc_etb_enable(drvdata);
  773. } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
  774. if (drvdata->out_mode == TMC_ETR_OUT_MODE_MEM)
  775. __tmc_etr_enable_to_mem(drvdata);
  776. } else {
  777. mode = tmc_readl(drvdata, TMC_MODE);
  778. if (mode == TMC_MODE_CIRCULAR_BUFFER)
  779. __tmc_etb_enable(drvdata);
  780. }
  781. out:
  782. drvdata->reading = false;
  783. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  784. dev_info(drvdata->dev, "TMC read end\n");
  785. }
  786. static int tmc_open(struct inode *inode, struct file *file)
  787. {
  788. struct tmc_drvdata *drvdata = container_of(file->private_data,
  789. struct tmc_drvdata, miscdev);
  790. int ret = 0;
  791. mutex_lock(&drvdata->read_lock);
  792. if (drvdata->read_count++)
  793. goto out;
  794. ret = tmc_read_prepare(drvdata);
  795. if (ret)
  796. goto err;
  797. out:
  798. mutex_unlock(&drvdata->read_lock);
  799. nonseekable_open(inode, file);
  800. dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
  801. return 0;
  802. err:
  803. drvdata->read_count--;
  804. mutex_unlock(&drvdata->read_lock);
  805. return ret;
  806. }
  807. static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
  808. loff_t *ppos)
  809. {
  810. struct tmc_drvdata *drvdata = container_of(file->private_data,
  811. struct tmc_drvdata, miscdev);
  812. char *bufp;
  813. mutex_lock(&drvdata->usb_lock);
  814. bufp = drvdata->buf + *ppos;
  815. if (*ppos + len > drvdata->size)
  816. len = drvdata->size - *ppos;
  817. if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
  818. if (bufp == (char *)(drvdata->vaddr + drvdata->size))
  819. bufp = drvdata->vaddr;
  820. else if (bufp > (char *)(drvdata->vaddr + drvdata->size))
  821. bufp -= drvdata->size;
  822. if ((bufp + len) > (char *)(drvdata->vaddr + drvdata->size))
  823. len = (char *)(drvdata->vaddr + drvdata->size) - bufp;
  824. }
  825. if (copy_to_user(data, bufp, len)) {
  826. dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
  827. mutex_unlock(&drvdata->usb_lock);
  828. return -EFAULT;
  829. }
  830. *ppos += len;
  831. dev_dbg(drvdata->dev, "%s: %d bytes copied, %d bytes left\n",
  832. __func__, len, (int) (drvdata->size - *ppos));
  833. mutex_unlock(&drvdata->usb_lock);
  834. return len;
  835. }
  836. static int tmc_release(struct inode *inode, struct file *file)
  837. {
  838. struct tmc_drvdata *drvdata = container_of(file->private_data,
  839. struct tmc_drvdata, miscdev);
  840. mutex_lock(&drvdata->read_lock);
  841. if (--drvdata->read_count) {
  842. if (drvdata->read_count < 0) {
  843. WARN_ONCE(1, "mismatched close\n");
  844. drvdata->read_count = 0;
  845. }
  846. goto out;
  847. }
  848. tmc_read_unprepare(drvdata);
  849. out:
  850. mutex_unlock(&drvdata->read_lock);
  851. dev_dbg(drvdata->dev, "%s: released\n", __func__);
  852. return 0;
  853. }
  854. static const struct file_operations tmc_fops = {
  855. .owner = THIS_MODULE,
  856. .open = tmc_open,
  857. .read = tmc_read,
  858. .release = tmc_release,
  859. .llseek = no_llseek,
  860. };
  861. static int tmc_etr_byte_cntr_open(struct inode *inode, struct file *file)
  862. {
  863. struct tmc_drvdata *drvdata = container_of(inode->i_cdev,
  864. struct tmc_drvdata,
  865. byte_cntr_dev);
  866. if (drvdata->out_mode != TMC_ETR_OUT_MODE_MEM ||
  867. !drvdata->byte_cntr_enable)
  868. return -EPERM;
  869. if (!mutex_trylock(&drvdata->byte_cntr_read_lock))
  870. return -EPERM;
  871. file->private_data = drvdata;
  872. nonseekable_open(inode, file);
  873. drvdata->byte_cntr_block_size = drvdata->byte_cntr_value * 8;
  874. drvdata->byte_cntr_read_active = true;
  875. dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
  876. return 0;
  877. }
  878. static void tmc_etr_read_bytes(struct tmc_drvdata *drvdata, loff_t *ppos,
  879. size_t bytes, size_t *len)
  880. {
  881. if (*len >= bytes) {
  882. atomic_dec(&drvdata->byte_cntr_irq_cnt);
  883. *len = bytes;
  884. } else {
  885. if (((uint32_t)*ppos % bytes) + *len > bytes)
  886. *len = bytes - ((uint32_t)*ppos % bytes);
  887. if ((*len + (uint32_t)*ppos) % bytes == 0)
  888. atomic_dec(&drvdata->byte_cntr_irq_cnt);
  889. }
  890. }
  891. static size_t tmc_etr_flush_bytes(struct tmc_drvdata *drvdata, loff_t *ppos,
  892. size_t bytes)
  893. {
  894. uint32_t rwp = 0;
  895. size_t len = bytes;
  896. rwp = tmc_etr_get_write_ptr(drvdata);
  897. if (rwp >= (drvdata->paddr + *ppos)) {
  898. if (len > (rwp - drvdata->paddr - *ppos))
  899. len = rwp - drvdata->paddr - *ppos;
  900. }
  901. return len;
  902. }
  903. static ssize_t tmc_etr_byte_cntr_read(struct file *file, char __user *data,
  904. size_t len, loff_t *ppos)
  905. {
  906. struct tmc_drvdata *drvdata = file->private_data;
  907. char *bufp = drvdata->vaddr + *ppos;
  908. size_t bytes = drvdata->byte_cntr_block_size;
  909. int ret = 0;
  910. if (!data)
  911. return -EINVAL;
  912. if (drvdata->byte_cntr_overflow)
  913. return -EIO;
  914. mutex_lock(&drvdata->byte_cntr_lock);
  915. /* In case the byte counter is enabled and disabled multiple times
  916. * prevent unexpected data from being given to the user
  917. */
  918. if (!drvdata->byte_cntr_read_active)
  919. goto read_err0;
  920. if (!drvdata->byte_cntr_enable) {
  921. if (!atomic_read(&drvdata->byte_cntr_irq_cnt)) {
  922. /* Read the last 'block' of data which might be needed
  923. * to be read partially. If already read, return 0
  924. */
  925. len = tmc_etr_flush_bytes(drvdata, ppos, bytes);
  926. if (!len)
  927. goto read_err0;
  928. } else {
  929. /* Keep reading until you reach the last block of data
  930. */
  931. tmc_etr_read_bytes(drvdata, ppos, bytes, &len);
  932. }
  933. } else {
  934. if (!atomic_read(&drvdata->byte_cntr_irq_cnt)) {
  935. mutex_unlock(&drvdata->byte_cntr_lock);
  936. if (wait_event_interruptible(drvdata->wq,
  937. (atomic_read(&drvdata->byte_cntr_irq_cnt) > 0) ||
  938. !drvdata->byte_cntr_enable)) {
  939. ret = -ERESTARTSYS;
  940. goto read_err1;
  941. }
  942. mutex_lock(&drvdata->byte_cntr_lock);
  943. if (!drvdata->byte_cntr_read_active) {
  944. ret = 0;
  945. goto read_err0;
  946. }
  947. }
  948. if (drvdata->byte_cntr_overflow) {
  949. ret = -EIO;
  950. goto read_err0;
  951. }
  952. if (!drvdata->byte_cntr_enable &&
  953. !atomic_read(&drvdata->byte_cntr_irq_cnt)) {
  954. len = tmc_etr_flush_bytes(drvdata, ppos, bytes);
  955. if (!len) {
  956. ret = 0;
  957. goto read_err0;
  958. }
  959. } else {
  960. tmc_etr_read_bytes(drvdata, ppos, bytes, &len);
  961. }
  962. }
  963. if (copy_to_user(data, bufp, len)) {
  964. mutex_unlock(&drvdata->byte_cntr_lock);
  965. dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
  966. ret = -EFAULT;
  967. goto read_err1;
  968. }
  969. mutex_unlock(&drvdata->byte_cntr_lock);
  970. if (*ppos + len >= drvdata->size)
  971. *ppos = 0;
  972. else
  973. *ppos += len;
  974. dev_dbg(drvdata->dev, "%s: %d bytes copied, %d bytes left\n",
  975. __func__, len, (int) (drvdata->size - *ppos));
  976. return len;
  977. read_err0:
  978. mutex_unlock(&drvdata->byte_cntr_lock);
  979. read_err1:
  980. return ret;
  981. }
  982. static int tmc_etr_byte_cntr_release(struct inode *inode, struct file *file)
  983. {
  984. struct tmc_drvdata *drvdata = file->private_data;
  985. mutex_lock(&drvdata->byte_cntr_lock);
  986. drvdata->byte_cntr_read_active = false;
  987. mutex_unlock(&drvdata->byte_cntr_lock);
  988. mutex_unlock(&drvdata->byte_cntr_read_lock);
  989. dev_dbg(drvdata->dev, "%s: released\n", __func__);
  990. return 0;
  991. }
  992. static const struct file_operations byte_cntr_fops = {
  993. .owner = THIS_MODULE,
  994. .open = tmc_etr_byte_cntr_open,
  995. .read = tmc_etr_byte_cntr_read,
  996. .release = tmc_etr_byte_cntr_release,
  997. .llseek = no_llseek,
  998. };
  999. static ssize_t tmc_show_trigger_cntr(struct device *dev,
  1000. struct device_attribute *attr, char *buf)
  1001. {
  1002. struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
  1003. unsigned long val = drvdata->trigger_cntr;
  1004. return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
  1005. }
  1006. static ssize_t tmc_store_trigger_cntr(struct device *dev,
  1007. struct device_attribute *attr,
  1008. const char *buf, size_t size)
  1009. {
  1010. struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
  1011. unsigned long val;
  1012. if (sscanf(buf, "%lx", &val) != 1)
  1013. return -EINVAL;
  1014. drvdata->trigger_cntr = val;
  1015. return size;
  1016. }
  1017. static DEVICE_ATTR(trigger_cntr, S_IRUGO | S_IWUSR, tmc_show_trigger_cntr,
  1018. tmc_store_trigger_cntr);
  1019. static ssize_t tmc_etr_show_out_mode(struct device *dev,
  1020. struct device_attribute *attr, char *buf)
  1021. {
  1022. struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
  1023. return scnprintf(buf, PAGE_SIZE, "%s\n",
  1024. drvdata->out_mode == TMC_ETR_OUT_MODE_MEM ?
  1025. "mem" : "usb");
  1026. }
  1027. static ssize_t tmc_etr_store_out_mode(struct device *dev,
  1028. struct device_attribute *attr,
  1029. const char *buf, size_t size)
  1030. {
  1031. struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
  1032. char str[10] = "";
  1033. unsigned long flags;
  1034. int ret;
  1035. if (strlen(buf) >= 10)
  1036. return -EINVAL;
  1037. if (sscanf(buf, "%s", str) != 1)
  1038. return -EINVAL;
  1039. mutex_lock(&drvdata->usb_lock);
  1040. if (!strcmp(str, "mem")) {
  1041. if (drvdata->out_mode == TMC_ETR_OUT_MODE_MEM)
  1042. goto out;
  1043. spin_lock_irqsave(&drvdata->spinlock, flags);
  1044. if (!drvdata->enable) {
  1045. drvdata->out_mode = TMC_ETR_OUT_MODE_MEM;
  1046. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  1047. goto out;
  1048. }
  1049. __tmc_etr_disable_to_bam(drvdata);
  1050. __tmc_etr_enable_to_mem(drvdata);
  1051. drvdata->out_mode = TMC_ETR_OUT_MODE_MEM;
  1052. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  1053. if (!drvdata->reset_flush_race) {
  1054. coresight_cti_map_trigout(drvdata->cti_flush, 3, 0);
  1055. coresight_cti_map_trigin(drvdata->cti_reset, 2, 0);
  1056. }
  1057. tmc_etr_bam_disable(drvdata);
  1058. usb_qdss_close(drvdata->usbch);
  1059. } else if (!strcmp(str, "usb")) {
  1060. if (drvdata->out_mode == TMC_ETR_OUT_MODE_USB)
  1061. goto out;
  1062. spin_lock_irqsave(&drvdata->spinlock, flags);
  1063. if (!drvdata->enable) {
  1064. drvdata->out_mode = TMC_ETR_OUT_MODE_USB;
  1065. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  1066. goto out;
  1067. }
  1068. if (drvdata->reading) {
  1069. ret = -EBUSY;
  1070. goto err1;
  1071. }
  1072. __tmc_etr_disable_to_mem(drvdata);
  1073. drvdata->out_mode = TMC_ETR_OUT_MODE_USB;
  1074. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  1075. if (!drvdata->reset_flush_race) {
  1076. coresight_cti_unmap_trigin(drvdata->cti_reset, 2, 0);
  1077. coresight_cti_unmap_trigout(drvdata->cti_flush, 3, 0);
  1078. }
  1079. drvdata->usbch = usb_qdss_open("qdss", drvdata,
  1080. usb_notifier);
  1081. if (IS_ERR(drvdata->usbch)) {
  1082. dev_err(drvdata->dev, "usb_qdss_open failed\n");
  1083. ret = PTR_ERR(drvdata->usbch);
  1084. goto err0;
  1085. }
  1086. }
  1087. out:
  1088. mutex_unlock(&drvdata->usb_lock);
  1089. return size;
  1090. err1:
  1091. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  1092. err0:
  1093. mutex_unlock(&drvdata->usb_lock);
  1094. return ret;
  1095. }
  1096. static DEVICE_ATTR(out_mode, S_IRUGO | S_IWUSR, tmc_etr_show_out_mode,
  1097. tmc_etr_store_out_mode);
  1098. static ssize_t tmc_etr_show_byte_cntr_value(struct device *dev,
  1099. struct device_attribute *attr,
  1100. char *buf)
  1101. {
  1102. struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
  1103. unsigned long val = drvdata->byte_cntr_value;
  1104. if (!drvdata->byte_cntr_present)
  1105. return -EPERM;
  1106. return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
  1107. }
  1108. static ssize_t tmc_etr_store_byte_cntr_value(struct device *dev,
  1109. struct device_attribute *attr,
  1110. const char *buf, size_t size)
  1111. {
  1112. struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
  1113. unsigned long val;
  1114. if (!drvdata->byte_cntr_present || drvdata->byte_cntr_enable)
  1115. return -EPERM;
  1116. if (sscanf(buf, "%lx", &val) != 1)
  1117. return -EINVAL;
  1118. if ((drvdata->size / 8) < val)
  1119. return -EINVAL;
  1120. if (val && drvdata->size % (val * 8) != 0)
  1121. return -EINVAL;
  1122. drvdata->byte_cntr_value = val;
  1123. return size;
  1124. }
  1125. static DEVICE_ATTR(byte_cntr_value, S_IRUGO | S_IWUSR,
  1126. tmc_etr_show_byte_cntr_value, tmc_etr_store_byte_cntr_value);
  1127. static ssize_t tmc_etr_show_mem_size(struct device *dev,
  1128. struct device_attribute *attr,
  1129. char *buf)
  1130. {
  1131. struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
  1132. unsigned long val = drvdata->mem_size;
  1133. return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
  1134. }
  1135. static ssize_t tmc_etr_store_mem_size(struct device *dev,
  1136. struct device_attribute *attr,
  1137. const char *buf, size_t size)
  1138. {
  1139. struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
  1140. unsigned long val;
  1141. if (sscanf(buf, "%lx", &val) != 1)
  1142. return -EINVAL;
  1143. drvdata->mem_size = val;
  1144. return size;
  1145. }
  1146. static DEVICE_ATTR(mem_size, S_IRUGO | S_IWUSR,
  1147. tmc_etr_show_mem_size, tmc_etr_store_mem_size);
  1148. static struct attribute *tmc_attrs[] = {
  1149. &dev_attr_trigger_cntr.attr,
  1150. NULL,
  1151. };
  1152. static struct attribute_group tmc_attr_grp = {
  1153. .attrs = tmc_attrs,
  1154. };
  1155. static struct attribute *tmc_etr_attrs[] = {
  1156. &dev_attr_out_mode.attr,
  1157. &dev_attr_byte_cntr_value.attr,
  1158. &dev_attr_mem_size.attr,
  1159. NULL,
  1160. };
  1161. static struct attribute_group tmc_etr_attr_grp = {
  1162. .attrs = tmc_etr_attrs,
  1163. };
  1164. static const struct attribute_group *tmc_etb_attr_grps[] = {
  1165. &tmc_attr_grp,
  1166. NULL,
  1167. };
  1168. static const struct attribute_group *tmc_etr_attr_grps[] = {
  1169. &tmc_attr_grp,
  1170. &tmc_etr_attr_grp,
  1171. NULL,
  1172. };
  1173. static const struct attribute_group *tmc_etf_attr_grps[] = {
  1174. &tmc_attr_grp,
  1175. NULL,
  1176. };
  1177. static int __devinit tmc_etr_bam_init(struct platform_device *pdev,
  1178. struct tmc_drvdata *drvdata)
  1179. {
  1180. struct device *dev = &pdev->dev;
  1181. struct resource *res;
  1182. struct tmc_etr_bam_data *bamdata;
  1183. bamdata = devm_kzalloc(dev, sizeof(*bamdata), GFP_KERNEL);
  1184. if (!bamdata)
  1185. return -ENOMEM;
  1186. drvdata->bamdata = bamdata;
  1187. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bam-base");
  1188. if (!res)
  1189. return -ENODEV;
  1190. bamdata->props.phys_addr = res->start;
  1191. bamdata->props.virt_addr = devm_ioremap(dev, res->start,
  1192. resource_size(res));
  1193. if (!bamdata->props.virt_addr)
  1194. return -ENOMEM;
  1195. bamdata->props.virt_size = resource_size(res);
  1196. bamdata->props.event_threshold = 0x4; /* Pipe event threshold */
  1197. bamdata->props.summing_threshold = 0x10; /* BAM event threshold */
  1198. bamdata->props.irq = 0;
  1199. bamdata->props.num_pipes = TMC_ETR_BAM_NR_PIPES;
  1200. return sps_register_bam_device(&bamdata->props, &bamdata->handle);
  1201. }
  1202. static void tmc_etr_bam_exit(struct tmc_drvdata *drvdata)
  1203. {
  1204. struct tmc_etr_bam_data *bamdata = drvdata->bamdata;
  1205. if (!bamdata->handle)
  1206. return;
  1207. sps_deregister_bam_device(bamdata->handle);
  1208. }
  1209. static irqreturn_t tmc_etr_byte_cntr_irq(int irq, void *data)
  1210. {
  1211. struct tmc_drvdata *drvdata = data;
  1212. atomic_inc(&drvdata->byte_cntr_irq_cnt);
  1213. if (atomic_read(&drvdata->byte_cntr_irq_cnt) >
  1214. drvdata->byte_cntr_overflow_cnt) {
  1215. dev_err(drvdata->dev, "Byte counter overflow\n");
  1216. drvdata->byte_cntr_overflow = true;
  1217. }
  1218. wake_up(&drvdata->wq);
  1219. return IRQ_HANDLED;
  1220. }
  1221. static int tmc_etr_byte_cntr_dev_register(struct tmc_drvdata *drvdata)
  1222. {
  1223. int ret;
  1224. struct device *device;
  1225. dev_t dev;
  1226. ret = alloc_chrdev_region(&dev, 0, 1, drvdata->byte_cntr_node);
  1227. if (ret)
  1228. goto err0;
  1229. cdev_init(&drvdata->byte_cntr_dev, &byte_cntr_fops);
  1230. drvdata->byte_cntr_dev.owner = THIS_MODULE;
  1231. drvdata->byte_cntr_dev.ops = &byte_cntr_fops;
  1232. ret = cdev_add(&drvdata->byte_cntr_dev, dev, 1);
  1233. if (ret)
  1234. goto err1;
  1235. drvdata->byte_cntr_class = class_create(THIS_MODULE,
  1236. drvdata->byte_cntr_node);
  1237. if (IS_ERR(drvdata->byte_cntr_class)) {
  1238. ret = PTR_ERR(drvdata->byte_cntr_class);
  1239. goto err2;
  1240. }
  1241. device = device_create(drvdata->byte_cntr_class, NULL,
  1242. drvdata->byte_cntr_dev.dev, drvdata,
  1243. drvdata->byte_cntr_node);
  1244. if (IS_ERR(device)) {
  1245. ret = PTR_ERR(device);
  1246. goto err3;
  1247. }
  1248. return 0;
  1249. err3:
  1250. class_destroy(drvdata->byte_cntr_class);
  1251. err2:
  1252. cdev_del(&drvdata->byte_cntr_dev);
  1253. err1:
  1254. unregister_chrdev_region(drvdata->byte_cntr_dev.dev, 1);
  1255. err0:
  1256. return ret;
  1257. }
  1258. static void tmc_etr_byte_cntr_dev_deregister(struct tmc_drvdata *drvdata)
  1259. {
  1260. device_destroy(drvdata->byte_cntr_class, drvdata->byte_cntr_dev.dev);
  1261. class_destroy(drvdata->byte_cntr_class);
  1262. cdev_del(&drvdata->byte_cntr_dev);
  1263. unregister_chrdev_region(drvdata->byte_cntr_dev.dev, 1);
  1264. }
  1265. static int tmc_etr_byte_cntr_init(struct platform_device *pdev,
  1266. struct tmc_drvdata *drvdata)
  1267. {
  1268. int ret = 0;
  1269. size_t node_size = strlen("-stream") + 1;
  1270. char *node_name = (char *)((struct coresight_platform_data *)
  1271. (pdev->dev.platform_data))->name;
  1272. if (!drvdata->byte_cntr_present) {
  1273. dev_info(&pdev->dev, "Byte Counter feature absent\n");
  1274. goto out;
  1275. }
  1276. drvdata->byte_cntr_irq = platform_get_irq_byname(pdev,
  1277. "byte-cntr-irq");
  1278. if (drvdata->byte_cntr_irq < 0) {
  1279. /* Even though this is an error condition, we do not fail
  1280. * the probe as the byte counter feature is optional
  1281. */
  1282. dev_err(&pdev->dev, "Byte-cntr-irq not specified\n");
  1283. goto err;
  1284. }
  1285. init_waitqueue_head(&drvdata->wq);
  1286. ret = devm_request_irq(&pdev->dev, drvdata->byte_cntr_irq,
  1287. tmc_etr_byte_cntr_irq,
  1288. IRQF_TRIGGER_RISING | IRQF_SHARED,
  1289. node_name, drvdata);
  1290. if (ret) {
  1291. dev_err(&pdev->dev, "Request irq failed\n");
  1292. goto err;
  1293. }
  1294. node_size += strlen(node_name);
  1295. drvdata->byte_cntr_node = devm_kzalloc(&pdev->dev,
  1296. node_size, GFP_KERNEL);
  1297. if (!drvdata->byte_cntr_node) {
  1298. dev_err(&pdev->dev, "Byte cntr node name allocation failed\n");
  1299. ret = -ENOMEM;
  1300. goto err;
  1301. }
  1302. strlcpy(drvdata->byte_cntr_node, node_name, node_size);
  1303. strlcat(drvdata->byte_cntr_node, "-stream", node_size);
  1304. ret = tmc_etr_byte_cntr_dev_register(drvdata);
  1305. if (ret) {
  1306. dev_err(&pdev->dev, "Byte cntr node not registered\n");
  1307. goto err;
  1308. }
  1309. dev_info(&pdev->dev, "Byte Counter feature enabled\n");
  1310. return 0;
  1311. err:
  1312. drvdata->byte_cntr_present = false;
  1313. out:
  1314. return ret;
  1315. }
  1316. static void tmc_etr_byte_cntr_exit(struct tmc_drvdata *drvdata)
  1317. {
  1318. if (drvdata->byte_cntr_present)
  1319. tmc_etr_byte_cntr_dev_deregister(drvdata);
  1320. }
  1321. static int __devinit tmc_probe(struct platform_device *pdev)
  1322. {
  1323. int ret;
  1324. uint32_t devid;
  1325. struct device *dev = &pdev->dev;
  1326. struct coresight_platform_data *pdata;
  1327. struct tmc_drvdata *drvdata;
  1328. struct resource *res;
  1329. uint32_t reg_size;
  1330. static int etfetb_count;
  1331. static int count;
  1332. void *baddr;
  1333. struct msm_client_dump dump;
  1334. struct coresight_cti_data *ctidata;
  1335. struct coresight_desc *desc;
  1336. if (coresight_fuse_access_disabled())
  1337. return -EPERM;
  1338. if (pdev->dev.of_node) {
  1339. pdata = of_get_coresight_platform_data(dev, pdev->dev.of_node);
  1340. if (IS_ERR(pdata))
  1341. return PTR_ERR(pdata);
  1342. pdev->dev.platform_data = pdata;
  1343. }
  1344. drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
  1345. if (!drvdata)
  1346. return -ENOMEM;
  1347. drvdata->dev = &pdev->dev;
  1348. platform_set_drvdata(pdev, drvdata);
  1349. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tmc-base");
  1350. if (!res)
  1351. return -ENODEV;
  1352. reg_size = resource_size(res);
  1353. drvdata->base = devm_ioremap(dev, res->start, resource_size(res));
  1354. if (!drvdata->base)
  1355. return -ENOMEM;
  1356. spin_lock_init(&drvdata->spinlock);
  1357. mutex_init(&drvdata->read_lock);
  1358. mutex_init(&drvdata->usb_lock);
  1359. mutex_init(&drvdata->byte_cntr_lock);
  1360. mutex_init(&drvdata->byte_cntr_read_lock);
  1361. atomic_set(&drvdata->byte_cntr_irq_cnt, 0);
  1362. drvdata->clk = devm_clk_get(dev, "core_clk");
  1363. if (IS_ERR(drvdata->clk))
  1364. return PTR_ERR(drvdata->clk);
  1365. ret = clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_TRACE);
  1366. if (ret)
  1367. return ret;
  1368. ret = clk_prepare_enable(drvdata->clk);
  1369. if (ret)
  1370. return ret;
  1371. devid = tmc_readl(drvdata, CORESIGHT_DEVID);
  1372. drvdata->config_type = BMVAL(devid, 6, 7);
  1373. if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
  1374. if (pdev->dev.of_node) {
  1375. ret = of_property_read_u32(pdev->dev.of_node,
  1376. "qcom,memory-size",
  1377. &drvdata->size);
  1378. if (ret) {
  1379. clk_disable_unprepare(drvdata->clk);
  1380. return ret;
  1381. }
  1382. }
  1383. } else {
  1384. drvdata->size = tmc_readl(drvdata, TMC_RSZ) * BYTES_PER_WORD;
  1385. }
  1386. clk_disable_unprepare(drvdata->clk);
  1387. if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
  1388. drvdata->vaddr = dma_zalloc_coherent(&pdev->dev, drvdata->size,
  1389. &drvdata->paddr,
  1390. GFP_KERNEL);
  1391. if (!drvdata->vaddr)
  1392. return -ENOMEM;
  1393. drvdata->buf = drvdata->vaddr;
  1394. drvdata->out_mode = TMC_ETR_OUT_MODE_MEM;
  1395. if (pdev->dev.of_node)
  1396. drvdata->byte_cntr_present = !of_property_read_bool
  1397. (pdev->dev.of_node,
  1398. "qcom,byte-cntr-absent");
  1399. ret = tmc_etr_byte_cntr_init(pdev, drvdata);
  1400. if (ret)
  1401. goto err0;
  1402. ret = tmc_etr_bam_init(pdev, drvdata);
  1403. if (ret)
  1404. goto err1;
  1405. } else {
  1406. baddr = devm_kzalloc(dev, PAGE_SIZE + drvdata->size,
  1407. GFP_KERNEL);
  1408. if (!baddr)
  1409. return -ENOMEM;
  1410. drvdata->buf = baddr + PAGE_SIZE;
  1411. *(uint32_t *)(baddr + TMC_ETFETB_DUMP_VER_OFF) =
  1412. TMC_ETFETB_DUMP_VER;
  1413. dump.id = MSM_TMC_ETFETB + etfetb_count;
  1414. dump.start_addr = virt_to_phys(baddr);
  1415. dump.end_addr = dump.start_addr + PAGE_SIZE + drvdata->size;
  1416. ret = msm_dump_table_register(&dump);
  1417. /*
  1418. * Don't free the buffer in case of error since it can still
  1419. * be used to provide dump collection via the device node or
  1420. * as part of abort.
  1421. */
  1422. if (ret)
  1423. dev_info(dev, "TMC ETF-ETB dump setup failed\n");
  1424. etfetb_count++;
  1425. }
  1426. baddr = devm_kzalloc(dev, PAGE_SIZE + reg_size, GFP_KERNEL);
  1427. if (baddr) {
  1428. drvdata->reg_buf = baddr + PAGE_SIZE;
  1429. *(uint32_t *)(baddr + TMC_REG_DUMP_VER_OFF) = TMC_REG_DUMP_VER;
  1430. dump.id = MSM_TMC0_REG + count;
  1431. dump.start_addr = virt_to_phys(baddr);
  1432. dump.end_addr = dump.start_addr + PAGE_SIZE + reg_size;
  1433. ret = msm_dump_table_register(&dump);
  1434. /*
  1435. * Don't free the buffer in case of error since it can still
  1436. * be used to dump registers as part of abort to aid post crash
  1437. * parsing.
  1438. */
  1439. if (ret)
  1440. dev_info(dev, "TMC REG dump setup failed\n");
  1441. } else {
  1442. dev_info(dev, "TMC REG dump space allocation failed\n");
  1443. }
  1444. count++;
  1445. if (pdev->dev.of_node) {
  1446. drvdata->reset_flush_race = of_property_read_bool(
  1447. pdev->dev.of_node,
  1448. "qcom,reset-flush-race");
  1449. ctidata = of_get_coresight_cti_data(dev, pdev->dev.of_node);
  1450. if (IS_ERR(ctidata)) {
  1451. dev_err(dev, "invalid cti data\n");
  1452. } else if (ctidata && ctidata->nr_ctis == 2) {
  1453. drvdata->cti_flush = coresight_cti_get(
  1454. ctidata->names[0]);
  1455. if (IS_ERR(drvdata->cti_flush))
  1456. dev_err(dev, "failed to get flush cti\n");
  1457. drvdata->cti_reset = coresight_cti_get(
  1458. ctidata->names[1]);
  1459. if (IS_ERR(drvdata->cti_reset))
  1460. dev_err(dev, "failed to get reset cti\n");
  1461. }
  1462. }
  1463. desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
  1464. if (!desc) {
  1465. ret = -ENOMEM;
  1466. goto err2;
  1467. }
  1468. if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
  1469. desc->type = CORESIGHT_DEV_TYPE_SINK;
  1470. desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
  1471. desc->ops = &tmc_etb_cs_ops;
  1472. desc->pdata = pdev->dev.platform_data;
  1473. desc->dev = &pdev->dev;
  1474. desc->groups = tmc_etb_attr_grps;
  1475. desc->owner = THIS_MODULE;
  1476. drvdata->csdev = coresight_register(desc);
  1477. if (IS_ERR(drvdata->csdev)) {
  1478. ret = PTR_ERR(drvdata->csdev);
  1479. goto err2;
  1480. }
  1481. } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
  1482. desc->type = CORESIGHT_DEV_TYPE_SINK;
  1483. desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
  1484. desc->ops = &tmc_etr_cs_ops;
  1485. desc->pdata = pdev->dev.platform_data;
  1486. desc->dev = &pdev->dev;
  1487. desc->groups = tmc_etr_attr_grps;
  1488. desc->owner = THIS_MODULE;
  1489. drvdata->csdev = coresight_register(desc);
  1490. if (IS_ERR(drvdata->csdev)) {
  1491. ret = PTR_ERR(drvdata->csdev);
  1492. goto err2;
  1493. }
  1494. } else {
  1495. desc->type = CORESIGHT_DEV_TYPE_LINKSINK;
  1496. desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
  1497. desc->subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
  1498. desc->ops = &tmc_etf_cs_ops;
  1499. desc->pdata = pdev->dev.platform_data;
  1500. desc->dev = &pdev->dev;
  1501. desc->groups = tmc_etf_attr_grps;
  1502. desc->owner = THIS_MODULE;
  1503. drvdata->csdev = coresight_register(desc);
  1504. if (IS_ERR(drvdata->csdev)) {
  1505. ret = PTR_ERR(drvdata->csdev);
  1506. goto err2;
  1507. }
  1508. }
  1509. drvdata->miscdev.name = ((struct coresight_platform_data *)
  1510. (pdev->dev.platform_data))->name;
  1511. drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
  1512. drvdata->miscdev.fops = &tmc_fops;
  1513. ret = misc_register(&drvdata->miscdev);
  1514. if (ret)
  1515. goto err3;
  1516. dev_info(dev, "TMC initialized\n");
  1517. return 0;
  1518. err3:
  1519. coresight_unregister(drvdata->csdev);
  1520. err2:
  1521. tmc_etr_bam_exit(drvdata);
  1522. err1:
  1523. tmc_etr_byte_cntr_exit(drvdata);
  1524. err0:
  1525. if (drvdata->vaddr)
  1526. dma_free_coherent(&pdev->dev, drvdata->size,
  1527. drvdata->vaddr,
  1528. drvdata->paddr);
  1529. return ret;
  1530. }
  1531. static int __devexit tmc_remove(struct platform_device *pdev)
  1532. {
  1533. struct tmc_drvdata *drvdata = platform_get_drvdata(pdev);
  1534. tmc_etr_byte_cntr_exit(drvdata);
  1535. misc_deregister(&drvdata->miscdev);
  1536. coresight_unregister(drvdata->csdev);
  1537. tmc_etr_bam_exit(drvdata);
  1538. if (drvdata->vaddr)
  1539. dma_free_coherent(&pdev->dev, drvdata->size, drvdata->vaddr,
  1540. drvdata->paddr);
  1541. return 0;
  1542. }
  1543. static struct of_device_id tmc_match[] = {
  1544. {.compatible = "arm,coresight-tmc"},
  1545. {}
  1546. };
  1547. EXPORT_COMPAT("arm,coresight-tmc");
  1548. static struct platform_driver tmc_driver = {
  1549. .probe = tmc_probe,
  1550. .remove = __devexit_p(tmc_remove),
  1551. .driver = {
  1552. .name = "coresight-tmc",
  1553. .owner = THIS_MODULE,
  1554. .of_match_table = tmc_match,
  1555. },
  1556. };
  1557. static int __init tmc_init(void)
  1558. {
  1559. return platform_driver_register(&tmc_driver);
  1560. }
  1561. module_init(tmc_init);
  1562. static void __exit tmc_exit(void)
  1563. {
  1564. platform_driver_unregister(&tmc_driver);
  1565. }
  1566. module_exit(tmc_exit);
  1567. MODULE_LICENSE("GPL v2");
  1568. MODULE_DESCRIPTION("CoreSight Trace Memory Controller driver");