time.c 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100
  1. /*
  2. * arch/score/kernel/time.c
  3. *
  4. * Score Processor version.
  5. *
  6. * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
  7. * Chen Liqin <liqin.chen@sunplusct.com>
  8. * Lennox Wu <lennox.wu@sunplusct.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, see the file COPYING, or write
  22. * to the Free Software Foundation, Inc.,
  23. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  24. */
  25. #include <linux/clockchips.h>
  26. #include <linux/interrupt.h>
  27. #include <asm/scoreregs.h>
  28. static irqreturn_t timer_interrupt(int irq, void *dev_id)
  29. {
  30. struct clock_event_device *evdev = dev_id;
  31. /* clear timer interrupt flag */
  32. outl(1, P_TIMER0_CPP_REG);
  33. evdev->event_handler(evdev);
  34. return IRQ_HANDLED;
  35. }
  36. static struct irqaction timer_irq = {
  37. .handler = timer_interrupt,
  38. .flags = IRQF_DISABLED | IRQF_TIMER,
  39. .name = "timer",
  40. };
  41. static int score_timer_set_next_event(unsigned long delta,
  42. struct clock_event_device *evdev)
  43. {
  44. outl((TMR_M_PERIODIC | TMR_IE_ENABLE), P_TIMER0_CTRL);
  45. outl(delta, P_TIMER0_PRELOAD);
  46. outl(inl(P_TIMER0_CTRL) | TMR_ENABLE, P_TIMER0_CTRL);
  47. return 0;
  48. }
  49. static void score_timer_set_mode(enum clock_event_mode mode,
  50. struct clock_event_device *evdev)
  51. {
  52. switch (mode) {
  53. case CLOCK_EVT_MODE_PERIODIC:
  54. outl((TMR_M_PERIODIC | TMR_IE_ENABLE), P_TIMER0_CTRL);
  55. outl(SYSTEM_CLOCK/HZ, P_TIMER0_PRELOAD);
  56. outl(inl(P_TIMER0_CTRL) | TMR_ENABLE, P_TIMER0_CTRL);
  57. break;
  58. case CLOCK_EVT_MODE_ONESHOT:
  59. case CLOCK_EVT_MODE_SHUTDOWN:
  60. case CLOCK_EVT_MODE_RESUME:
  61. case CLOCK_EVT_MODE_UNUSED:
  62. break;
  63. default:
  64. BUG();
  65. }
  66. }
  67. static struct clock_event_device score_clockevent = {
  68. .name = "score_clockevent",
  69. .features = CLOCK_EVT_FEAT_PERIODIC,
  70. .shift = 16,
  71. .set_next_event = score_timer_set_next_event,
  72. .set_mode = score_timer_set_mode,
  73. };
  74. void __init time_init(void)
  75. {
  76. timer_irq.dev_id = &score_clockevent;
  77. setup_irq(IRQ_TIMER , &timer_irq);
  78. /* setup COMPARE clockevent */
  79. score_clockevent.mult = div_sc(SYSTEM_CLOCK, NSEC_PER_SEC,
  80. score_clockevent.shift);
  81. score_clockevent.max_delta_ns = clockevent_delta2ns((u32)~0,
  82. &score_clockevent);
  83. score_clockevent.min_delta_ns = clockevent_delta2ns(50,
  84. &score_clockevent) + 1;
  85. score_clockevent.cpumask = cpumask_of(0);
  86. clockevents_register_device(&score_clockevent);
  87. }