attach.c 9.9 KB

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  1. /*
  2. * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
  3. * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
  4. *
  5. * Permission to use, copy, modify, and distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. *
  17. */
  18. /*************************************\
  19. * Attach/Detach Functions and helpers *
  20. \*************************************/
  21. #include <linux/pci.h>
  22. #include <linux/slab.h>
  23. #include "ath5k.h"
  24. #include "reg.h"
  25. #include "debug.h"
  26. /**
  27. * ath5k_hw_post() - Power On Self Test helper function
  28. * @ah: The &struct ath5k_hw
  29. */
  30. static int ath5k_hw_post(struct ath5k_hw *ah)
  31. {
  32. static const u32 static_pattern[4] = {
  33. 0x55555555, 0xaaaaaaaa,
  34. 0x66666666, 0x99999999
  35. };
  36. static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
  37. int i, c;
  38. u16 cur_reg;
  39. u32 var_pattern;
  40. u32 init_val;
  41. u32 cur_val;
  42. for (c = 0; c < 2; c++) {
  43. cur_reg = regs[c];
  44. /* Save previous value */
  45. init_val = ath5k_hw_reg_read(ah, cur_reg);
  46. for (i = 0; i < 256; i++) {
  47. var_pattern = i << 16 | i;
  48. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  49. cur_val = ath5k_hw_reg_read(ah, cur_reg);
  50. if (cur_val != var_pattern) {
  51. ATH5K_ERR(ah, "POST Failed !!!\n");
  52. return -EAGAIN;
  53. }
  54. /* Found on ndiswrapper dumps */
  55. var_pattern = 0x0039080f;
  56. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  57. }
  58. for (i = 0; i < 4; i++) {
  59. var_pattern = static_pattern[i];
  60. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  61. cur_val = ath5k_hw_reg_read(ah, cur_reg);
  62. if (cur_val != var_pattern) {
  63. ATH5K_ERR(ah, "POST Failed !!!\n");
  64. return -EAGAIN;
  65. }
  66. /* Found on ndiswrapper dumps */
  67. var_pattern = 0x003b080f;
  68. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  69. }
  70. /* Restore previous value */
  71. ath5k_hw_reg_write(ah, init_val, cur_reg);
  72. }
  73. return 0;
  74. }
  75. /**
  76. * ath5k_hw_init() - Check if hw is supported and init the needed structs
  77. * @ah: The &struct ath5k_hw associated with the device
  78. *
  79. * Check if the device is supported, perform a POST and initialize the needed
  80. * structs. Returns -ENOMEM if we don't have memory for the needed structs,
  81. * -ENODEV if the device is not supported or prints an error msg if something
  82. * else went wrong.
  83. */
  84. int ath5k_hw_init(struct ath5k_hw *ah)
  85. {
  86. static const u8 zero_mac[ETH_ALEN] = { };
  87. struct ath_common *common = ath5k_hw_common(ah);
  88. struct pci_dev *pdev = ah->pdev;
  89. struct ath5k_eeprom_info *ee;
  90. int ret;
  91. u32 srev;
  92. /*
  93. * HW information
  94. */
  95. ah->ah_bwmode = AR5K_BWMODE_DEFAULT;
  96. ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
  97. ah->ah_imr = 0;
  98. ah->ah_retry_short = AR5K_INIT_RETRY_SHORT;
  99. ah->ah_retry_long = AR5K_INIT_RETRY_LONG;
  100. ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT;
  101. ah->ah_noise_floor = -95; /* until first NF calibration is run */
  102. ah->ani_state.ani_mode = ATH5K_ANI_MODE_AUTO;
  103. ah->ah_current_channel = &ah->channels[0];
  104. /*
  105. * Find the mac version
  106. */
  107. ath5k_hw_read_srev(ah);
  108. srev = ah->ah_mac_srev;
  109. if (srev < AR5K_SREV_AR5311)
  110. ah->ah_version = AR5K_AR5210;
  111. else if (srev < AR5K_SREV_AR5212)
  112. ah->ah_version = AR5K_AR5211;
  113. else
  114. ah->ah_version = AR5K_AR5212;
  115. /* Get the MAC version */
  116. ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
  117. /* Fill the ath5k_hw struct with the needed functions */
  118. ret = ath5k_hw_init_desc_functions(ah);
  119. if (ret)
  120. goto err;
  121. /* Bring device out of sleep and reset its units */
  122. ret = ath5k_hw_nic_wakeup(ah, NULL);
  123. if (ret)
  124. goto err;
  125. /* Get PHY and RADIO revisions */
  126. ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
  127. 0xffffffff;
  128. ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
  129. IEEE80211_BAND_5GHZ);
  130. /* Try to identify radio chip based on its srev */
  131. switch (ah->ah_radio_5ghz_revision & 0xf0) {
  132. case AR5K_SREV_RAD_5111:
  133. ah->ah_radio = AR5K_RF5111;
  134. ah->ah_single_chip = false;
  135. ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
  136. IEEE80211_BAND_2GHZ);
  137. break;
  138. case AR5K_SREV_RAD_5112:
  139. case AR5K_SREV_RAD_2112:
  140. ah->ah_radio = AR5K_RF5112;
  141. ah->ah_single_chip = false;
  142. ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
  143. IEEE80211_BAND_2GHZ);
  144. break;
  145. case AR5K_SREV_RAD_2413:
  146. ah->ah_radio = AR5K_RF2413;
  147. ah->ah_single_chip = true;
  148. break;
  149. case AR5K_SREV_RAD_5413:
  150. ah->ah_radio = AR5K_RF5413;
  151. ah->ah_single_chip = true;
  152. break;
  153. case AR5K_SREV_RAD_2316:
  154. ah->ah_radio = AR5K_RF2316;
  155. ah->ah_single_chip = true;
  156. break;
  157. case AR5K_SREV_RAD_2317:
  158. ah->ah_radio = AR5K_RF2317;
  159. ah->ah_single_chip = true;
  160. break;
  161. case AR5K_SREV_RAD_5424:
  162. if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
  163. ah->ah_mac_version == AR5K_SREV_AR2417) {
  164. ah->ah_radio = AR5K_RF2425;
  165. ah->ah_single_chip = true;
  166. } else {
  167. ah->ah_radio = AR5K_RF5413;
  168. ah->ah_single_chip = true;
  169. }
  170. break;
  171. default:
  172. /* Identify radio based on mac/phy srev */
  173. if (ah->ah_version == AR5K_AR5210) {
  174. ah->ah_radio = AR5K_RF5110;
  175. ah->ah_single_chip = false;
  176. } else if (ah->ah_version == AR5K_AR5211) {
  177. ah->ah_radio = AR5K_RF5111;
  178. ah->ah_single_chip = false;
  179. ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
  180. IEEE80211_BAND_2GHZ);
  181. } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
  182. ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
  183. ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
  184. ah->ah_radio = AR5K_RF2425;
  185. ah->ah_single_chip = true;
  186. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
  187. } else if (srev == AR5K_SREV_AR5213A &&
  188. ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
  189. ah->ah_radio = AR5K_RF5112;
  190. ah->ah_single_chip = false;
  191. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
  192. } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4) ||
  193. ah->ah_mac_version == (AR5K_SREV_AR2315_R6 >> 4)) {
  194. ah->ah_radio = AR5K_RF2316;
  195. ah->ah_single_chip = true;
  196. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
  197. } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
  198. ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
  199. ah->ah_radio = AR5K_RF5413;
  200. ah->ah_single_chip = true;
  201. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
  202. } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
  203. ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
  204. ah->ah_radio = AR5K_RF2413;
  205. ah->ah_single_chip = true;
  206. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
  207. } else {
  208. ATH5K_ERR(ah, "Couldn't identify radio revision.\n");
  209. ret = -ENODEV;
  210. goto err;
  211. }
  212. }
  213. /* Return on unsupported chips (unsupported eeprom etc) */
  214. if ((srev >= AR5K_SREV_AR5416) && (srev < AR5K_SREV_AR2425)) {
  215. ATH5K_ERR(ah, "Device not yet supported.\n");
  216. ret = -ENODEV;
  217. goto err;
  218. }
  219. /*
  220. * POST
  221. */
  222. ret = ath5k_hw_post(ah);
  223. if (ret)
  224. goto err;
  225. /* Enable pci core retry fix on Hainan (5213A) and later chips */
  226. if (srev >= AR5K_SREV_AR5213A)
  227. AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX);
  228. /*
  229. * Get card capabilities, calibration values etc
  230. * TODO: EEPROM work
  231. */
  232. ret = ath5k_eeprom_init(ah);
  233. if (ret) {
  234. ATH5K_ERR(ah, "unable to init EEPROM\n");
  235. goto err;
  236. }
  237. ee = &ah->ah_capabilities.cap_eeprom;
  238. /*
  239. * Write PCI-E power save settings
  240. */
  241. if ((ah->ah_version == AR5K_AR5212) && pdev && (pci_is_pcie(pdev))) {
  242. ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
  243. ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
  244. /* Shut off RX when elecidle is asserted */
  245. ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
  246. ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
  247. /* If serdes programming is enabled, increase PCI-E
  248. * tx power for systems with long trace from host
  249. * to minicard connector. */
  250. if (ee->ee_serdes)
  251. ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
  252. else
  253. ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);
  254. /* Shut off PLL and CLKREQ active in L1 */
  255. ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
  256. /* Preserve other settings */
  257. ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
  258. ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
  259. ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
  260. /* Reset SERDES to load new settings */
  261. ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
  262. usleep_range(1000, 1500);
  263. }
  264. /* Get misc capabilities */
  265. ret = ath5k_hw_set_capabilities(ah);
  266. if (ret) {
  267. ATH5K_ERR(ah, "unable to get device capabilities\n");
  268. goto err;
  269. }
  270. /* Crypto settings */
  271. common->keymax = (ah->ah_version == AR5K_AR5210 ?
  272. AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211);
  273. if (srev >= AR5K_SREV_AR5212_V4 &&
  274. (ee->ee_version < AR5K_EEPROM_VERSION_5_0 ||
  275. !AR5K_EEPROM_AES_DIS(ee->ee_misc5)))
  276. common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
  277. if (srev >= AR5K_SREV_AR2414) {
  278. common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
  279. AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
  280. AR5K_MISC_MODE_COMBINED_MIC);
  281. }
  282. /* MAC address is cleared until add_interface */
  283. ath5k_hw_set_lladdr(ah, zero_mac);
  284. /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
  285. memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN);
  286. ath5k_hw_set_bssid(ah);
  287. ath5k_hw_set_opmode(ah, ah->opmode);
  288. ath5k_hw_rfgain_opt_init(ah);
  289. ath5k_hw_init_nfcal_hist(ah);
  290. /* turn on HW LEDs */
  291. ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);
  292. return 0;
  293. err:
  294. return ret;
  295. }
  296. /**
  297. * ath5k_hw_deinit() - Free the &struct ath5k_hw
  298. * @ah: The &struct ath5k_hw
  299. */
  300. void ath5k_hw_deinit(struct ath5k_hw *ah)
  301. {
  302. __set_bit(ATH_STAT_INVALID, ah->status);
  303. if (ah->ah_rf_banks != NULL)
  304. kfree(ah->ah_rf_banks);
  305. ath5k_eeprom_detach(ah);
  306. /* assume interrupts are down */
  307. }