ath.h 8.1 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef ATH_H
  17. #define ATH_H
  18. #include <linux/skbuff.h>
  19. #include <linux/if_ether.h>
  20. #include <linux/spinlock.h>
  21. #include <net/mac80211.h>
  22. /*
  23. * The key cache is used for h/w cipher state and also for
  24. * tracking station state such as the current tx antenna.
  25. * We also setup a mapping table between key cache slot indices
  26. * and station state to short-circuit node lookups on rx.
  27. * Different parts have different size key caches. We handle
  28. * up to ATH_KEYMAX entries (could dynamically allocate state).
  29. */
  30. #define ATH_KEYMAX 128 /* max key cache size we handle */
  31. static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  32. struct ath_ani {
  33. bool caldone;
  34. unsigned int longcal_timer;
  35. unsigned int shortcal_timer;
  36. unsigned int resetcal_timer;
  37. unsigned int checkani_timer;
  38. struct timer_list timer;
  39. };
  40. struct ath_cycle_counters {
  41. u32 cycles;
  42. u32 rx_busy;
  43. u32 rx_frame;
  44. u32 tx_frame;
  45. };
  46. enum ath_device_state {
  47. ATH_HW_UNAVAILABLE,
  48. ATH_HW_INITIALIZED,
  49. };
  50. enum ath_bus_type {
  51. ATH_PCI,
  52. ATH_AHB,
  53. ATH_USB,
  54. };
  55. struct reg_dmn_pair_mapping {
  56. u16 regDmnEnum;
  57. u16 reg_5ghz_ctl;
  58. u16 reg_2ghz_ctl;
  59. };
  60. struct ath_regulatory {
  61. char alpha2[2];
  62. u16 country_code;
  63. u16 max_power_level;
  64. u16 current_rd;
  65. int16_t power_limit;
  66. struct reg_dmn_pair_mapping *regpair;
  67. };
  68. enum ath_crypt_caps {
  69. ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0),
  70. ATH_CRYPT_CAP_MIC_COMBINED = BIT(1),
  71. };
  72. struct ath_keyval {
  73. u8 kv_type;
  74. u8 kv_pad;
  75. u16 kv_len;
  76. u8 kv_val[16]; /* TK */
  77. u8 kv_mic[8]; /* Michael MIC key */
  78. u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
  79. * supports both MIC keys in the same key cache entry;
  80. * in that case, kv_mic is the RX key) */
  81. };
  82. enum ath_cipher {
  83. ATH_CIPHER_WEP = 0,
  84. ATH_CIPHER_AES_OCB = 1,
  85. ATH_CIPHER_AES_CCM = 2,
  86. ATH_CIPHER_CKIP = 3,
  87. ATH_CIPHER_TKIP = 4,
  88. ATH_CIPHER_CLR = 5,
  89. ATH_CIPHER_MIC = 127
  90. };
  91. /**
  92. * struct ath_ops - Register read/write operations
  93. *
  94. * @read: Register read
  95. * @multi_read: Multiple register read
  96. * @write: Register write
  97. * @enable_write_buffer: Enable multiple register writes
  98. * @write_flush: flush buffered register writes and disable buffering
  99. */
  100. struct ath_ops {
  101. unsigned int (*read)(void *, u32 reg_offset);
  102. void (*multi_read)(void *, u32 *addr, u32 *val, u16 count);
  103. void (*write)(void *, u32 val, u32 reg_offset);
  104. void (*enable_write_buffer)(void *);
  105. void (*write_flush) (void *);
  106. u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
  107. };
  108. struct ath_common;
  109. struct ath_bus_ops;
  110. struct ath_common {
  111. void *ah;
  112. void *priv;
  113. struct ieee80211_hw *hw;
  114. int debug_mask;
  115. enum ath_device_state state;
  116. struct ath_ani ani;
  117. u16 cachelsz;
  118. u16 curaid;
  119. u8 macaddr[ETH_ALEN];
  120. u8 curbssid[ETH_ALEN];
  121. u8 bssidmask[ETH_ALEN];
  122. u32 rx_bufsize;
  123. u32 keymax;
  124. DECLARE_BITMAP(keymap, ATH_KEYMAX);
  125. DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
  126. DECLARE_BITMAP(ccmp_keymap, ATH_KEYMAX);
  127. enum ath_crypt_caps crypt_caps;
  128. unsigned int clockrate;
  129. spinlock_t cc_lock;
  130. struct ath_cycle_counters cc_ani;
  131. struct ath_cycle_counters cc_survey;
  132. struct ath_regulatory regulatory;
  133. struct ath_regulatory reg_world_copy;
  134. const struct ath_ops *ops;
  135. const struct ath_bus_ops *bus_ops;
  136. bool btcoex_enabled;
  137. bool disable_ani;
  138. };
  139. struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
  140. u32 len,
  141. gfp_t gfp_mask);
  142. void ath_hw_setbssidmask(struct ath_common *common);
  143. void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key);
  144. int ath_key_config(struct ath_common *common,
  145. struct ieee80211_vif *vif,
  146. struct ieee80211_sta *sta,
  147. struct ieee80211_key_conf *key);
  148. bool ath_hw_keyreset(struct ath_common *common, u16 entry);
  149. void ath_hw_cycle_counters_update(struct ath_common *common);
  150. int32_t ath_hw_get_listen_time(struct ath_common *common);
  151. __printf(3, 4)
  152. void ath_printk(const char *level, const struct ath_common *common,
  153. const char *fmt, ...);
  154. #define ath_emerg(common, fmt, ...) \
  155. ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
  156. #define ath_alert(common, fmt, ...) \
  157. ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
  158. #define ath_crit(common, fmt, ...) \
  159. ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
  160. #define ath_err(common, fmt, ...) \
  161. ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
  162. #define ath_warn(common, fmt, ...) \
  163. ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
  164. #define ath_notice(common, fmt, ...) \
  165. ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
  166. #define ath_info(common, fmt, ...) \
  167. ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)
  168. /**
  169. * enum ath_debug_level - atheros wireless debug level
  170. *
  171. * @ATH_DBG_RESET: reset processing
  172. * @ATH_DBG_QUEUE: hardware queue management
  173. * @ATH_DBG_EEPROM: eeprom processing
  174. * @ATH_DBG_CALIBRATE: periodic calibration
  175. * @ATH_DBG_INTERRUPT: interrupt processing
  176. * @ATH_DBG_REGULATORY: regulatory processing
  177. * @ATH_DBG_ANI: adaptive noise immunitive processing
  178. * @ATH_DBG_XMIT: basic xmit operation
  179. * @ATH_DBG_BEACON: beacon handling
  180. * @ATH_DBG_CONFIG: configuration of the hardware
  181. * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
  182. * @ATH_DBG_PS: power save processing
  183. * @ATH_DBG_HWTIMER: hardware timer handling
  184. * @ATH_DBG_BTCOEX: bluetooth coexistance
  185. * @ATH_DBG_BSTUCK: stuck beacons
  186. * @ATH_DBG_MCI: Message Coexistence Interface, a private protocol
  187. * used exclusively for WLAN-BT coexistence starting from
  188. * AR9462.
  189. * @ATH_DBG_DFS: radar datection
  190. * @ATH_DBG_ANY: enable all debugging
  191. *
  192. * The debug level is used to control the amount and type of debugging output
  193. * we want to see. Each driver has its own method for enabling debugging and
  194. * modifying debug level states -- but this is typically done through a
  195. * module parameter 'debug' along with a respective 'debug' debugfs file
  196. * entry.
  197. */
  198. enum ATH_DEBUG {
  199. ATH_DBG_RESET = 0x00000001,
  200. ATH_DBG_QUEUE = 0x00000002,
  201. ATH_DBG_EEPROM = 0x00000004,
  202. ATH_DBG_CALIBRATE = 0x00000008,
  203. ATH_DBG_INTERRUPT = 0x00000010,
  204. ATH_DBG_REGULATORY = 0x00000020,
  205. ATH_DBG_ANI = 0x00000040,
  206. ATH_DBG_XMIT = 0x00000080,
  207. ATH_DBG_BEACON = 0x00000100,
  208. ATH_DBG_CONFIG = 0x00000200,
  209. ATH_DBG_FATAL = 0x00000400,
  210. ATH_DBG_PS = 0x00000800,
  211. ATH_DBG_HWTIMER = 0x00001000,
  212. ATH_DBG_BTCOEX = 0x00002000,
  213. ATH_DBG_WMI = 0x00004000,
  214. ATH_DBG_BSTUCK = 0x00008000,
  215. ATH_DBG_MCI = 0x00010000,
  216. ATH_DBG_DFS = 0x00020000,
  217. ATH_DBG_ANY = 0xffffffff
  218. };
  219. #define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
  220. #ifdef CONFIG_ATH_DEBUG
  221. #define ath_dbg(common, dbg_mask, fmt, ...) \
  222. do { \
  223. if ((common)->debug_mask & ATH_DBG_##dbg_mask) \
  224. ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__); \
  225. } while (0)
  226. #define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
  227. #define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)
  228. #else
  229. static inline __attribute__ ((format (printf, 3, 4)))
  230. void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
  231. const char *fmt, ...)
  232. {
  233. }
  234. #define ath_dbg(common, dbg_mask, fmt, ...) \
  235. _ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__)
  236. #define ATH_DBG_WARN(foo, arg...) do {} while (0)
  237. #define ATH_DBG_WARN_ON_ONCE(foo) ({ \
  238. int __ret_warn_once = !!(foo); \
  239. unlikely(__ret_warn_once); \
  240. })
  241. #endif /* CONFIG_ATH_DEBUG */
  242. /** Returns string describing opmode, or NULL if unknown mode. */
  243. #ifdef CONFIG_ATH_DEBUG
  244. const char *ath_opmode_to_string(enum nl80211_iftype opmode);
  245. #else
  246. static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
  247. {
  248. return "UNKNOWN";
  249. }
  250. #endif
  251. #endif /* ATH_H */