wcd9310.c 288 KB

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  1. /* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/init.h>
  14. #include <linux/firmware.h>
  15. #include <linux/slab.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/device.h>
  18. #include <linux/printk.h>
  19. #include <linux/ratelimit.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/wait.h>
  22. #include <linux/mfd/wcd9xxx/core.h>
  23. #include <linux/mfd/wcd9xxx/wcd9xxx_registers.h>
  24. #include <linux/mfd/wcd9xxx/wcd9310_registers.h>
  25. #include <linux/mfd/wcd9xxx/pdata.h>
  26. #include <sound/pcm.h>
  27. #include <sound/pcm_params.h>
  28. #include <sound/soc.h>
  29. #include <sound/soc-dapm.h>
  30. #include <sound/tlv.h>
  31. #include <linux/bitops.h>
  32. #include <linux/delay.h>
  33. #include <linux/pm_runtime.h>
  34. #include <linux/kernel.h>
  35. #include <linux/gpio.h>
  36. #include <linux/irq.h>
  37. #include <linux/wakelock.h>
  38. #include <linux/suspend.h>
  39. #include "wcd9310.h"
  40. static int cfilt_adjust_ms = 10;
  41. module_param(cfilt_adjust_ms, int, 0644);
  42. MODULE_PARM_DESC(cfilt_adjust_ms, "delay after adjusting cfilt voltage in ms");
  43. #define WCD9310_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  44. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  45. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  46. #define NUM_DECIMATORS 10
  47. #define NUM_INTERPOLATORS 7
  48. #define BITS_PER_REG 8
  49. #define TABLA_CFILT_FAST_MODE 0x00
  50. #define TABLA_CFILT_SLOW_MODE 0x40
  51. #define MBHC_FW_READ_ATTEMPTS 15
  52. #define MBHC_FW_READ_TIMEOUT 2000000
  53. #define MBHC_VDDIO_SWITCH_WAIT_MS 10
  54. #define COMP_DIGITAL_DB_GAIN_APPLY(a, b) \
  55. (((a) <= 0) ? ((a) - b) : (a))
  56. #define SLIM_CLOSE_TIMEOUT 1000
  57. /* The wait time value comes from codec HW specification */
  58. #define COMP_BRINGUP_WAIT_TIME 2000
  59. enum {
  60. MBHC_USE_HPHL_TRIGGER = 1,
  61. MBHC_USE_MB_TRIGGER = 2
  62. };
  63. #define MBHC_NUM_DCE_PLUG_DETECT 3
  64. #define NUM_ATTEMPTS_INSERT_DETECT 25
  65. #define NUM_ATTEMPTS_TO_REPORT 5
  66. #define TABLA_JACK_MASK (SND_JACK_HEADSET | SND_JACK_OC_HPHL | \
  67. SND_JACK_OC_HPHR | SND_JACK_LINEOUT | \
  68. SND_JACK_UNSUPPORTED)
  69. #define TABLA_I2S_MASTER_MODE_MASK 0x08
  70. #define TABLA_OCP_ATTEMPT 1
  71. enum {
  72. AIF1_PB = 0,
  73. AIF1_CAP,
  74. AIF2_PB,
  75. AIF2_CAP,
  76. AIF3_PB,
  77. AIF3_CAP,
  78. NUM_CODEC_DAIS,
  79. };
  80. enum {
  81. RX_MIX1_INP_SEL_ZERO = 0,
  82. RX_MIX1_INP_SEL_SRC1,
  83. RX_MIX1_INP_SEL_SRC2,
  84. RX_MIX1_INP_SEL_IIR1,
  85. RX_MIX1_INP_SEL_IIR2,
  86. RX_MIX1_INP_SEL_RX1,
  87. RX_MIX1_INP_SEL_RX2,
  88. RX_MIX1_INP_SEL_RX3,
  89. RX_MIX1_INP_SEL_RX4,
  90. RX_MIX1_INP_SEL_RX5,
  91. RX_MIX1_INP_SEL_RX6,
  92. RX_MIX1_INP_SEL_RX7,
  93. };
  94. #define MAX_PA_GAIN_OPTIONS 13
  95. #define TABLA_MCLK_RATE_12288KHZ 12288000
  96. #define TABLA_MCLK_RATE_9600KHZ 9600000
  97. #define TABLA_FAKE_INS_THRESHOLD_MS 2500
  98. #define TABLA_FAKE_REMOVAL_MIN_PERIOD_MS 50
  99. #define TABLA_MBHC_BUTTON_MIN 0x8000
  100. #define TABLA_MBHC_FAKE_INSERT_LOW 10
  101. #define TABLA_MBHC_FAKE_INSERT_HIGH 80
  102. #define TABLA_MBHC_FAKE_INS_HIGH_NO_GPIO 150
  103. #define TABLA_MBHC_STATUS_REL_DETECTION 0x0C
  104. #define TABLA_MBHC_GPIO_REL_DEBOUNCE_TIME_MS 50
  105. #define TABLA_MBHC_FAKE_INS_DELTA_MV 200
  106. #define TABLA_MBHC_FAKE_INS_DELTA_SCALED_MV 300
  107. #define TABLA_HS_DETECT_PLUG_TIME_MS (5 * 1000)
  108. #define TABLA_HS_DETECT_PLUG_INERVAL_MS 100
  109. #define TABLA_GPIO_IRQ_DEBOUNCE_TIME_US 5000
  110. #define TABLA_MBHC_GND_MIC_SWAP_THRESHOLD 2
  111. #define TABLA_RX_PORT_START_NUMBER 10
  112. #define TABLA_ACQUIRE_LOCK(x) do { \
  113. mutex_lock_nested(&x, SINGLE_DEPTH_NESTING); \
  114. } while (0)
  115. #define TABLA_RELEASE_LOCK(x) do { mutex_unlock(&x); } while (0)
  116. static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
  117. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  118. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  119. static struct snd_soc_dai_driver tabla_dai[];
  120. static const DECLARE_TLV_DB_SCALE(aux_pga_gain, 0, 2, 0);
  121. static int tabla_codec_enable_slimrx(struct snd_soc_dapm_widget *w,
  122. struct snd_kcontrol *kcontrol, int event);
  123. static int tabla_codec_enable_slimtx(struct snd_soc_dapm_widget *w,
  124. struct snd_kcontrol *kcontrol, int event);
  125. enum tabla_bandgap_type {
  126. TABLA_BANDGAP_OFF = 0,
  127. TABLA_BANDGAP_AUDIO_MODE,
  128. TABLA_BANDGAP_MBHC_MODE,
  129. };
  130. struct mbhc_micbias_regs {
  131. u16 cfilt_val;
  132. u16 cfilt_ctl;
  133. u16 mbhc_reg;
  134. u16 int_rbias;
  135. u16 ctl_reg;
  136. u8 cfilt_sel;
  137. };
  138. /* Codec supports 2 IIR filters */
  139. enum {
  140. IIR1 = 0,
  141. IIR2,
  142. IIR_MAX,
  143. };
  144. /* Codec supports 5 bands */
  145. enum {
  146. BAND1 = 0,
  147. BAND2,
  148. BAND3,
  149. BAND4,
  150. BAND5,
  151. BAND_MAX,
  152. };
  153. enum {
  154. COMPANDER_1 = 0,
  155. COMPANDER_2,
  156. COMPANDER_MAX,
  157. };
  158. enum {
  159. COMPANDER_FS_8KHZ = 0,
  160. COMPANDER_FS_16KHZ,
  161. COMPANDER_FS_32KHZ,
  162. COMPANDER_FS_48KHZ,
  163. COMPANDER_FS_96KHZ,
  164. COMPANDER_FS_192KHZ,
  165. COMPANDER_FS_MAX,
  166. };
  167. enum {
  168. COMP_SHUTDWN_TIMEOUT_PCM_1 = 0,
  169. COMP_SHUTDWN_TIMEOUT_PCM_240,
  170. COMP_SHUTDWN_TIMEOUT_PCM_480,
  171. COMP_SHUTDWN_TIMEOUT_PCM_960,
  172. COMP_SHUTDWN_TIMEOUT_PCM_1440,
  173. COMP_SHUTDWN_TIMEOUT_PCM_2880,
  174. COMP_SHUTDWN_TIMEOUT_PCM_5760,
  175. };
  176. /* Flags to track of PA and DAC state.
  177. * PA and DAC should be tracked separately as AUXPGA loopback requires
  178. * only PA to be turned on without DAC being on. */
  179. enum tabla_priv_ack_flags {
  180. TABLA_HPHL_PA_OFF_ACK = 0,
  181. TABLA_HPHR_PA_OFF_ACK,
  182. TABLA_HPHL_DAC_OFF_ACK,
  183. TABLA_HPHR_DAC_OFF_ACK
  184. };
  185. struct comp_sample_dependent_params {
  186. u32 peak_det_timeout;
  187. u32 rms_meter_div_fact;
  188. u32 rms_meter_resamp_fact;
  189. u32 shutdown_timeout;
  190. };
  191. struct comp_dgtl_gain_offset {
  192. u8 whole_db_gain;
  193. u8 half_db_gain;
  194. };
  195. static const struct comp_dgtl_gain_offset
  196. comp_dgtl_gain[MAX_PA_GAIN_OPTIONS] = {
  197. {0, 0},
  198. {1, 1},
  199. {3, 0},
  200. {4, 1},
  201. {6, 0},
  202. {7, 1},
  203. {9, 0},
  204. {10, 1},
  205. {12, 0},
  206. {13, 1},
  207. {15, 0},
  208. {16, 1},
  209. {18, 0},
  210. };
  211. /* Data used by MBHC */
  212. struct mbhc_internal_cal_data {
  213. u16 dce_z;
  214. u16 dce_mb;
  215. u16 sta_z;
  216. u16 sta_mb;
  217. u32 t_sta_dce;
  218. u32 t_dce;
  219. u32 t_sta;
  220. u32 micb_mv;
  221. u16 v_ins_hu;
  222. u16 v_ins_h;
  223. u16 v_b1_hu;
  224. u16 v_b1_h;
  225. u16 v_b1_huc;
  226. u16 v_brh;
  227. u16 v_brl;
  228. u16 v_no_mic;
  229. u8 npoll;
  230. u8 nbounce_wait;
  231. s16 adj_v_hs_max;
  232. u16 adj_v_ins_hu;
  233. u16 adj_v_ins_h;
  234. s16 v_inval_ins_low;
  235. s16 v_inval_ins_high;
  236. };
  237. struct tabla_reg_address {
  238. u16 micb_4_ctl;
  239. u16 micb_4_int_rbias;
  240. u16 micb_4_mbhc;
  241. };
  242. enum tabla_mbhc_plug_type {
  243. PLUG_TYPE_INVALID = -1,
  244. PLUG_TYPE_NONE,
  245. PLUG_TYPE_HEADSET,
  246. PLUG_TYPE_HEADPHONE,
  247. PLUG_TYPE_HIGH_HPH,
  248. PLUG_TYPE_GND_MIC_SWAP,
  249. };
  250. enum tabla_mbhc_state {
  251. MBHC_STATE_NONE = -1,
  252. MBHC_STATE_POTENTIAL,
  253. MBHC_STATE_POTENTIAL_RECOVERY,
  254. MBHC_STATE_RELEASE,
  255. };
  256. struct hpf_work {
  257. struct tabla_priv *tabla;
  258. u32 decimator;
  259. u8 tx_hpf_cut_of_freq;
  260. struct delayed_work dwork;
  261. };
  262. static struct hpf_work tx_hpf_work[NUM_DECIMATORS];
  263. struct mute_work {
  264. struct tabla_priv *tabla;
  265. u32 decimator;
  266. struct delayed_work dwork;
  267. };
  268. static struct mute_work tx_mute_work[NUM_DECIMATORS];
  269. static const struct wcd9xxx_ch tabla_rx_chs[TABLA_RX_MAX] = {
  270. WCD9XXX_CH(TABLA_RX_PORT_START_NUMBER, 0),
  271. WCD9XXX_CH(TABLA_RX_PORT_START_NUMBER + 1, 1),
  272. WCD9XXX_CH(TABLA_RX_PORT_START_NUMBER + 2, 2),
  273. WCD9XXX_CH(TABLA_RX_PORT_START_NUMBER + 3, 3),
  274. WCD9XXX_CH(TABLA_RX_PORT_START_NUMBER + 4, 4),
  275. WCD9XXX_CH(TABLA_RX_PORT_START_NUMBER + 5, 5),
  276. WCD9XXX_CH(TABLA_RX_PORT_START_NUMBER + 6, 6)
  277. };
  278. static const struct wcd9xxx_ch tabla_tx_chs[TABLA_TX_MAX] = {
  279. WCD9XXX_CH(0, 0),
  280. WCD9XXX_CH(1, 1),
  281. WCD9XXX_CH(2, 2),
  282. WCD9XXX_CH(3, 3),
  283. WCD9XXX_CH(4, 4),
  284. WCD9XXX_CH(5, 5),
  285. WCD9XXX_CH(6, 6),
  286. WCD9XXX_CH(7, 7),
  287. WCD9XXX_CH(8, 8),
  288. WCD9XXX_CH(9, 9)
  289. };
  290. static const u32 vport_check_table[NUM_CODEC_DAIS] = {
  291. 0, /* AIF1_PB */
  292. (1 << AIF2_CAP) | (1 << AIF3_CAP), /* AIF1_CAP */
  293. 0, /* AIF2_PB */
  294. (1 << AIF1_CAP) | (1 << AIF3_CAP), /* AIF2_CAP */
  295. 0, /* AIF2_PB */
  296. (1 << AIF1_CAP) | (1 << AIF2_CAP), /* AIF2_CAP */
  297. };
  298. static const u32 vport_i2s_check_table[NUM_CODEC_DAIS] = {
  299. 0, /* AIF1_PB */
  300. 0, /* AIF1_CAP */
  301. };
  302. struct tabla_priv {
  303. struct snd_soc_codec *codec;
  304. struct tabla_reg_address reg_addr;
  305. u32 adc_count;
  306. u32 cfilt1_cnt;
  307. u32 cfilt2_cnt;
  308. u32 cfilt3_cnt;
  309. u32 rx_bias_count;
  310. s32 dmic_1_2_clk_cnt;
  311. s32 dmic_3_4_clk_cnt;
  312. s32 dmic_5_6_clk_cnt;
  313. enum tabla_bandgap_type bandgap_type;
  314. bool mclk_enabled;
  315. bool clock_active;
  316. bool config_mode_active;
  317. bool mbhc_polling_active;
  318. unsigned long mbhc_fake_ins_start;
  319. int buttons_pressed;
  320. enum tabla_mbhc_state mbhc_state;
  321. struct tabla_mbhc_config mbhc_cfg;
  322. struct mbhc_internal_cal_data mbhc_data;
  323. u32 ldo_h_count;
  324. u32 micbias_enable_count[TABLA_NUM_MICBIAS];
  325. struct wcd9xxx_pdata *pdata;
  326. u32 anc_slot;
  327. bool anc_func;
  328. bool no_mic_headset_override;
  329. /* Delayed work to report long button press */
  330. struct delayed_work mbhc_btn_dwork;
  331. struct mbhc_micbias_regs mbhc_bias_regs;
  332. bool mbhc_micbias_switched;
  333. /* track PA/DAC state */
  334. unsigned long hph_pa_dac_state;
  335. /*track tabla interface type*/
  336. u8 intf_type;
  337. u32 hph_status; /* track headhpone status */
  338. /* define separate work for left and right headphone OCP to avoid
  339. * additional checking on which OCP event to report so no locking
  340. * to ensure synchronization is required
  341. */
  342. struct work_struct hphlocp_work; /* reporting left hph ocp off */
  343. struct work_struct hphrocp_work; /* reporting right hph ocp off */
  344. u8 hphlocp_cnt; /* headphone left ocp retry */
  345. u8 hphrocp_cnt; /* headphone right ocp retry */
  346. /* Work to perform MBHC Firmware Read */
  347. struct delayed_work mbhc_firmware_dwork;
  348. const struct firmware *mbhc_fw;
  349. /* num of slim ports required */
  350. struct wcd9xxx_codec_dai_data dai[NUM_CODEC_DAIS];
  351. /*compander*/
  352. int comp_enabled[COMPANDER_MAX];
  353. u32 comp_fs[COMPANDER_MAX];
  354. u8 comp_gain_offset[TABLA_SB_PGD_MAX_NUMBER_OF_RX_SLAVE_DEV_PORTS - 1];
  355. /* Maintain the status of AUX PGA */
  356. int aux_pga_cnt;
  357. u8 aux_l_gain;
  358. u8 aux_r_gain;
  359. struct delayed_work mbhc_insert_dwork;
  360. unsigned long mbhc_last_resume; /* in jiffies */
  361. u8 current_plug;
  362. struct work_struct hs_correct_plug_work;
  363. bool hs_detect_work_stop;
  364. bool hs_polling_irq_prepared;
  365. bool lpi_enabled; /* low power insertion detection */
  366. bool in_gpio_handler;
  367. /* Currently, only used for mbhc purpose, to protect
  368. * concurrent execution of mbhc threaded irq handlers and
  369. * kill race between DAPM and MBHC.But can serve as a
  370. * general lock to protect codec resource
  371. */
  372. struct mutex codec_resource_lock;
  373. /* Work to perform polling on microphone voltage
  374. * in order to correct plug type once plug type
  375. * is detected as headphone
  376. */
  377. struct work_struct hs_correct_plug_work_nogpio;
  378. bool gpio_irq_resend;
  379. struct wake_lock irq_resend_wlock;
  380. #ifdef CONFIG_DEBUG_FS
  381. struct dentry *debugfs_poke;
  382. struct dentry *debugfs_mbhc;
  383. #endif
  384. };
  385. static const u32 comp_shift[] = {
  386. 0,
  387. 1,
  388. };
  389. static const int comp_rx_path[] = {
  390. COMPANDER_1,
  391. COMPANDER_1,
  392. COMPANDER_2,
  393. COMPANDER_2,
  394. COMPANDER_2,
  395. COMPANDER_2,
  396. COMPANDER_MAX,
  397. };
  398. static const struct comp_sample_dependent_params
  399. comp_samp_params[COMPANDER_FS_MAX] = {
  400. {
  401. .peak_det_timeout = 0x6,
  402. .rms_meter_div_fact = 0x9 << 4,
  403. .rms_meter_resamp_fact = 0x06,
  404. .shutdown_timeout = COMP_SHUTDWN_TIMEOUT_PCM_240 << 3,
  405. },
  406. {
  407. .peak_det_timeout = 0x7,
  408. .rms_meter_div_fact = 0xA << 4,
  409. .rms_meter_resamp_fact = 0x0C,
  410. .shutdown_timeout = COMP_SHUTDWN_TIMEOUT_PCM_480 << 3,
  411. },
  412. {
  413. .peak_det_timeout = 0x8,
  414. .rms_meter_div_fact = 0xB << 4,
  415. .rms_meter_resamp_fact = 0x30,
  416. .shutdown_timeout = COMP_SHUTDWN_TIMEOUT_PCM_960 << 3,
  417. },
  418. {
  419. .peak_det_timeout = 0x9,
  420. .rms_meter_div_fact = 0xB << 4,
  421. .rms_meter_resamp_fact = 0x28,
  422. .shutdown_timeout = COMP_SHUTDWN_TIMEOUT_PCM_1440 << 3,
  423. },
  424. {
  425. .peak_det_timeout = 0xA,
  426. .rms_meter_div_fact = 0xC << 4,
  427. .rms_meter_resamp_fact = 0x50,
  428. .shutdown_timeout = COMP_SHUTDWN_TIMEOUT_PCM_2880 << 3,
  429. },
  430. {
  431. .peak_det_timeout = 0xB,
  432. .rms_meter_div_fact = 0xC << 4,
  433. .rms_meter_resamp_fact = 0x50,
  434. .shutdown_timeout = COMP_SHUTDWN_TIMEOUT_PCM_5760 << 3,
  435. },
  436. };
  437. static unsigned short rx_digital_gain_reg[] = {
  438. TABLA_A_CDC_RX1_VOL_CTL_B2_CTL,
  439. TABLA_A_CDC_RX2_VOL_CTL_B2_CTL,
  440. TABLA_A_CDC_RX3_VOL_CTL_B2_CTL,
  441. TABLA_A_CDC_RX4_VOL_CTL_B2_CTL,
  442. TABLA_A_CDC_RX5_VOL_CTL_B2_CTL,
  443. TABLA_A_CDC_RX6_VOL_CTL_B2_CTL,
  444. TABLA_A_CDC_RX7_VOL_CTL_B2_CTL,
  445. };
  446. static unsigned short tx_digital_gain_reg[] = {
  447. TABLA_A_CDC_TX1_VOL_CTL_GAIN,
  448. TABLA_A_CDC_TX2_VOL_CTL_GAIN,
  449. TABLA_A_CDC_TX3_VOL_CTL_GAIN,
  450. TABLA_A_CDC_TX4_VOL_CTL_GAIN,
  451. TABLA_A_CDC_TX5_VOL_CTL_GAIN,
  452. TABLA_A_CDC_TX6_VOL_CTL_GAIN,
  453. TABLA_A_CDC_TX7_VOL_CTL_GAIN,
  454. TABLA_A_CDC_TX8_VOL_CTL_GAIN,
  455. TABLA_A_CDC_TX9_VOL_CTL_GAIN,
  456. TABLA_A_CDC_TX10_VOL_CTL_GAIN,
  457. };
  458. static int tabla_codec_enable_charge_pump(struct snd_soc_dapm_widget *w,
  459. struct snd_kcontrol *kcontrol, int event)
  460. {
  461. struct snd_soc_codec *codec = w->codec;
  462. pr_debug("%s %d\n", __func__, event);
  463. switch (event) {
  464. case SND_SOC_DAPM_POST_PMU:
  465. snd_soc_update_bits(codec, TABLA_A_CDC_CLK_OTHR_CTL, 0x01,
  466. 0x01);
  467. snd_soc_update_bits(codec, TABLA_A_CDC_CLSG_CTL, 0x08, 0x08);
  468. usleep_range(200, 200);
  469. snd_soc_update_bits(codec, TABLA_A_CP_STATIC, 0x10, 0x00);
  470. break;
  471. case SND_SOC_DAPM_PRE_PMD:
  472. snd_soc_update_bits(codec, TABLA_A_CDC_CLK_OTHR_RESET_CTL, 0x10,
  473. 0x10);
  474. usleep_range(20, 20);
  475. snd_soc_update_bits(codec, TABLA_A_CP_STATIC, 0x08, 0x08);
  476. snd_soc_update_bits(codec, TABLA_A_CP_STATIC, 0x10, 0x10);
  477. snd_soc_update_bits(codec, TABLA_A_CDC_CLSG_CTL, 0x08, 0x00);
  478. snd_soc_update_bits(codec, TABLA_A_CDC_CLK_OTHR_CTL, 0x01,
  479. 0x00);
  480. snd_soc_update_bits(codec, TABLA_A_CDC_CLK_OTHR_RESET_CTL, 0x10,
  481. 0x00);
  482. snd_soc_update_bits(codec, TABLA_A_CP_STATIC, 0x08, 0x00);
  483. break;
  484. }
  485. return 0;
  486. }
  487. static int tabla_get_anc_slot(struct snd_kcontrol *kcontrol,
  488. struct snd_ctl_elem_value *ucontrol)
  489. {
  490. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  491. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  492. ucontrol->value.integer.value[0] = tabla->anc_slot;
  493. return 0;
  494. }
  495. static int tabla_put_anc_slot(struct snd_kcontrol *kcontrol,
  496. struct snd_ctl_elem_value *ucontrol)
  497. {
  498. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  499. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  500. tabla->anc_slot = ucontrol->value.integer.value[0];
  501. return 0;
  502. }
  503. static int tabla_get_anc_func(struct snd_kcontrol *kcontrol,
  504. struct snd_ctl_elem_value *ucontrol)
  505. {
  506. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  507. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  508. mutex_lock(&codec->dapm.codec->mutex);
  509. ucontrol->value.integer.value[0] = (tabla->anc_func == true ? 1 : 0);
  510. mutex_unlock(&codec->dapm.codec->mutex);
  511. return 0;
  512. }
  513. static int tabla_put_anc_func(struct snd_kcontrol *kcontrol,
  514. struct snd_ctl_elem_value *ucontrol)
  515. {
  516. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  517. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  518. struct snd_soc_dapm_context *dapm = &codec->dapm;
  519. mutex_lock(&dapm->codec->mutex);
  520. tabla->anc_func = (!ucontrol->value.integer.value[0] ? false : true);
  521. dev_dbg(codec->dev, "%s: anc_func %x", __func__, tabla->anc_func);
  522. if (tabla->anc_func == true) {
  523. snd_soc_dapm_enable_pin(dapm, "ANC HPHR");
  524. snd_soc_dapm_enable_pin(dapm, "ANC HPHL");
  525. snd_soc_dapm_enable_pin(dapm, "ANC HEADPHONE");
  526. snd_soc_dapm_disable_pin(dapm, "HPHR");
  527. snd_soc_dapm_disable_pin(dapm, "HPHL");
  528. snd_soc_dapm_disable_pin(dapm, "HEADPHONE");
  529. } else {
  530. snd_soc_dapm_disable_pin(dapm, "ANC HPHR");
  531. snd_soc_dapm_disable_pin(dapm, "ANC HPHL");
  532. snd_soc_dapm_disable_pin(dapm, "ANC HEADPHONE");
  533. snd_soc_dapm_enable_pin(dapm, "HPHR");
  534. snd_soc_dapm_enable_pin(dapm, "HPHL");
  535. snd_soc_dapm_enable_pin(dapm, "HEADPHONE");
  536. }
  537. snd_soc_dapm_sync(dapm);
  538. mutex_unlock(&dapm->codec->mutex);
  539. return 0;
  540. }
  541. static int tabla_pa_gain_get(struct snd_kcontrol *kcontrol,
  542. struct snd_ctl_elem_value *ucontrol)
  543. {
  544. u8 ear_pa_gain;
  545. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  546. ear_pa_gain = snd_soc_read(codec, TABLA_A_RX_EAR_GAIN);
  547. ear_pa_gain = ear_pa_gain >> 5;
  548. if (ear_pa_gain == 0x00) {
  549. ucontrol->value.integer.value[0] = 0;
  550. } else if (ear_pa_gain == 0x04) {
  551. ucontrol->value.integer.value[0] = 1;
  552. } else {
  553. pr_err("%s: ERROR: Unsupported Ear Gain = 0x%x\n",
  554. __func__, ear_pa_gain);
  555. return -EINVAL;
  556. }
  557. pr_debug("%s: ear_pa_gain = 0x%x\n", __func__, ear_pa_gain);
  558. return 0;
  559. }
  560. static int tabla_pa_gain_put(struct snd_kcontrol *kcontrol,
  561. struct snd_ctl_elem_value *ucontrol)
  562. {
  563. u8 ear_pa_gain;
  564. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  565. pr_debug("%s: ucontrol->value.integer.value[0] = %ld\n", __func__,
  566. ucontrol->value.integer.value[0]);
  567. switch (ucontrol->value.integer.value[0]) {
  568. case 0:
  569. ear_pa_gain = 0x00;
  570. break;
  571. case 1:
  572. ear_pa_gain = 0x80;
  573. break;
  574. default:
  575. return -EINVAL;
  576. }
  577. snd_soc_update_bits(codec, TABLA_A_RX_EAR_GAIN, 0xE0, ear_pa_gain);
  578. return 0;
  579. }
  580. static int tabla_get_iir_enable_audio_mixer(
  581. struct snd_kcontrol *kcontrol,
  582. struct snd_ctl_elem_value *ucontrol)
  583. {
  584. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  585. int iir_idx = ((struct soc_multi_mixer_control *)
  586. kcontrol->private_value)->reg;
  587. int band_idx = ((struct soc_multi_mixer_control *)
  588. kcontrol->private_value)->shift;
  589. ucontrol->value.integer.value[0] =
  590. snd_soc_read(codec, (TABLA_A_CDC_IIR1_CTL + 16 * iir_idx)) &
  591. (1 << band_idx);
  592. pr_debug("%s: IIR #%d band #%d enable %d\n", __func__,
  593. iir_idx, band_idx,
  594. (uint32_t)ucontrol->value.integer.value[0]);
  595. return 0;
  596. }
  597. static int tabla_put_iir_enable_audio_mixer(
  598. struct snd_kcontrol *kcontrol,
  599. struct snd_ctl_elem_value *ucontrol)
  600. {
  601. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  602. int iir_idx = ((struct soc_multi_mixer_control *)
  603. kcontrol->private_value)->reg;
  604. int band_idx = ((struct soc_multi_mixer_control *)
  605. kcontrol->private_value)->shift;
  606. int value = ucontrol->value.integer.value[0];
  607. /* Mask first 5 bits, 6-8 are reserved */
  608. snd_soc_update_bits(codec, (TABLA_A_CDC_IIR1_CTL + 16 * iir_idx),
  609. (1 << band_idx), (value << band_idx));
  610. pr_debug("%s: IIR #%d band #%d enable %d\n", __func__,
  611. iir_idx, band_idx, value);
  612. return 0;
  613. }
  614. static uint32_t get_iir_band_coeff(struct snd_soc_codec *codec,
  615. int iir_idx, int band_idx,
  616. int coeff_idx)
  617. {
  618. /* Address does not automatically update if reading */
  619. snd_soc_write(codec,
  620. (TABLA_A_CDC_IIR1_COEF_B1_CTL + 16 * iir_idx),
  621. (band_idx * BAND_MAX + coeff_idx) & 0x1F);
  622. /* Mask bits top 2 bits since they are reserved */
  623. return ((snd_soc_read(codec,
  624. (TABLA_A_CDC_IIR1_COEF_B2_CTL + 16 * iir_idx)) << 24) |
  625. (snd_soc_read(codec,
  626. (TABLA_A_CDC_IIR1_COEF_B3_CTL + 16 * iir_idx)) << 16) |
  627. (snd_soc_read(codec,
  628. (TABLA_A_CDC_IIR1_COEF_B4_CTL + 16 * iir_idx)) << 8) |
  629. (snd_soc_read(codec,
  630. (TABLA_A_CDC_IIR1_COEF_B5_CTL + 16 * iir_idx)))) &
  631. 0x3FFFFFFF;
  632. }
  633. static int tabla_get_iir_band_audio_mixer(
  634. struct snd_kcontrol *kcontrol,
  635. struct snd_ctl_elem_value *ucontrol)
  636. {
  637. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  638. int iir_idx = ((struct soc_multi_mixer_control *)
  639. kcontrol->private_value)->reg;
  640. int band_idx = ((struct soc_multi_mixer_control *)
  641. kcontrol->private_value)->shift;
  642. ucontrol->value.integer.value[0] =
  643. get_iir_band_coeff(codec, iir_idx, band_idx, 0);
  644. ucontrol->value.integer.value[1] =
  645. get_iir_band_coeff(codec, iir_idx, band_idx, 1);
  646. ucontrol->value.integer.value[2] =
  647. get_iir_band_coeff(codec, iir_idx, band_idx, 2);
  648. ucontrol->value.integer.value[3] =
  649. get_iir_band_coeff(codec, iir_idx, band_idx, 3);
  650. ucontrol->value.integer.value[4] =
  651. get_iir_band_coeff(codec, iir_idx, band_idx, 4);
  652. pr_debug("%s: IIR #%d band #%d b0 = 0x%x\n"
  653. "%s: IIR #%d band #%d b1 = 0x%x\n"
  654. "%s: IIR #%d band #%d b2 = 0x%x\n"
  655. "%s: IIR #%d band #%d a1 = 0x%x\n"
  656. "%s: IIR #%d band #%d a2 = 0x%x\n",
  657. __func__, iir_idx, band_idx,
  658. (uint32_t)ucontrol->value.integer.value[0],
  659. __func__, iir_idx, band_idx,
  660. (uint32_t)ucontrol->value.integer.value[1],
  661. __func__, iir_idx, band_idx,
  662. (uint32_t)ucontrol->value.integer.value[2],
  663. __func__, iir_idx, band_idx,
  664. (uint32_t)ucontrol->value.integer.value[3],
  665. __func__, iir_idx, band_idx,
  666. (uint32_t)ucontrol->value.integer.value[4]);
  667. return 0;
  668. }
  669. static void set_iir_band_coeff(struct snd_soc_codec *codec,
  670. int iir_idx, int band_idx,
  671. int coeff_idx, uint32_t value)
  672. {
  673. /* Mask top 3 bits, 6-8 are reserved */
  674. /* Update address manually each time */
  675. snd_soc_write(codec,
  676. (TABLA_A_CDC_IIR1_COEF_B1_CTL + 16 * iir_idx),
  677. (band_idx * BAND_MAX + coeff_idx) & 0x1F);
  678. /* Mask top 2 bits, 7-8 are reserved */
  679. snd_soc_write(codec,
  680. (TABLA_A_CDC_IIR1_COEF_B2_CTL + 16 * iir_idx),
  681. (value >> 24) & 0x3F);
  682. /* Isolate 8bits at a time */
  683. snd_soc_write(codec,
  684. (TABLA_A_CDC_IIR1_COEF_B3_CTL + 16 * iir_idx),
  685. (value >> 16) & 0xFF);
  686. snd_soc_write(codec,
  687. (TABLA_A_CDC_IIR1_COEF_B4_CTL + 16 * iir_idx),
  688. (value >> 8) & 0xFF);
  689. snd_soc_write(codec,
  690. (TABLA_A_CDC_IIR1_COEF_B5_CTL + 16 * iir_idx),
  691. value & 0xFF);
  692. }
  693. static int tabla_put_iir_band_audio_mixer(
  694. struct snd_kcontrol *kcontrol,
  695. struct snd_ctl_elem_value *ucontrol)
  696. {
  697. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  698. int iir_idx = ((struct soc_multi_mixer_control *)
  699. kcontrol->private_value)->reg;
  700. int band_idx = ((struct soc_multi_mixer_control *)
  701. kcontrol->private_value)->shift;
  702. set_iir_band_coeff(codec, iir_idx, band_idx, 0,
  703. ucontrol->value.integer.value[0]);
  704. set_iir_band_coeff(codec, iir_idx, band_idx, 1,
  705. ucontrol->value.integer.value[1]);
  706. set_iir_band_coeff(codec, iir_idx, band_idx, 2,
  707. ucontrol->value.integer.value[2]);
  708. set_iir_band_coeff(codec, iir_idx, band_idx, 3,
  709. ucontrol->value.integer.value[3]);
  710. set_iir_band_coeff(codec, iir_idx, band_idx, 4,
  711. ucontrol->value.integer.value[4]);
  712. pr_debug("%s: IIR #%d band #%d b0 = 0x%x\n"
  713. "%s: IIR #%d band #%d b1 = 0x%x\n"
  714. "%s: IIR #%d band #%d b2 = 0x%x\n"
  715. "%s: IIR #%d band #%d a1 = 0x%x\n"
  716. "%s: IIR #%d band #%d a2 = 0x%x\n",
  717. __func__, iir_idx, band_idx,
  718. get_iir_band_coeff(codec, iir_idx, band_idx, 0),
  719. __func__, iir_idx, band_idx,
  720. get_iir_band_coeff(codec, iir_idx, band_idx, 1),
  721. __func__, iir_idx, band_idx,
  722. get_iir_band_coeff(codec, iir_idx, band_idx, 2),
  723. __func__, iir_idx, band_idx,
  724. get_iir_band_coeff(codec, iir_idx, band_idx, 3),
  725. __func__, iir_idx, band_idx,
  726. get_iir_band_coeff(codec, iir_idx, band_idx, 4));
  727. return 0;
  728. }
  729. static int tabla_compander_gain_offset(
  730. struct snd_soc_codec *codec, u32 enable,
  731. unsigned int pa_reg, unsigned int vol_reg,
  732. int mask, int event,
  733. struct comp_dgtl_gain_offset *gain_offset,
  734. int index)
  735. {
  736. unsigned int pa_gain = snd_soc_read(codec, pa_reg);
  737. unsigned int digital_vol = snd_soc_read(codec, vol_reg);
  738. int pa_mode = pa_gain & mask;
  739. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  740. pr_debug("%s: pa_gain(0x%x=0x%x)digital_vol(0x%x=0x%x)event(0x%x) index(%d)\n",
  741. __func__, pa_reg, pa_gain, vol_reg, digital_vol, event, index);
  742. if (((pa_gain & 0xF) + 1) > ARRAY_SIZE(comp_dgtl_gain) ||
  743. (index >= ARRAY_SIZE(tabla->comp_gain_offset))) {
  744. pr_err("%s: Out of array boundary\n", __func__);
  745. return -EINVAL;
  746. }
  747. if (SND_SOC_DAPM_EVENT_ON(event) && (enable != 0)) {
  748. gain_offset->whole_db_gain = COMP_DIGITAL_DB_GAIN_APPLY(
  749. (digital_vol - comp_dgtl_gain[pa_gain & 0xF].whole_db_gain),
  750. comp_dgtl_gain[pa_gain & 0xF].half_db_gain);
  751. pr_debug("%s: listed whole_db_gain:0x%x, adjusted whole_db_gain:0x%x\n",
  752. __func__, comp_dgtl_gain[pa_gain & 0xF].whole_db_gain,
  753. gain_offset->whole_db_gain);
  754. gain_offset->half_db_gain =
  755. comp_dgtl_gain[pa_gain & 0xF].half_db_gain;
  756. tabla->comp_gain_offset[index] = digital_vol -
  757. gain_offset->whole_db_gain ;
  758. }
  759. if (SND_SOC_DAPM_EVENT_OFF(event) && (pa_mode == 0)) {
  760. gain_offset->whole_db_gain = digital_vol +
  761. tabla->comp_gain_offset[index];
  762. pr_debug("%s: listed whole_db_gain:0x%x, adjusted whole_db_gain:0x%x\n",
  763. __func__, comp_dgtl_gain[pa_gain & 0xF].whole_db_gain,
  764. gain_offset->whole_db_gain);
  765. gain_offset->half_db_gain = 0;
  766. }
  767. pr_debug("%s: half_db_gain(%d)whole_db_gain(%d)comp_gain_offset[%d](%d)\n",
  768. __func__, gain_offset->half_db_gain,
  769. gain_offset->whole_db_gain, index,
  770. tabla->comp_gain_offset[index]);
  771. return 0;
  772. }
  773. static int tabla_config_gain_compander(
  774. struct snd_soc_codec *codec,
  775. u32 compander, u32 enable, int event)
  776. {
  777. int value = 0;
  778. int mask = 1 << 4;
  779. struct comp_dgtl_gain_offset gain_offset = {0, 0};
  780. if (compander >= COMPANDER_MAX) {
  781. pr_err("%s: Error, invalid compander channel\n", __func__);
  782. return -EINVAL;
  783. }
  784. if ((enable == 0) || SND_SOC_DAPM_EVENT_OFF(event))
  785. value = 1 << 4;
  786. if (compander == COMPANDER_1) {
  787. tabla_compander_gain_offset(codec, enable,
  788. TABLA_A_RX_HPH_L_GAIN,
  789. TABLA_A_CDC_RX1_VOL_CTL_B2_CTL,
  790. mask, event, &gain_offset, 0);
  791. snd_soc_update_bits(codec, TABLA_A_RX_HPH_L_GAIN, mask, value);
  792. snd_soc_update_bits(codec, TABLA_A_CDC_RX1_VOL_CTL_B2_CTL,
  793. 0xFF, gain_offset.whole_db_gain);
  794. snd_soc_update_bits(codec, TABLA_A_CDC_RX1_B6_CTL,
  795. 0x02, gain_offset.half_db_gain);
  796. tabla_compander_gain_offset(codec, enable,
  797. TABLA_A_RX_HPH_R_GAIN,
  798. TABLA_A_CDC_RX2_VOL_CTL_B2_CTL,
  799. mask, event, &gain_offset, 1);
  800. snd_soc_update_bits(codec, TABLA_A_RX_HPH_R_GAIN, mask, value);
  801. snd_soc_update_bits(codec, TABLA_A_CDC_RX2_VOL_CTL_B2_CTL,
  802. 0xFF, gain_offset.whole_db_gain);
  803. snd_soc_update_bits(codec, TABLA_A_CDC_RX2_B6_CTL,
  804. 0x02, gain_offset.half_db_gain);
  805. } else if (compander == COMPANDER_2) {
  806. tabla_compander_gain_offset(codec, enable,
  807. TABLA_A_RX_LINE_1_GAIN,
  808. TABLA_A_CDC_RX3_VOL_CTL_B2_CTL,
  809. mask, event, &gain_offset, 2);
  810. snd_soc_update_bits(codec, TABLA_A_RX_LINE_1_GAIN, mask, value);
  811. snd_soc_update_bits(codec, TABLA_A_CDC_RX3_VOL_CTL_B2_CTL,
  812. 0xFF, gain_offset.whole_db_gain);
  813. snd_soc_update_bits(codec, TABLA_A_CDC_RX3_B6_CTL,
  814. 0x02, gain_offset.half_db_gain);
  815. tabla_compander_gain_offset(codec, enable,
  816. TABLA_A_RX_LINE_3_GAIN,
  817. TABLA_A_CDC_RX4_VOL_CTL_B2_CTL,
  818. mask, event, &gain_offset, 3);
  819. snd_soc_update_bits(codec, TABLA_A_RX_LINE_3_GAIN, mask, value);
  820. snd_soc_update_bits(codec, TABLA_A_CDC_RX4_VOL_CTL_B2_CTL,
  821. 0xFF, gain_offset.whole_db_gain);
  822. snd_soc_update_bits(codec, TABLA_A_CDC_RX4_B6_CTL,
  823. 0x02, gain_offset.half_db_gain);
  824. tabla_compander_gain_offset(codec, enable,
  825. TABLA_A_RX_LINE_2_GAIN,
  826. TABLA_A_CDC_RX5_VOL_CTL_B2_CTL,
  827. mask, event, &gain_offset, 4);
  828. snd_soc_update_bits(codec, TABLA_A_RX_LINE_2_GAIN, mask, value);
  829. snd_soc_update_bits(codec, TABLA_A_CDC_RX5_VOL_CTL_B2_CTL,
  830. 0xFF, gain_offset.whole_db_gain);
  831. snd_soc_update_bits(codec, TABLA_A_CDC_RX5_B6_CTL,
  832. 0x02, gain_offset.half_db_gain);
  833. tabla_compander_gain_offset(codec, enable,
  834. TABLA_A_RX_LINE_4_GAIN,
  835. TABLA_A_CDC_RX6_VOL_CTL_B2_CTL,
  836. mask, event, &gain_offset, 5);
  837. snd_soc_update_bits(codec, TABLA_A_RX_LINE_4_GAIN, mask, value);
  838. snd_soc_update_bits(codec, TABLA_A_CDC_RX6_VOL_CTL_B2_CTL,
  839. 0xFF, gain_offset.whole_db_gain);
  840. snd_soc_update_bits(codec, TABLA_A_CDC_RX6_B6_CTL,
  841. 0x02, gain_offset.half_db_gain);
  842. }
  843. return 0;
  844. }
  845. static int tabla_get_compander(struct snd_kcontrol *kcontrol,
  846. struct snd_ctl_elem_value *ucontrol)
  847. {
  848. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  849. int comp = ((struct soc_multi_mixer_control *)
  850. kcontrol->private_value)->max;
  851. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  852. ucontrol->value.integer.value[0] = tabla->comp_enabled[comp];
  853. return 0;
  854. }
  855. static int tabla_set_compander(struct snd_kcontrol *kcontrol,
  856. struct snd_ctl_elem_value *ucontrol)
  857. {
  858. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  859. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  860. int comp = ((struct soc_multi_mixer_control *)
  861. kcontrol->private_value)->max;
  862. int value = ucontrol->value.integer.value[0];
  863. pr_debug("%s: compander #%d enable %d\n",
  864. __func__, comp + 1, value);
  865. if (value == tabla->comp_enabled[comp]) {
  866. pr_debug("%s: compander #%d enable %d no change\n",
  867. __func__, comp + 1, value);
  868. return 0;
  869. }
  870. tabla->comp_enabled[comp] = value;
  871. return 0;
  872. }
  873. static int tabla_config_compander(struct snd_soc_dapm_widget *w,
  874. struct snd_kcontrol *kcontrol,
  875. int event)
  876. {
  877. struct snd_soc_codec *codec = w->codec;
  878. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  879. u32 rate = tabla->comp_fs[w->shift];
  880. pr_debug("%s: compander #%d enable %d event %d widget name %s\n",
  881. __func__, w->shift + 1,
  882. tabla->comp_enabled[w->shift], event , w->name);
  883. if (tabla->comp_enabled[w->shift] == 0)
  884. goto rtn;
  885. if ((w->shift == COMPANDER_1) && (tabla->anc_func)) {
  886. pr_debug("%s: ANC is enabled so compander #%d cannot be enabled\n",
  887. __func__, w->shift + 1);
  888. goto rtn;
  889. }
  890. switch (event) {
  891. case SND_SOC_DAPM_PRE_PMU:
  892. /* Update compander sample rate */
  893. snd_soc_update_bits(codec, TABLA_A_CDC_COMP1_FS_CFG +
  894. w->shift * 8, 0x07, rate);
  895. /* Enable both L/R compander clocks */
  896. snd_soc_update_bits(codec,
  897. TABLA_A_CDC_CLK_RX_B2_CTL,
  898. 1 << comp_shift[w->shift],
  899. 1 << comp_shift[w->shift]);
  900. /* Toggle compander reset bits */
  901. snd_soc_update_bits(codec,
  902. TABLA_A_CDC_CLK_OTHR_RESET_CTL,
  903. 1 << comp_shift[w->shift],
  904. 1 << comp_shift[w->shift]);
  905. snd_soc_update_bits(codec,
  906. TABLA_A_CDC_CLK_OTHR_RESET_CTL,
  907. 1 << comp_shift[w->shift], 0);
  908. tabla_config_gain_compander(codec, w->shift, 1, event);
  909. /* Compander enable -> 0x370/0x378 */
  910. snd_soc_update_bits(codec, TABLA_A_CDC_COMP1_B1_CTL +
  911. w->shift * 8, 0x03, 0x03);
  912. /* Update the RMS meter resampling */
  913. snd_soc_update_bits(codec,
  914. TABLA_A_CDC_COMP1_B3_CTL +
  915. w->shift * 8, 0xFF, 0x01);
  916. snd_soc_update_bits(codec,
  917. TABLA_A_CDC_COMP1_B2_CTL +
  918. w->shift * 8, 0xF0, 0x50);
  919. usleep_range(COMP_BRINGUP_WAIT_TIME, COMP_BRINGUP_WAIT_TIME);
  920. break;
  921. case SND_SOC_DAPM_POST_PMU:
  922. /* Set sample rate dependent paramater */
  923. if (w->shift == COMPANDER_1) {
  924. snd_soc_update_bits(codec,
  925. TABLA_A_CDC_CLSG_CTL,
  926. 0x11, 0x00);
  927. snd_soc_write(codec,
  928. TABLA_A_CDC_CONN_CLSG_CTL, 0x11);
  929. }
  930. snd_soc_update_bits(codec, TABLA_A_CDC_COMP1_B2_CTL +
  931. w->shift * 8, 0x0F,
  932. comp_samp_params[rate].peak_det_timeout);
  933. snd_soc_update_bits(codec, TABLA_A_CDC_COMP1_B2_CTL +
  934. w->shift * 8, 0xF0,
  935. comp_samp_params[rate].rms_meter_div_fact);
  936. snd_soc_update_bits(codec, TABLA_A_CDC_COMP1_B3_CTL +
  937. w->shift * 8, 0xFF,
  938. comp_samp_params[rate].rms_meter_resamp_fact);
  939. snd_soc_update_bits(codec, TABLA_A_CDC_COMP1_B1_CTL +
  940. w->shift * 8, 0x38,
  941. comp_samp_params[rate].shutdown_timeout);
  942. break;
  943. case SND_SOC_DAPM_PRE_PMD:
  944. break;
  945. case SND_SOC_DAPM_POST_PMD:
  946. /* Disable the compander */
  947. snd_soc_update_bits(codec, TABLA_A_CDC_COMP1_B1_CTL +
  948. w->shift * 8, 0x03, 0x00);
  949. /* Toggle compander reset bits */
  950. snd_soc_update_bits(codec,
  951. TABLA_A_CDC_CLK_OTHR_RESET_CTL,
  952. 1 << comp_shift[w->shift],
  953. 1 << comp_shift[w->shift]);
  954. snd_soc_update_bits(codec,
  955. TABLA_A_CDC_CLK_OTHR_RESET_CTL,
  956. 1 << comp_shift[w->shift], 0);
  957. /* Turn off the clock for compander in pair */
  958. snd_soc_update_bits(codec, TABLA_A_CDC_CLK_RX_B2_CTL,
  959. 0x03 << comp_shift[w->shift], 0);
  960. /* Restore the gain */
  961. tabla_config_gain_compander(codec, w->shift,
  962. tabla->comp_enabled[w->shift],
  963. event);
  964. if (w->shift == COMPANDER_1) {
  965. snd_soc_update_bits(codec,
  966. TABLA_A_CDC_CLSG_CTL,
  967. 0x11, 0x11);
  968. snd_soc_write(codec,
  969. TABLA_A_CDC_CONN_CLSG_CTL, 0x14);
  970. }
  971. break;
  972. }
  973. rtn:
  974. return 0;
  975. }
  976. static int tabla_codec_hphr_dem_input_selection(struct snd_soc_dapm_widget *w,
  977. struct snd_kcontrol *kcontrol,
  978. int event)
  979. {
  980. struct snd_soc_codec *codec = w->codec;
  981. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  982. pr_debug("%s: compander#1->enable(%d) reg(0x%x = 0x%x) event(%d)\n",
  983. __func__, tabla->comp_enabled[COMPANDER_1],
  984. TABLA_A_CDC_RX1_B6_CTL,
  985. snd_soc_read(codec, TABLA_A_CDC_RX1_B6_CTL), event);
  986. switch (event) {
  987. case SND_SOC_DAPM_POST_PMU:
  988. if (tabla->comp_enabled[COMPANDER_1] && !tabla->anc_func)
  989. snd_soc_update_bits(codec, TABLA_A_CDC_RX1_B6_CTL,
  990. 1 << w->shift, 0);
  991. else
  992. snd_soc_update_bits(codec, TABLA_A_CDC_RX1_B6_CTL,
  993. 1 << w->shift, 1 << w->shift);
  994. break;
  995. case SND_SOC_DAPM_POST_PMD:
  996. snd_soc_update_bits(codec, TABLA_A_CDC_RX1_B6_CTL,
  997. 1 << w->shift, 0);
  998. break;
  999. default:
  1000. return -EINVAL;
  1001. }
  1002. return 0;
  1003. }
  1004. static int tabla_codec_hphl_dem_input_selection(struct snd_soc_dapm_widget *w,
  1005. struct snd_kcontrol *kcontrol,
  1006. int event)
  1007. {
  1008. struct snd_soc_codec *codec = w->codec;
  1009. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  1010. pr_debug("%s: compander#1->enable(%d) reg(0x%x = 0x%x) event(%d)\n",
  1011. __func__, tabla->comp_enabled[COMPANDER_1],
  1012. TABLA_A_CDC_RX2_B6_CTL,
  1013. snd_soc_read(codec, TABLA_A_CDC_RX2_B6_CTL), event);
  1014. switch (event) {
  1015. case SND_SOC_DAPM_POST_PMU:
  1016. if (tabla->comp_enabled[COMPANDER_1] && !tabla->anc_func)
  1017. snd_soc_update_bits(codec, TABLA_A_CDC_RX2_B6_CTL,
  1018. 1 << w->shift, 0);
  1019. else
  1020. snd_soc_update_bits(codec, TABLA_A_CDC_RX2_B6_CTL,
  1021. 1 << w->shift, 1 << w->shift);
  1022. break;
  1023. case SND_SOC_DAPM_POST_PMD:
  1024. snd_soc_update_bits(codec, TABLA_A_CDC_RX2_B6_CTL,
  1025. 1 << w->shift, 0);
  1026. break;
  1027. default:
  1028. return -EINVAL;
  1029. }
  1030. return 0;
  1031. }
  1032. static const char *const tabla_anc_func_text[] = {"OFF", "ON"};
  1033. static const struct soc_enum tabla_anc_func_enum =
  1034. SOC_ENUM_SINGLE_EXT(2, tabla_anc_func_text);
  1035. static const char *tabla_ear_pa_gain_text[] = {"POS_6_DB", "POS_2_DB"};
  1036. static const struct soc_enum tabla_ear_pa_gain_enum[] = {
  1037. SOC_ENUM_SINGLE_EXT(2, tabla_ear_pa_gain_text),
  1038. };
  1039. /*cut of frequency for high pass filter*/
  1040. static const char *cf_text[] = {
  1041. "MIN_3DB_4Hz", "MIN_3DB_75Hz", "MIN_3DB_150Hz"
  1042. };
  1043. static const struct soc_enum cf_dec1_enum =
  1044. SOC_ENUM_SINGLE(TABLA_A_CDC_TX1_MUX_CTL, 4, 3, cf_text);
  1045. static const struct soc_enum cf_dec2_enum =
  1046. SOC_ENUM_SINGLE(TABLA_A_CDC_TX2_MUX_CTL, 4, 3, cf_text);
  1047. static const struct soc_enum cf_dec3_enum =
  1048. SOC_ENUM_SINGLE(TABLA_A_CDC_TX3_MUX_CTL, 4, 3, cf_text);
  1049. static const struct soc_enum cf_dec4_enum =
  1050. SOC_ENUM_SINGLE(TABLA_A_CDC_TX4_MUX_CTL, 4, 3, cf_text);
  1051. static const struct soc_enum cf_dec5_enum =
  1052. SOC_ENUM_SINGLE(TABLA_A_CDC_TX5_MUX_CTL, 4, 3, cf_text);
  1053. static const struct soc_enum cf_dec6_enum =
  1054. SOC_ENUM_SINGLE(TABLA_A_CDC_TX6_MUX_CTL, 4, 3, cf_text);
  1055. static const struct soc_enum cf_dec7_enum =
  1056. SOC_ENUM_SINGLE(TABLA_A_CDC_TX7_MUX_CTL, 4, 3, cf_text);
  1057. static const struct soc_enum cf_dec8_enum =
  1058. SOC_ENUM_SINGLE(TABLA_A_CDC_TX8_MUX_CTL, 4, 3, cf_text);
  1059. static const struct soc_enum cf_dec9_enum =
  1060. SOC_ENUM_SINGLE(TABLA_A_CDC_TX9_MUX_CTL, 4, 3, cf_text);
  1061. static const struct soc_enum cf_dec10_enum =
  1062. SOC_ENUM_SINGLE(TABLA_A_CDC_TX10_MUX_CTL, 4, 3, cf_text);
  1063. static const struct soc_enum cf_rxmix1_enum =
  1064. SOC_ENUM_SINGLE(TABLA_A_CDC_RX1_B4_CTL, 1, 3, cf_text);
  1065. static const struct soc_enum cf_rxmix2_enum =
  1066. SOC_ENUM_SINGLE(TABLA_A_CDC_RX2_B4_CTL, 1, 3, cf_text);
  1067. static const struct soc_enum cf_rxmix3_enum =
  1068. SOC_ENUM_SINGLE(TABLA_A_CDC_RX3_B4_CTL, 1, 3, cf_text);
  1069. static const struct soc_enum cf_rxmix4_enum =
  1070. SOC_ENUM_SINGLE(TABLA_A_CDC_RX4_B4_CTL, 1, 3, cf_text);
  1071. static const struct soc_enum cf_rxmix5_enum =
  1072. SOC_ENUM_SINGLE(TABLA_A_CDC_RX5_B4_CTL, 1, 3, cf_text)
  1073. ;
  1074. static const struct soc_enum cf_rxmix6_enum =
  1075. SOC_ENUM_SINGLE(TABLA_A_CDC_RX6_B4_CTL, 1, 3, cf_text);
  1076. static const struct soc_enum cf_rxmix7_enum =
  1077. SOC_ENUM_SINGLE(TABLA_A_CDC_RX7_B4_CTL, 1, 3, cf_text);
  1078. static const struct snd_kcontrol_new tabla_snd_controls[] = {
  1079. SOC_ENUM_EXT("EAR PA Gain", tabla_ear_pa_gain_enum[0],
  1080. tabla_pa_gain_get, tabla_pa_gain_put),
  1081. SOC_SINGLE_TLV("LINEOUT1 Volume", TABLA_A_RX_LINE_1_GAIN, 0, 12, 1,
  1082. line_gain),
  1083. SOC_SINGLE_TLV("LINEOUT2 Volume", TABLA_A_RX_LINE_2_GAIN, 0, 12, 1,
  1084. line_gain),
  1085. SOC_SINGLE_TLV("LINEOUT3 Volume", TABLA_A_RX_LINE_3_GAIN, 0, 12, 1,
  1086. line_gain),
  1087. SOC_SINGLE_TLV("LINEOUT4 Volume", TABLA_A_RX_LINE_4_GAIN, 0, 12, 1,
  1088. line_gain),
  1089. SOC_SINGLE_TLV("LINEOUT5 Volume", TABLA_A_RX_LINE_5_GAIN, 0, 12, 1,
  1090. line_gain),
  1091. SOC_SINGLE_TLV("HPHL Volume", TABLA_A_RX_HPH_L_GAIN, 0, 12, 1,
  1092. line_gain),
  1093. SOC_SINGLE_TLV("HPHR Volume", TABLA_A_RX_HPH_R_GAIN, 0, 12, 1,
  1094. line_gain),
  1095. SOC_SINGLE_SX_TLV("RX1 Digital Volume", TABLA_A_CDC_RX1_VOL_CTL_B2_CTL,
  1096. 0, -84, 40, digital_gain),
  1097. SOC_SINGLE_SX_TLV("RX2 Digital Volume", TABLA_A_CDC_RX2_VOL_CTL_B2_CTL,
  1098. 0, -84, 40, digital_gain),
  1099. SOC_SINGLE_SX_TLV("RX3 Digital Volume", TABLA_A_CDC_RX3_VOL_CTL_B2_CTL,
  1100. 0, -84, 40, digital_gain),
  1101. SOC_SINGLE_SX_TLV("RX4 Digital Volume", TABLA_A_CDC_RX4_VOL_CTL_B2_CTL,
  1102. 0, -84, 40, digital_gain),
  1103. SOC_SINGLE_SX_TLV("RX5 Digital Volume", TABLA_A_CDC_RX5_VOL_CTL_B2_CTL,
  1104. 0, -84, 40, digital_gain),
  1105. SOC_SINGLE_SX_TLV("RX6 Digital Volume", TABLA_A_CDC_RX6_VOL_CTL_B2_CTL,
  1106. 0, -84, 40, digital_gain),
  1107. SOC_SINGLE_SX_TLV("RX7 Digital Volume", TABLA_A_CDC_RX7_VOL_CTL_B2_CTL,
  1108. 0, -84, 40, digital_gain),
  1109. SOC_SINGLE_SX_TLV("DEC1 Volume", TABLA_A_CDC_TX1_VOL_CTL_GAIN, 0, -84,
  1110. 40, digital_gain),
  1111. SOC_SINGLE_SX_TLV("DEC2 Volume", TABLA_A_CDC_TX2_VOL_CTL_GAIN, 0, -84,
  1112. 40, digital_gain),
  1113. SOC_SINGLE_SX_TLV("DEC3 Volume", TABLA_A_CDC_TX3_VOL_CTL_GAIN, 0, -84,
  1114. 40, digital_gain),
  1115. SOC_SINGLE_SX_TLV("DEC4 Volume", TABLA_A_CDC_TX4_VOL_CTL_GAIN, 0, -84,
  1116. 40, digital_gain),
  1117. SOC_SINGLE_SX_TLV("DEC5 Volume", TABLA_A_CDC_TX5_VOL_CTL_GAIN, 0, -84,
  1118. 40, digital_gain),
  1119. SOC_SINGLE_SX_TLV("DEC6 Volume", TABLA_A_CDC_TX6_VOL_CTL_GAIN, 0, -84,
  1120. 40, digital_gain),
  1121. SOC_SINGLE_SX_TLV("DEC7 Volume", TABLA_A_CDC_TX7_VOL_CTL_GAIN, 0, -84,
  1122. 40, digital_gain),
  1123. SOC_SINGLE_SX_TLV("DEC8 Volume", TABLA_A_CDC_TX8_VOL_CTL_GAIN, 0, -84,
  1124. 40, digital_gain),
  1125. SOC_SINGLE_SX_TLV("DEC9 Volume", TABLA_A_CDC_TX9_VOL_CTL_GAIN, 0, -84,
  1126. 40, digital_gain),
  1127. SOC_SINGLE_SX_TLV("DEC10 Volume", TABLA_A_CDC_TX10_VOL_CTL_GAIN, 0,
  1128. -84, 40, digital_gain),
  1129. SOC_SINGLE_SX_TLV("IIR1 INP1 Volume", TABLA_A_CDC_IIR1_GAIN_B1_CTL, 0,
  1130. -84, 40, digital_gain),
  1131. SOC_SINGLE_SX_TLV("IIR1 INP2 Volume", TABLA_A_CDC_IIR1_GAIN_B2_CTL, 0,
  1132. -84, 40, digital_gain),
  1133. SOC_SINGLE_SX_TLV("IIR1 INP3 Volume", TABLA_A_CDC_IIR1_GAIN_B3_CTL, 0,
  1134. -84, 40, digital_gain),
  1135. SOC_SINGLE_SX_TLV("IIR1 INP4 Volume", TABLA_A_CDC_IIR1_GAIN_B4_CTL, 0,
  1136. -84, 40, digital_gain),
  1137. SOC_SINGLE_TLV("ADC1 Volume", TABLA_A_TX_1_2_EN, 5, 3, 0, analog_gain),
  1138. SOC_SINGLE_TLV("ADC2 Volume", TABLA_A_TX_1_2_EN, 1, 3, 0, analog_gain),
  1139. SOC_SINGLE_TLV("ADC3 Volume", TABLA_A_TX_3_4_EN, 5, 3, 0, analog_gain),
  1140. SOC_SINGLE_TLV("ADC4 Volume", TABLA_A_TX_3_4_EN, 1, 3, 0, analog_gain),
  1141. SOC_SINGLE_TLV("ADC5 Volume", TABLA_A_TX_5_6_EN, 5, 3, 0, analog_gain),
  1142. SOC_SINGLE_TLV("ADC6 Volume", TABLA_A_TX_5_6_EN, 1, 3, 0, analog_gain),
  1143. SOC_SINGLE_TLV("AUX_PGA_LEFT Volume", TABLA_A_AUX_L_GAIN, 0, 39, 0,
  1144. aux_pga_gain),
  1145. SOC_SINGLE_TLV("AUX_PGA_RIGHT Volume", TABLA_A_AUX_R_GAIN, 0, 39, 0,
  1146. aux_pga_gain),
  1147. SOC_SINGLE("MICBIAS1 CAPLESS Switch", TABLA_A_MICB_1_CTL, 4, 1, 1),
  1148. SOC_SINGLE("MICBIAS2 CAPLESS Switch", TABLA_A_MICB_2_CTL, 4, 1, 1),
  1149. SOC_SINGLE("MICBIAS3 CAPLESS Switch", TABLA_A_MICB_3_CTL, 4, 1, 1),
  1150. SOC_SINGLE_EXT("ANC Slot", SND_SOC_NOPM, 0, 0, 100, tabla_get_anc_slot,
  1151. tabla_put_anc_slot),
  1152. SOC_ENUM_EXT("ANC Function", tabla_anc_func_enum, tabla_get_anc_func,
  1153. tabla_put_anc_func),
  1154. SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
  1155. SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
  1156. SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
  1157. SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
  1158. SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
  1159. SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
  1160. SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
  1161. SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
  1162. SOC_ENUM("TX9 HPF cut off", cf_dec9_enum),
  1163. SOC_ENUM("TX10 HPF cut off", cf_dec10_enum),
  1164. SOC_SINGLE("TX1 HPF Switch", TABLA_A_CDC_TX1_MUX_CTL, 3, 1, 0),
  1165. SOC_SINGLE("TX2 HPF Switch", TABLA_A_CDC_TX2_MUX_CTL, 3, 1, 0),
  1166. SOC_SINGLE("TX3 HPF Switch", TABLA_A_CDC_TX3_MUX_CTL, 3, 1, 0),
  1167. SOC_SINGLE("TX4 HPF Switch", TABLA_A_CDC_TX4_MUX_CTL, 3, 1, 0),
  1168. SOC_SINGLE("TX5 HPF Switch", TABLA_A_CDC_TX5_MUX_CTL, 3, 1, 0),
  1169. SOC_SINGLE("TX6 HPF Switch", TABLA_A_CDC_TX6_MUX_CTL, 3, 1, 0),
  1170. SOC_SINGLE("TX7 HPF Switch", TABLA_A_CDC_TX7_MUX_CTL, 3, 1, 0),
  1171. SOC_SINGLE("TX8 HPF Switch", TABLA_A_CDC_TX8_MUX_CTL, 3, 1, 0),
  1172. SOC_SINGLE("TX9 HPF Switch", TABLA_A_CDC_TX9_MUX_CTL, 3, 1, 0),
  1173. SOC_SINGLE("TX10 HPF Switch", TABLA_A_CDC_TX10_MUX_CTL, 3, 1, 0),
  1174. SOC_SINGLE("RX1 HPF Switch", TABLA_A_CDC_RX1_B5_CTL, 2, 1, 0),
  1175. SOC_SINGLE("RX2 HPF Switch", TABLA_A_CDC_RX2_B5_CTL, 2, 1, 0),
  1176. SOC_SINGLE("RX3 HPF Switch", TABLA_A_CDC_RX3_B5_CTL, 2, 1, 0),
  1177. SOC_SINGLE("RX4 HPF Switch", TABLA_A_CDC_RX4_B5_CTL, 2, 1, 0),
  1178. SOC_SINGLE("RX5 HPF Switch", TABLA_A_CDC_RX5_B5_CTL, 2, 1, 0),
  1179. SOC_SINGLE("RX6 HPF Switch", TABLA_A_CDC_RX6_B5_CTL, 2, 1, 0),
  1180. SOC_SINGLE("RX7 HPF Switch", TABLA_A_CDC_RX7_B5_CTL, 2, 1, 0),
  1181. SOC_ENUM("RX1 HPF cut off", cf_rxmix1_enum),
  1182. SOC_ENUM("RX2 HPF cut off", cf_rxmix2_enum),
  1183. SOC_ENUM("RX3 HPF cut off", cf_rxmix3_enum),
  1184. SOC_ENUM("RX4 HPF cut off", cf_rxmix4_enum),
  1185. SOC_ENUM("RX5 HPF cut off", cf_rxmix5_enum),
  1186. SOC_ENUM("RX6 HPF cut off", cf_rxmix6_enum),
  1187. SOC_ENUM("RX7 HPF cut off", cf_rxmix7_enum),
  1188. SOC_SINGLE_EXT("IIR1 Enable Band1", IIR1, BAND1, 1, 0,
  1189. tabla_get_iir_enable_audio_mixer, tabla_put_iir_enable_audio_mixer),
  1190. SOC_SINGLE_EXT("IIR1 Enable Band2", IIR1, BAND2, 1, 0,
  1191. tabla_get_iir_enable_audio_mixer, tabla_put_iir_enable_audio_mixer),
  1192. SOC_SINGLE_EXT("IIR1 Enable Band3", IIR1, BAND3, 1, 0,
  1193. tabla_get_iir_enable_audio_mixer, tabla_put_iir_enable_audio_mixer),
  1194. SOC_SINGLE_EXT("IIR1 Enable Band4", IIR1, BAND4, 1, 0,
  1195. tabla_get_iir_enable_audio_mixer, tabla_put_iir_enable_audio_mixer),
  1196. SOC_SINGLE_EXT("IIR1 Enable Band5", IIR1, BAND5, 1, 0,
  1197. tabla_get_iir_enable_audio_mixer, tabla_put_iir_enable_audio_mixer),
  1198. SOC_SINGLE_EXT("IIR2 Enable Band1", IIR2, BAND1, 1, 0,
  1199. tabla_get_iir_enable_audio_mixer, tabla_put_iir_enable_audio_mixer),
  1200. SOC_SINGLE_EXT("IIR2 Enable Band2", IIR2, BAND2, 1, 0,
  1201. tabla_get_iir_enable_audio_mixer, tabla_put_iir_enable_audio_mixer),
  1202. SOC_SINGLE_EXT("IIR2 Enable Band3", IIR2, BAND3, 1, 0,
  1203. tabla_get_iir_enable_audio_mixer, tabla_put_iir_enable_audio_mixer),
  1204. SOC_SINGLE_EXT("IIR2 Enable Band4", IIR2, BAND4, 1, 0,
  1205. tabla_get_iir_enable_audio_mixer, tabla_put_iir_enable_audio_mixer),
  1206. SOC_SINGLE_EXT("IIR2 Enable Band5", IIR2, BAND5, 1, 0,
  1207. tabla_get_iir_enable_audio_mixer, tabla_put_iir_enable_audio_mixer),
  1208. SOC_SINGLE_MULTI_EXT("IIR1 Band1", IIR1, BAND1, 255, 0, 5,
  1209. tabla_get_iir_band_audio_mixer, tabla_put_iir_band_audio_mixer),
  1210. SOC_SINGLE_MULTI_EXT("IIR1 Band2", IIR1, BAND2, 255, 0, 5,
  1211. tabla_get_iir_band_audio_mixer, tabla_put_iir_band_audio_mixer),
  1212. SOC_SINGLE_MULTI_EXT("IIR1 Band3", IIR1, BAND3, 255, 0, 5,
  1213. tabla_get_iir_band_audio_mixer, tabla_put_iir_band_audio_mixer),
  1214. SOC_SINGLE_MULTI_EXT("IIR1 Band4", IIR1, BAND4, 255, 0, 5,
  1215. tabla_get_iir_band_audio_mixer, tabla_put_iir_band_audio_mixer),
  1216. SOC_SINGLE_MULTI_EXT("IIR1 Band5", IIR1, BAND5, 255, 0, 5,
  1217. tabla_get_iir_band_audio_mixer, tabla_put_iir_band_audio_mixer),
  1218. SOC_SINGLE_MULTI_EXT("IIR2 Band1", IIR2, BAND1, 255, 0, 5,
  1219. tabla_get_iir_band_audio_mixer, tabla_put_iir_band_audio_mixer),
  1220. SOC_SINGLE_MULTI_EXT("IIR2 Band2", IIR2, BAND2, 255, 0, 5,
  1221. tabla_get_iir_band_audio_mixer, tabla_put_iir_band_audio_mixer),
  1222. SOC_SINGLE_MULTI_EXT("IIR2 Band3", IIR2, BAND3, 255, 0, 5,
  1223. tabla_get_iir_band_audio_mixer, tabla_put_iir_band_audio_mixer),
  1224. SOC_SINGLE_MULTI_EXT("IIR2 Band4", IIR2, BAND4, 255, 0, 5,
  1225. tabla_get_iir_band_audio_mixer, tabla_put_iir_band_audio_mixer),
  1226. SOC_SINGLE_MULTI_EXT("IIR2 Band5", IIR2, BAND5, 255, 0, 5,
  1227. tabla_get_iir_band_audio_mixer, tabla_put_iir_band_audio_mixer),
  1228. SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, 1, COMPANDER_1, 0,
  1229. tabla_get_compander, tabla_set_compander),
  1230. SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, 0, COMPANDER_2, 0,
  1231. tabla_get_compander, tabla_set_compander),
  1232. };
  1233. static const struct snd_kcontrol_new tabla_1_x_snd_controls[] = {
  1234. SOC_SINGLE("MICBIAS4 CAPLESS Switch", TABLA_1_A_MICB_4_CTL, 4, 1, 1),
  1235. };
  1236. static const struct snd_kcontrol_new tabla_2_higher_snd_controls[] = {
  1237. SOC_SINGLE("MICBIAS4 CAPLESS Switch", TABLA_2_A_MICB_4_CTL, 4, 1, 1),
  1238. };
  1239. static const char *rx_mix1_text[] = {
  1240. "ZERO", "SRC1", "SRC2", "IIR1", "IIR2", "RX1", "RX2", "RX3", "RX4",
  1241. "RX5", "RX6", "RX7"
  1242. };
  1243. static const char *rx_mix2_text[] = {
  1244. "ZERO", "SRC1", "SRC2", "IIR1", "IIR2"
  1245. };
  1246. static const char *rx_dsm_text[] = {
  1247. "CIC_OUT", "DSM_INV"
  1248. };
  1249. static const char *sb_tx1_mux_text[] = {
  1250. "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
  1251. "DEC1"
  1252. };
  1253. static const char *sb_tx2_mux_text[] = {
  1254. "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
  1255. "DEC2"
  1256. };
  1257. static const char *sb_tx3_mux_text[] = {
  1258. "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
  1259. "DEC3"
  1260. };
  1261. static const char *sb_tx4_mux_text[] = {
  1262. "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
  1263. "DEC4"
  1264. };
  1265. static const char *sb_tx5_mux_text[] = {
  1266. "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
  1267. "DEC5"
  1268. };
  1269. static const char *sb_tx6_mux_text[] = {
  1270. "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
  1271. "DEC6"
  1272. };
  1273. static const char const *sb_tx7_to_tx10_mux_text[] = {
  1274. "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
  1275. "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6", "DEC7", "DEC8",
  1276. "DEC9", "DEC10"
  1277. };
  1278. static const char *dec1_mux_text[] = {
  1279. "ZERO", "DMIC1", "ADC6",
  1280. };
  1281. static const char *dec2_mux_text[] = {
  1282. "ZERO", "DMIC2", "ADC5",
  1283. };
  1284. static const char *dec3_mux_text[] = {
  1285. "ZERO", "DMIC3", "ADC4",
  1286. };
  1287. static const char *dec4_mux_text[] = {
  1288. "ZERO", "DMIC4", "ADC3",
  1289. };
  1290. static const char *dec5_mux_text[] = {
  1291. "ZERO", "DMIC5", "ADC2",
  1292. };
  1293. static const char *dec6_mux_text[] = {
  1294. "ZERO", "DMIC6", "ADC1",
  1295. };
  1296. static const char const *dec7_mux_text[] = {
  1297. "ZERO", "DMIC1", "DMIC6", "ADC1", "ADC6", "ANC1_FB", "ANC2_FB",
  1298. };
  1299. static const char *dec8_mux_text[] = {
  1300. "ZERO", "DMIC2", "DMIC5", "ADC2", "ADC5",
  1301. };
  1302. static const char *dec9_mux_text[] = {
  1303. "ZERO", "DMIC4", "DMIC5", "ADC2", "ADC3", "ADCMB", "ANC1_FB", "ANC2_FB",
  1304. };
  1305. static const char *dec10_mux_text[] = {
  1306. "ZERO", "DMIC3", "DMIC6", "ADC1", "ADC4", "ADCMB", "ANC1_FB", "ANC2_FB",
  1307. };
  1308. static const char const *anc_mux_text[] = {
  1309. "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6", "ADC_MB",
  1310. "RSVD_1", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", "DMIC6"
  1311. };
  1312. static const char const *anc1_fb_mux_text[] = {
  1313. "ZERO", "EAR_HPH_L", "EAR_LINE_1",
  1314. };
  1315. static const char *const iir_inp1_text[] = {
  1316. "ZERO", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6", "DEC7", "DEC8",
  1317. "DEC9", "DEC10", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7"
  1318. };
  1319. static const struct soc_enum rx_mix1_inp1_chain_enum =
  1320. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX1_B1_CTL, 0, 12, rx_mix1_text);
  1321. static const struct soc_enum rx_mix1_inp2_chain_enum =
  1322. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX1_B1_CTL, 4, 12, rx_mix1_text);
  1323. static const struct soc_enum rx_mix1_inp3_chain_enum =
  1324. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX1_B2_CTL, 0, 12, rx_mix1_text);
  1325. static const struct soc_enum rx2_mix1_inp1_chain_enum =
  1326. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX2_B1_CTL, 0, 12, rx_mix1_text);
  1327. static const struct soc_enum rx2_mix1_inp2_chain_enum =
  1328. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX2_B1_CTL, 4, 12, rx_mix1_text);
  1329. static const struct soc_enum rx3_mix1_inp1_chain_enum =
  1330. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX3_B1_CTL, 0, 12, rx_mix1_text);
  1331. static const struct soc_enum rx3_mix1_inp2_chain_enum =
  1332. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX3_B1_CTL, 4, 12, rx_mix1_text);
  1333. static const struct soc_enum rx4_mix1_inp1_chain_enum =
  1334. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX4_B1_CTL, 0, 12, rx_mix1_text);
  1335. static const struct soc_enum rx4_mix1_inp2_chain_enum =
  1336. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX4_B1_CTL, 4, 12, rx_mix1_text);
  1337. static const struct soc_enum rx5_mix1_inp1_chain_enum =
  1338. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX5_B1_CTL, 0, 12, rx_mix1_text);
  1339. static const struct soc_enum rx5_mix1_inp2_chain_enum =
  1340. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX5_B1_CTL, 4, 12, rx_mix1_text);
  1341. static const struct soc_enum rx6_mix1_inp1_chain_enum =
  1342. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX6_B1_CTL, 0, 12, rx_mix1_text);
  1343. static const struct soc_enum rx6_mix1_inp2_chain_enum =
  1344. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX6_B1_CTL, 4, 12, rx_mix1_text);
  1345. static const struct soc_enum rx7_mix1_inp1_chain_enum =
  1346. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX7_B1_CTL, 0, 12, rx_mix1_text);
  1347. static const struct soc_enum rx7_mix1_inp2_chain_enum =
  1348. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX7_B1_CTL, 4, 12, rx_mix1_text);
  1349. static const struct soc_enum rx1_mix2_inp1_chain_enum =
  1350. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX1_B3_CTL, 0, 5, rx_mix2_text);
  1351. static const struct soc_enum rx1_mix2_inp2_chain_enum =
  1352. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX1_B3_CTL, 3, 5, rx_mix2_text);
  1353. static const struct soc_enum rx2_mix2_inp1_chain_enum =
  1354. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX2_B3_CTL, 0, 5, rx_mix2_text);
  1355. static const struct soc_enum rx2_mix2_inp2_chain_enum =
  1356. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX2_B3_CTL, 3, 5, rx_mix2_text);
  1357. static const struct soc_enum rx3_mix2_inp1_chain_enum =
  1358. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX3_B3_CTL, 0, 5, rx_mix2_text);
  1359. static const struct soc_enum rx3_mix2_inp2_chain_enum =
  1360. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_RX3_B3_CTL, 3, 5, rx_mix2_text);
  1361. static const struct soc_enum rx4_dsm_enum =
  1362. SOC_ENUM_SINGLE(TABLA_A_CDC_RX4_B6_CTL, 4, 2, rx_dsm_text);
  1363. static const struct soc_enum rx6_dsm_enum =
  1364. SOC_ENUM_SINGLE(TABLA_A_CDC_RX6_B6_CTL, 4, 2, rx_dsm_text);
  1365. static const struct soc_enum sb_tx1_mux_enum =
  1366. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B1_CTL, 0, 9, sb_tx1_mux_text);
  1367. static const struct soc_enum sb_tx2_mux_enum =
  1368. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B2_CTL, 0, 9, sb_tx2_mux_text);
  1369. static const struct soc_enum sb_tx3_mux_enum =
  1370. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B3_CTL, 0, 9, sb_tx3_mux_text);
  1371. static const struct soc_enum sb_tx4_mux_enum =
  1372. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B4_CTL, 0, 9, sb_tx4_mux_text);
  1373. static const struct soc_enum sb_tx5_mux_enum =
  1374. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B5_CTL, 0, 9, sb_tx5_mux_text);
  1375. static const struct soc_enum sb_tx6_mux_enum =
  1376. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B6_CTL, 0, 9, sb_tx6_mux_text);
  1377. static const struct soc_enum sb_tx7_mux_enum =
  1378. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B7_CTL, 0, 18,
  1379. sb_tx7_to_tx10_mux_text);
  1380. static const struct soc_enum sb_tx8_mux_enum =
  1381. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B8_CTL, 0, 18,
  1382. sb_tx7_to_tx10_mux_text);
  1383. static const struct soc_enum sb_tx9_mux_enum =
  1384. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B9_CTL, 0, 18,
  1385. sb_tx7_to_tx10_mux_text);
  1386. static const struct soc_enum sb_tx10_mux_enum =
  1387. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_SB_B10_CTL, 0, 18,
  1388. sb_tx7_to_tx10_mux_text);
  1389. static const struct soc_enum dec1_mux_enum =
  1390. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_B1_CTL, 0, 3, dec1_mux_text);
  1391. static const struct soc_enum dec2_mux_enum =
  1392. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_B1_CTL, 2, 3, dec2_mux_text);
  1393. static const struct soc_enum dec3_mux_enum =
  1394. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_B1_CTL, 4, 3, dec3_mux_text);
  1395. static const struct soc_enum dec4_mux_enum =
  1396. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_B1_CTL, 6, 3, dec4_mux_text);
  1397. static const struct soc_enum dec5_mux_enum =
  1398. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_B2_CTL, 0, 3, dec5_mux_text);
  1399. static const struct soc_enum dec6_mux_enum =
  1400. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_B2_CTL, 2, 3, dec6_mux_text);
  1401. static const struct soc_enum dec7_mux_enum =
  1402. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_B2_CTL, 4, 7, dec7_mux_text);
  1403. static const struct soc_enum dec8_mux_enum =
  1404. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_B3_CTL, 0, 7, dec8_mux_text);
  1405. static const struct soc_enum dec9_mux_enum =
  1406. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_B3_CTL, 3, 8, dec9_mux_text);
  1407. static const struct soc_enum dec10_mux_enum =
  1408. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_TX_B4_CTL, 0, 8, dec10_mux_text);
  1409. static const struct soc_enum anc1_mux_enum =
  1410. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_ANC_B1_CTL, 0, 16, anc_mux_text);
  1411. static const struct soc_enum anc2_mux_enum =
  1412. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_ANC_B1_CTL, 4, 16, anc_mux_text);
  1413. static const struct soc_enum anc1_fb_mux_enum =
  1414. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_ANC_B2_CTL, 0, 3, anc1_fb_mux_text);
  1415. static const struct soc_enum iir1_inp1_mux_enum =
  1416. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_EQ1_B1_CTL, 0, 18, iir_inp1_text);
  1417. static const struct soc_enum iir2_inp1_mux_enum =
  1418. SOC_ENUM_SINGLE(TABLA_A_CDC_CONN_EQ2_B1_CTL, 0, 18, iir_inp1_text);
  1419. static const struct snd_kcontrol_new rx_mix1_inp1_mux =
  1420. SOC_DAPM_ENUM("RX1 MIX1 INP1 Mux", rx_mix1_inp1_chain_enum);
  1421. static const struct snd_kcontrol_new rx_mix1_inp2_mux =
  1422. SOC_DAPM_ENUM("RX1 MIX1 INP2 Mux", rx_mix1_inp2_chain_enum);
  1423. static const struct snd_kcontrol_new rx_mix1_inp3_mux =
  1424. SOC_DAPM_ENUM("RX1 MIX1 INP3 Mux", rx_mix1_inp3_chain_enum);
  1425. static const struct snd_kcontrol_new rx2_mix1_inp1_mux =
  1426. SOC_DAPM_ENUM("RX2 MIX1 INP1 Mux", rx2_mix1_inp1_chain_enum);
  1427. static const struct snd_kcontrol_new rx2_mix1_inp2_mux =
  1428. SOC_DAPM_ENUM("RX2 MIX1 INP2 Mux", rx2_mix1_inp2_chain_enum);
  1429. static const struct snd_kcontrol_new rx3_mix1_inp1_mux =
  1430. SOC_DAPM_ENUM("RX3 MIX1 INP1 Mux", rx3_mix1_inp1_chain_enum);
  1431. static const struct snd_kcontrol_new rx3_mix1_inp2_mux =
  1432. SOC_DAPM_ENUM("RX3 MIX1 INP2 Mux", rx3_mix1_inp2_chain_enum);
  1433. static const struct snd_kcontrol_new rx4_mix1_inp1_mux =
  1434. SOC_DAPM_ENUM("RX4 MIX1 INP1 Mux", rx4_mix1_inp1_chain_enum);
  1435. static const struct snd_kcontrol_new rx4_mix1_inp2_mux =
  1436. SOC_DAPM_ENUM("RX4 MIX1 INP2 Mux", rx4_mix1_inp2_chain_enum);
  1437. static const struct snd_kcontrol_new rx5_mix1_inp1_mux =
  1438. SOC_DAPM_ENUM("RX5 MIX1 INP1 Mux", rx5_mix1_inp1_chain_enum);
  1439. static const struct snd_kcontrol_new rx5_mix1_inp2_mux =
  1440. SOC_DAPM_ENUM("RX5 MIX1 INP2 Mux", rx5_mix1_inp2_chain_enum);
  1441. static const struct snd_kcontrol_new rx6_mix1_inp1_mux =
  1442. SOC_DAPM_ENUM("RX6 MIX1 INP1 Mux", rx6_mix1_inp1_chain_enum);
  1443. static const struct snd_kcontrol_new rx6_mix1_inp2_mux =
  1444. SOC_DAPM_ENUM("RX6 MIX1 INP2 Mux", rx6_mix1_inp2_chain_enum);
  1445. static const struct snd_kcontrol_new rx7_mix1_inp1_mux =
  1446. SOC_DAPM_ENUM("RX7 MIX1 INP1 Mux", rx7_mix1_inp1_chain_enum);
  1447. static const struct snd_kcontrol_new rx7_mix1_inp2_mux =
  1448. SOC_DAPM_ENUM("RX7 MIX1 INP2 Mux", rx7_mix1_inp2_chain_enum);
  1449. static const struct snd_kcontrol_new rx1_mix2_inp1_mux =
  1450. SOC_DAPM_ENUM("RX1 MIX2 INP1 Mux", rx1_mix2_inp1_chain_enum);
  1451. static const struct snd_kcontrol_new rx1_mix2_inp2_mux =
  1452. SOC_DAPM_ENUM("RX1 MIX2 INP2 Mux", rx1_mix2_inp2_chain_enum);
  1453. static const struct snd_kcontrol_new rx2_mix2_inp1_mux =
  1454. SOC_DAPM_ENUM("RX2 MIX2 INP1 Mux", rx2_mix2_inp1_chain_enum);
  1455. static const struct snd_kcontrol_new rx2_mix2_inp2_mux =
  1456. SOC_DAPM_ENUM("RX2 MIX2 INP2 Mux", rx2_mix2_inp2_chain_enum);
  1457. static const struct snd_kcontrol_new rx3_mix2_inp1_mux =
  1458. SOC_DAPM_ENUM("RX3 MIX2 INP1 Mux", rx3_mix2_inp1_chain_enum);
  1459. static const struct snd_kcontrol_new rx3_mix2_inp2_mux =
  1460. SOC_DAPM_ENUM("RX3 MIX2 INP2 Mux", rx3_mix2_inp2_chain_enum);
  1461. static const struct snd_kcontrol_new rx4_dsm_mux =
  1462. SOC_DAPM_ENUM("RX4 DSM MUX Mux", rx4_dsm_enum);
  1463. static const struct snd_kcontrol_new rx6_dsm_mux =
  1464. SOC_DAPM_ENUM("RX6 DSM MUX Mux", rx6_dsm_enum);
  1465. static const struct snd_kcontrol_new sb_tx1_mux =
  1466. SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
  1467. static const struct snd_kcontrol_new sb_tx2_mux =
  1468. SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum);
  1469. static const struct snd_kcontrol_new sb_tx3_mux =
  1470. SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum);
  1471. static const struct snd_kcontrol_new sb_tx4_mux =
  1472. SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum);
  1473. static const struct snd_kcontrol_new sb_tx5_mux =
  1474. SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum);
  1475. static const struct snd_kcontrol_new sb_tx6_mux =
  1476. SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum);
  1477. static const struct snd_kcontrol_new sb_tx7_mux =
  1478. SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum);
  1479. static const struct snd_kcontrol_new sb_tx8_mux =
  1480. SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum);
  1481. static const struct snd_kcontrol_new sb_tx9_mux =
  1482. SOC_DAPM_ENUM("SLIM TX9 MUX Mux", sb_tx9_mux_enum);
  1483. static const struct snd_kcontrol_new sb_tx10_mux =
  1484. SOC_DAPM_ENUM("SLIM TX10 MUX Mux", sb_tx10_mux_enum);
  1485. static int wcd9310_put_dec_enum(struct snd_kcontrol *kcontrol,
  1486. struct snd_ctl_elem_value *ucontrol)
  1487. {
  1488. struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
  1489. struct snd_soc_dapm_widget *w = wlist->widgets[0];
  1490. struct snd_soc_codec *codec = w->codec;
  1491. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  1492. unsigned int dec_mux, decimator;
  1493. char *dec_name = NULL;
  1494. char *widget_name = NULL;
  1495. char *temp;
  1496. u16 tx_mux_ctl_reg;
  1497. u8 adc_dmic_sel = 0x0;
  1498. int ret = 0;
  1499. if (ucontrol->value.enumerated.item[0] > e->max - 1)
  1500. return -EINVAL;
  1501. dec_mux = ucontrol->value.enumerated.item[0];
  1502. widget_name = kstrndup(w->name, 15, GFP_KERNEL);
  1503. if (!widget_name)
  1504. return -ENOMEM;
  1505. temp = widget_name;
  1506. dec_name = strsep(&widget_name, " ");
  1507. widget_name = temp;
  1508. if (!dec_name) {
  1509. pr_err("%s: Invalid decimator = %s\n", __func__, w->name);
  1510. ret = -EINVAL;
  1511. goto out;
  1512. }
  1513. ret = kstrtouint(strpbrk(dec_name, "123456789"), 10, &decimator);
  1514. if (ret < 0) {
  1515. pr_err("%s: Invalid decimator = %s\n", __func__, dec_name);
  1516. ret = -EINVAL;
  1517. goto out;
  1518. }
  1519. dev_dbg(w->dapm->dev, "%s(): widget = %s dec_name = %s decimator = %u"
  1520. " dec_mux = %u\n", __func__, w->name, dec_name, decimator,
  1521. dec_mux);
  1522. switch (decimator) {
  1523. case 1:
  1524. case 2:
  1525. case 3:
  1526. case 4:
  1527. case 5:
  1528. case 6:
  1529. if (dec_mux == 1)
  1530. adc_dmic_sel = 0x1;
  1531. else
  1532. adc_dmic_sel = 0x0;
  1533. break;
  1534. case 7:
  1535. case 8:
  1536. case 9:
  1537. case 10:
  1538. if ((dec_mux == 1) || (dec_mux == 2))
  1539. adc_dmic_sel = 0x1;
  1540. else
  1541. adc_dmic_sel = 0x0;
  1542. break;
  1543. default:
  1544. pr_err("%s: Invalid Decimator = %u\n", __func__, decimator);
  1545. ret = -EINVAL;
  1546. goto out;
  1547. }
  1548. tx_mux_ctl_reg = TABLA_A_CDC_TX1_MUX_CTL + 8 * (decimator - 1);
  1549. snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x1, adc_dmic_sel);
  1550. ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
  1551. out:
  1552. kfree(widget_name);
  1553. return ret;
  1554. }
  1555. #define WCD9310_DEC_ENUM(xname, xenum) \
  1556. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  1557. .info = snd_soc_info_enum_double, \
  1558. .get = snd_soc_dapm_get_enum_double, \
  1559. .put = wcd9310_put_dec_enum, \
  1560. .private_value = (unsigned long)&xenum }
  1561. static const struct snd_kcontrol_new dec1_mux =
  1562. WCD9310_DEC_ENUM("DEC1 MUX Mux", dec1_mux_enum);
  1563. static const struct snd_kcontrol_new dec2_mux =
  1564. WCD9310_DEC_ENUM("DEC2 MUX Mux", dec2_mux_enum);
  1565. static const struct snd_kcontrol_new dec3_mux =
  1566. WCD9310_DEC_ENUM("DEC3 MUX Mux", dec3_mux_enum);
  1567. static const struct snd_kcontrol_new dec4_mux =
  1568. WCD9310_DEC_ENUM("DEC4 MUX Mux", dec4_mux_enum);
  1569. static const struct snd_kcontrol_new dec5_mux =
  1570. WCD9310_DEC_ENUM("DEC5 MUX Mux", dec5_mux_enum);
  1571. static const struct snd_kcontrol_new dec6_mux =
  1572. WCD9310_DEC_ENUM("DEC6 MUX Mux", dec6_mux_enum);
  1573. static const struct snd_kcontrol_new dec7_mux =
  1574. WCD9310_DEC_ENUM("DEC7 MUX Mux", dec7_mux_enum);
  1575. static const struct snd_kcontrol_new dec8_mux =
  1576. WCD9310_DEC_ENUM("DEC8 MUX Mux", dec8_mux_enum);
  1577. static const struct snd_kcontrol_new dec9_mux =
  1578. WCD9310_DEC_ENUM("DEC9 MUX Mux", dec9_mux_enum);
  1579. static const struct snd_kcontrol_new dec10_mux =
  1580. WCD9310_DEC_ENUM("DEC10 MUX Mux", dec10_mux_enum);
  1581. static const struct snd_kcontrol_new iir1_inp1_mux =
  1582. SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
  1583. static const struct snd_kcontrol_new iir2_inp1_mux =
  1584. SOC_DAPM_ENUM("IIR2 INP1 Mux", iir2_inp1_mux_enum);
  1585. static const struct snd_kcontrol_new anc1_mux =
  1586. SOC_DAPM_ENUM("ANC1 MUX Mux", anc1_mux_enum);
  1587. static const struct snd_kcontrol_new anc2_mux =
  1588. SOC_DAPM_ENUM("ANC2 MUX Mux", anc2_mux_enum);
  1589. static const struct snd_kcontrol_new anc1_fb_mux =
  1590. SOC_DAPM_ENUM("ANC1 FB MUX Mux", anc1_fb_mux_enum);
  1591. static const struct snd_kcontrol_new dac1_switch[] = {
  1592. SOC_DAPM_SINGLE("Switch", TABLA_A_RX_EAR_EN, 5, 1, 0)
  1593. };
  1594. static const struct snd_kcontrol_new hphl_switch[] = {
  1595. SOC_DAPM_SINGLE("Switch", TABLA_A_RX_HPH_L_DAC_CTL, 6, 1, 0)
  1596. };
  1597. static const struct snd_kcontrol_new hphl_pa_mix[] = {
  1598. SOC_DAPM_SINGLE("AUX_PGA_L Switch", TABLA_A_AUX_L_PA_CONN,
  1599. 7, 1, 0),
  1600. SOC_DAPM_SINGLE("AUX_PGA_R Switch", TABLA_A_AUX_R_PA_CONN,
  1601. 7, 1, 0),
  1602. SOC_DAPM_SINGLE("AUX_PGA_L_INV Switch",
  1603. TABLA_A_AUX_L_PA_CONN_INV, 7, 1, 0),
  1604. SOC_DAPM_SINGLE("AUX_PGA_R_INV Switch",
  1605. TABLA_A_AUX_R_PA_CONN_INV, 7, 1, 0),
  1606. };
  1607. static const struct snd_kcontrol_new hphr_pa_mix[] = {
  1608. SOC_DAPM_SINGLE("AUX_PGA_L Switch", TABLA_A_AUX_L_PA_CONN,
  1609. 6, 1, 0),
  1610. SOC_DAPM_SINGLE("AUX_PGA_R Switch", TABLA_A_AUX_R_PA_CONN,
  1611. 6, 1, 0),
  1612. SOC_DAPM_SINGLE("AUX_PGA_L_INV Switch",
  1613. TABLA_A_AUX_L_PA_CONN_INV, 6, 1, 0),
  1614. SOC_DAPM_SINGLE("AUX_PGA_R_INV Switch",
  1615. TABLA_A_AUX_R_PA_CONN_INV, 6, 1, 0),
  1616. };
  1617. static const struct snd_kcontrol_new lineout1_pa_mix[] = {
  1618. SOC_DAPM_SINGLE("AUX_PGA_L Switch", TABLA_A_AUX_L_PA_CONN,
  1619. 5, 1, 0),
  1620. SOC_DAPM_SINGLE("AUX_PGA_R Switch", TABLA_A_AUX_R_PA_CONN,
  1621. 5, 1, 0),
  1622. SOC_DAPM_SINGLE("AUX_PGA_L_INV Switch",
  1623. TABLA_A_AUX_L_PA_CONN_INV, 5, 1, 0),
  1624. SOC_DAPM_SINGLE("AUX_PGA_R_INV Switch",
  1625. TABLA_A_AUX_R_PA_CONN_INV, 5, 1, 0),
  1626. };
  1627. static const struct snd_kcontrol_new lineout2_pa_mix[] = {
  1628. SOC_DAPM_SINGLE("AUX_PGA_L Switch", TABLA_A_AUX_L_PA_CONN,
  1629. 4, 1, 0),
  1630. SOC_DAPM_SINGLE("AUX_PGA_R Switch", TABLA_A_AUX_R_PA_CONN,
  1631. 4, 1, 0),
  1632. SOC_DAPM_SINGLE("AUX_PGA_L_INV Switch",
  1633. TABLA_A_AUX_L_PA_CONN_INV, 4, 1, 0),
  1634. SOC_DAPM_SINGLE("AUX_PGA_R_INV Switch",
  1635. TABLA_A_AUX_R_PA_CONN_INV, 4, 1, 0),
  1636. };
  1637. static const struct snd_kcontrol_new lineout3_pa_mix[] = {
  1638. SOC_DAPM_SINGLE("AUX_PGA_L Switch", TABLA_A_AUX_L_PA_CONN,
  1639. 3, 1, 0),
  1640. SOC_DAPM_SINGLE("AUX_PGA_R Switch", TABLA_A_AUX_R_PA_CONN,
  1641. 3, 1, 0),
  1642. SOC_DAPM_SINGLE("AUX_PGA_L_INV Switch",
  1643. TABLA_A_AUX_L_PA_CONN_INV, 3, 1, 0),
  1644. SOC_DAPM_SINGLE("AUX_PGA_R_INV Switch",
  1645. TABLA_A_AUX_R_PA_CONN_INV, 3, 1, 0),
  1646. };
  1647. static const struct snd_kcontrol_new lineout4_pa_mix[] = {
  1648. SOC_DAPM_SINGLE("AUX_PGA_L Switch", TABLA_A_AUX_L_PA_CONN,
  1649. 2, 1, 0),
  1650. SOC_DAPM_SINGLE("AUX_PGA_R Switch", TABLA_A_AUX_R_PA_CONN,
  1651. 2, 1, 0),
  1652. SOC_DAPM_SINGLE("AUX_PGA_L_INV Switch",
  1653. TABLA_A_AUX_L_PA_CONN_INV, 2, 1, 0),
  1654. SOC_DAPM_SINGLE("AUX_PGA_R_INV Switch",
  1655. TABLA_A_AUX_R_PA_CONN_INV, 2, 1, 0),
  1656. };
  1657. static const struct snd_kcontrol_new lineout5_pa_mix[] = {
  1658. SOC_DAPM_SINGLE("AUX_PGA_L Switch", TABLA_A_AUX_L_PA_CONN,
  1659. 1, 1, 0),
  1660. SOC_DAPM_SINGLE("AUX_PGA_R Switch", TABLA_A_AUX_R_PA_CONN,
  1661. 1, 1, 0),
  1662. SOC_DAPM_SINGLE("AUX_PGA_L_INV Switch",
  1663. TABLA_A_AUX_L_PA_CONN_INV, 1, 1, 0),
  1664. SOC_DAPM_SINGLE("AUX_PGA_R_INV Switch",
  1665. TABLA_A_AUX_R_PA_CONN_INV, 1, 1, 0),
  1666. };
  1667. static const struct snd_kcontrol_new ear_pa_mix[] = {
  1668. SOC_DAPM_SINGLE("AUX_PGA_L Switch", TABLA_A_AUX_L_PA_CONN,
  1669. 0, 1, 0),
  1670. SOC_DAPM_SINGLE("AUX_PGA_R Switch", TABLA_A_AUX_R_PA_CONN,
  1671. 0, 1, 0),
  1672. SOC_DAPM_SINGLE("AUX_PGA_L_INV Switch",
  1673. TABLA_A_AUX_L_PA_CONN_INV, 0, 1, 0),
  1674. SOC_DAPM_SINGLE("AUX_PGA_R_INV Switch",
  1675. TABLA_A_AUX_R_PA_CONN_INV, 0, 1, 0),
  1676. };
  1677. static const struct snd_kcontrol_new lineout3_ground_switch =
  1678. SOC_DAPM_SINGLE("Switch", TABLA_A_RX_LINE_3_DAC_CTL, 6, 1, 0);
  1679. static const struct snd_kcontrol_new lineout4_ground_switch =
  1680. SOC_DAPM_SINGLE("Switch", TABLA_A_RX_LINE_4_DAC_CTL, 6, 1, 0);
  1681. /* virtual port entries */
  1682. static int slim_tx_mixer_get(struct snd_kcontrol *kcontrol,
  1683. struct snd_ctl_elem_value *ucontrol)
  1684. {
  1685. struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
  1686. struct snd_soc_dapm_widget *widget = wlist->widgets[0];
  1687. ucontrol->value.integer.value[0] = widget->value;
  1688. return 0;
  1689. }
  1690. static int slim_tx_mixer_put(struct snd_kcontrol *kcontrol,
  1691. struct snd_ctl_elem_value *ucontrol)
  1692. {
  1693. struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
  1694. struct snd_soc_dapm_widget *widget = wlist->widgets[0];
  1695. struct snd_soc_codec *codec = widget->codec;
  1696. struct tabla_priv *tabla_p = snd_soc_codec_get_drvdata(codec);
  1697. struct wcd9xxx *core = dev_get_drvdata(codec->dev->parent);
  1698. struct soc_multi_mixer_control *mixer =
  1699. ((struct soc_multi_mixer_control *)kcontrol->private_value);
  1700. u32 dai_id = widget->shift;
  1701. u32 port_id = mixer->shift;
  1702. u32 enable = ucontrol->value.integer.value[0];
  1703. u32 vtable = vport_check_table[dai_id];
  1704. pr_debug("%s: wname %s cname %s value %u shift %d item %ld\n", __func__,
  1705. widget->name, ucontrol->id.name, widget->value, widget->shift,
  1706. ucontrol->value.integer.value[0]);
  1707. mutex_lock(&codec->mutex);
  1708. if (tabla_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
  1709. if (dai_id != AIF1_CAP) {
  1710. dev_err(codec->dev, "%s: invalid AIF for I2C mode\n",
  1711. __func__);
  1712. mutex_unlock(&codec->mutex);
  1713. return -EINVAL;
  1714. }
  1715. }
  1716. switch (dai_id) {
  1717. case AIF1_CAP:
  1718. case AIF2_CAP:
  1719. case AIF3_CAP:
  1720. /* only add to the list if value not set
  1721. */
  1722. if (enable && !(widget->value & 1 << port_id)) {
  1723. if (tabla_p->intf_type ==
  1724. WCD9XXX_INTERFACE_TYPE_SLIMBUS)
  1725. vtable = vport_check_table[dai_id];
  1726. if (tabla_p->intf_type == WCD9XXX_INTERFACE_TYPE_I2C)
  1727. vtable = vport_i2s_check_table[dai_id];
  1728. if (wcd9xxx_tx_vport_validation(
  1729. vtable,
  1730. port_id,
  1731. tabla_p->dai, NUM_CODEC_DAIS)) {
  1732. dev_dbg(codec->dev, "%s: TX%u is used by other virtual port\n",
  1733. __func__, port_id + 1);
  1734. mutex_unlock(&codec->mutex);
  1735. return 0;
  1736. }
  1737. widget->value |= 1 << port_id;
  1738. list_add_tail(&core->tx_chs[port_id].list,
  1739. &tabla_p->dai[dai_id].wcd9xxx_ch_list
  1740. );
  1741. } else if (!enable && (widget->value & 1 << port_id)) {
  1742. widget->value &= ~(1 << port_id);
  1743. list_del_init(&core->tx_chs[port_id].list);
  1744. } else {
  1745. if (enable)
  1746. dev_dbg(codec->dev, "%s: TX%u port is used by this virtual port\n",
  1747. __func__, port_id + 1);
  1748. else
  1749. dev_dbg(codec->dev, "%s: TX%u port is not used by this virtual port\n",
  1750. __func__, port_id + 1);
  1751. /* avoid update power function */
  1752. mutex_unlock(&codec->mutex);
  1753. return 0;
  1754. }
  1755. break;
  1756. default:
  1757. pr_err("Unknown AIF %d\n", dai_id);
  1758. mutex_unlock(&codec->mutex);
  1759. return -EINVAL;
  1760. }
  1761. pr_debug("%s: name %s sname %s updated value %u shift %d\n", __func__,
  1762. widget->name, widget->sname, widget->value, widget->shift);
  1763. snd_soc_dapm_mixer_update_power(widget, kcontrol, enable);
  1764. mutex_unlock(&codec->mutex);
  1765. return 0;
  1766. }
  1767. static int slim_rx_mux_get(struct snd_kcontrol *kcontrol,
  1768. struct snd_ctl_elem_value *ucontrol)
  1769. {
  1770. struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
  1771. struct snd_soc_dapm_widget *widget = wlist->widgets[0];
  1772. ucontrol->value.enumerated.item[0] = widget->value;
  1773. return 0;
  1774. }
  1775. static const char *const slim_rx_mux_text[] = {
  1776. "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB"
  1777. };
  1778. static int slim_rx_mux_put(struct snd_kcontrol *kcontrol,
  1779. struct snd_ctl_elem_value *ucontrol)
  1780. {
  1781. struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
  1782. struct snd_soc_dapm_widget *widget = wlist->widgets[0];
  1783. struct snd_soc_codec *codec = widget->codec;
  1784. struct tabla_priv *tabla_p = snd_soc_codec_get_drvdata(codec);
  1785. struct wcd9xxx *core = dev_get_drvdata(codec->dev->parent);
  1786. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  1787. u32 port_id = widget->shift;
  1788. pr_debug("%s: wname %s cname %s value %u shift %d item %u\n", __func__,
  1789. widget->name, ucontrol->id.name, widget->value, widget->shift,
  1790. ucontrol->value.enumerated.item[0]);
  1791. widget->value = ucontrol->value.enumerated.item[0];
  1792. mutex_lock(&codec->mutex);
  1793. if (tabla_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
  1794. if (widget->value > 1) {
  1795. dev_err(codec->dev, "%s: invalid AIF for I2C mode\n",
  1796. __func__);
  1797. goto err;
  1798. }
  1799. }
  1800. /* value need to match the Virtual port and AIF number
  1801. */
  1802. switch (widget->value) {
  1803. case 0:
  1804. list_del_init(&core->rx_chs[port_id].list);
  1805. break;
  1806. case 1:
  1807. if (wcd9xxx_rx_vport_validation(port_id +
  1808. TABLA_RX_PORT_START_NUMBER,
  1809. &tabla_p->dai[AIF1_PB].wcd9xxx_ch_list)) {
  1810. dev_dbg(codec->dev, "%s: RX%u is used by current requesting AIF_PB itself\n",
  1811. __func__, port_id + 1);
  1812. goto rtn;
  1813. }
  1814. list_add_tail(&core->rx_chs[port_id].list,
  1815. &tabla_p->dai[AIF1_PB].wcd9xxx_ch_list);
  1816. break;
  1817. case 2:
  1818. if (wcd9xxx_rx_vport_validation(port_id +
  1819. TABLA_RX_PORT_START_NUMBER,
  1820. &tabla_p->dai[AIF1_PB].wcd9xxx_ch_list)) {
  1821. dev_dbg(codec->dev, "%s: RX%u is used by current requesting AIF_PB itself\n",
  1822. __func__, port_id + 1);
  1823. goto rtn;
  1824. }
  1825. list_add_tail(&core->rx_chs[port_id].list,
  1826. &tabla_p->dai[AIF2_PB].wcd9xxx_ch_list);
  1827. break;
  1828. case 3:
  1829. if (wcd9xxx_rx_vport_validation(port_id +
  1830. TABLA_RX_PORT_START_NUMBER,
  1831. &tabla_p->dai[AIF1_PB].wcd9xxx_ch_list)) {
  1832. dev_dbg(codec->dev, "%s: RX%u is used by current requesting AIF_PB itself\n",
  1833. __func__, port_id + 1);
  1834. goto rtn;
  1835. }
  1836. list_add_tail(&core->rx_chs[port_id].list,
  1837. &tabla_p->dai[AIF3_PB].wcd9xxx_ch_list);
  1838. break;
  1839. default:
  1840. pr_err("Unknown AIF %d\n", widget->value);
  1841. goto err;
  1842. }
  1843. rtn:
  1844. snd_soc_dapm_mux_update_power(widget, kcontrol, widget->value, e);
  1845. mutex_unlock(&codec->mutex);
  1846. return 0;
  1847. err:
  1848. mutex_unlock(&codec->mutex);
  1849. return -EINVAL;
  1850. }
  1851. static const struct soc_enum slim_rx_mux_enum =
  1852. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
  1853. static const struct snd_kcontrol_new slim_rx_mux[TABLA_RX_MAX] = {
  1854. SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
  1855. slim_rx_mux_get, slim_rx_mux_put),
  1856. SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
  1857. slim_rx_mux_get, slim_rx_mux_put),
  1858. SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
  1859. slim_rx_mux_get, slim_rx_mux_put),
  1860. SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
  1861. slim_rx_mux_get, slim_rx_mux_put),
  1862. SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
  1863. slim_rx_mux_get, slim_rx_mux_put),
  1864. SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
  1865. slim_rx_mux_get, slim_rx_mux_put),
  1866. SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
  1867. slim_rx_mux_get, slim_rx_mux_put),
  1868. };
  1869. static const struct snd_kcontrol_new aif_cap_mixer[] = {
  1870. SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, TABLA_TX1, 1, 0,
  1871. slim_tx_mixer_get, slim_tx_mixer_put),
  1872. SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, TABLA_TX2, 1, 0,
  1873. slim_tx_mixer_get, slim_tx_mixer_put),
  1874. SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, TABLA_TX3, 1, 0,
  1875. slim_tx_mixer_get, slim_tx_mixer_put),
  1876. SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, TABLA_TX4, 1, 0,
  1877. slim_tx_mixer_get, slim_tx_mixer_put),
  1878. SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, TABLA_TX5, 1, 0,
  1879. slim_tx_mixer_get, slim_tx_mixer_put),
  1880. SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, TABLA_TX6, 1, 0,
  1881. slim_tx_mixer_get, slim_tx_mixer_put),
  1882. SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, TABLA_TX7, 1, 0,
  1883. slim_tx_mixer_get, slim_tx_mixer_put),
  1884. SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, TABLA_TX8, 1, 0,
  1885. slim_tx_mixer_get, slim_tx_mixer_put),
  1886. SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, TABLA_TX9, 1, 0,
  1887. slim_tx_mixer_get, slim_tx_mixer_put),
  1888. SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, TABLA_TX10, 1, 0,
  1889. slim_tx_mixer_get, slim_tx_mixer_put),
  1890. };
  1891. static void tabla_codec_enable_adc_block(struct snd_soc_codec *codec,
  1892. int enable)
  1893. {
  1894. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  1895. pr_debug("%s %d\n", __func__, enable);
  1896. if (enable) {
  1897. tabla->adc_count++;
  1898. snd_soc_update_bits(codec, TABLA_A_CDC_CLK_OTHR_CTL, 0x2, 0x2);
  1899. } else {
  1900. tabla->adc_count--;
  1901. if (!tabla->adc_count)
  1902. snd_soc_update_bits(codec, TABLA_A_CDC_CLK_OTHR_CTL,
  1903. 0x2, 0x0);
  1904. }
  1905. }
  1906. static int tabla_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1907. struct snd_kcontrol *kcontrol, int event)
  1908. {
  1909. struct snd_soc_codec *codec = w->codec;
  1910. u16 adc_reg;
  1911. u8 init_bit_shift;
  1912. pr_debug("%s %d\n", __func__, event);
  1913. if (w->reg == TABLA_A_TX_1_2_EN)
  1914. adc_reg = TABLA_A_TX_1_2_TEST_CTL;
  1915. else if (w->reg == TABLA_A_TX_3_4_EN)
  1916. adc_reg = TABLA_A_TX_3_4_TEST_CTL;
  1917. else if (w->reg == TABLA_A_TX_5_6_EN)
  1918. adc_reg = TABLA_A_TX_5_6_TEST_CTL;
  1919. else {
  1920. pr_err("%s: Error, invalid adc register\n", __func__);
  1921. return -EINVAL;
  1922. }
  1923. if (w->shift == 3)
  1924. init_bit_shift = 6;
  1925. else if (w->shift == 7)
  1926. init_bit_shift = 7;
  1927. else {
  1928. pr_err("%s: Error, invalid init bit postion adc register\n",
  1929. __func__);
  1930. return -EINVAL;
  1931. }
  1932. switch (event) {
  1933. case SND_SOC_DAPM_PRE_PMU:
  1934. tabla_codec_enable_adc_block(codec, 1);
  1935. snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift,
  1936. 1 << init_bit_shift);
  1937. break;
  1938. case SND_SOC_DAPM_POST_PMU:
  1939. snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift, 0x00);
  1940. break;
  1941. case SND_SOC_DAPM_POST_PMD:
  1942. tabla_codec_enable_adc_block(codec, 0);
  1943. break;
  1944. }
  1945. return 0;
  1946. }
  1947. static void tabla_codec_enable_audio_mode_bandgap(struct snd_soc_codec *codec)
  1948. {
  1949. snd_soc_update_bits(codec, TABLA_A_BIAS_CENTRAL_BG_CTL, 0x80,
  1950. 0x80);
  1951. snd_soc_update_bits(codec, TABLA_A_BIAS_CENTRAL_BG_CTL, 0x04,
  1952. 0x04);
  1953. snd_soc_update_bits(codec, TABLA_A_BIAS_CENTRAL_BG_CTL, 0x01,
  1954. 0x01);
  1955. usleep_range(1000, 1000);
  1956. snd_soc_update_bits(codec, TABLA_A_BIAS_CENTRAL_BG_CTL, 0x80,
  1957. 0x00);
  1958. }
  1959. static void tabla_codec_enable_bandgap(struct snd_soc_codec *codec,
  1960. enum tabla_bandgap_type choice)
  1961. {
  1962. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  1963. /* TODO lock resources accessed by audio streams and threaded
  1964. * interrupt handlers
  1965. */
  1966. pr_debug("%s, choice is %d, current is %d\n", __func__, choice,
  1967. tabla->bandgap_type);
  1968. if (tabla->bandgap_type == choice)
  1969. return;
  1970. if ((tabla->bandgap_type == TABLA_BANDGAP_OFF) &&
  1971. (choice == TABLA_BANDGAP_AUDIO_MODE)) {
  1972. tabla_codec_enable_audio_mode_bandgap(codec);
  1973. } else if (choice == TABLA_BANDGAP_MBHC_MODE) {
  1974. /* bandgap mode becomes fast,
  1975. * mclk should be off or clk buff source souldn't be VBG
  1976. * Let's turn off mclk always */
  1977. WARN_ON(snd_soc_read(codec, TABLA_A_CLK_BUFF_EN2) & (1 << 2));
  1978. snd_soc_update_bits(codec, TABLA_A_BIAS_CENTRAL_BG_CTL, 0x2,
  1979. 0x2);
  1980. snd_soc_update_bits(codec, TABLA_A_BIAS_CENTRAL_BG_CTL, 0x80,
  1981. 0x80);
  1982. snd_soc_update_bits(codec, TABLA_A_BIAS_CENTRAL_BG_CTL, 0x4,
  1983. 0x4);
  1984. snd_soc_update_bits(codec, TABLA_A_BIAS_CENTRAL_BG_CTL, 0x01,
  1985. 0x01);
  1986. usleep_range(1000, 1000);
  1987. snd_soc_update_bits(codec, TABLA_A_BIAS_CENTRAL_BG_CTL, 0x80,
  1988. 0x00);
  1989. } else if ((tabla->bandgap_type == TABLA_BANDGAP_MBHC_MODE) &&
  1990. (choice == TABLA_BANDGAP_AUDIO_MODE)) {
  1991. snd_soc_write(codec, TABLA_A_BIAS_CENTRAL_BG_CTL, 0x50);
  1992. usleep_range(100, 100);
  1993. tabla_codec_enable_audio_mode_bandgap(codec);
  1994. } else if (choice == TABLA_BANDGAP_OFF) {
  1995. snd_soc_write(codec, TABLA_A_BIAS_CENTRAL_BG_CTL, 0x50);
  1996. } else {
  1997. pr_err("%s: Error, Invalid bandgap settings\n", __func__);
  1998. }
  1999. tabla->bandgap_type = choice;
  2000. }
  2001. static void tabla_codec_disable_clock_block(struct snd_soc_codec *codec)
  2002. {
  2003. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  2004. pr_debug("%s\n", __func__);
  2005. snd_soc_update_bits(codec, TABLA_A_CLK_BUFF_EN2, 0x04, 0x00);
  2006. usleep_range(50, 50);
  2007. snd_soc_update_bits(codec, TABLA_A_CLK_BUFF_EN2, 0x02, 0x02);
  2008. snd_soc_update_bits(codec, TABLA_A_CLK_BUFF_EN1, 0x05, 0x00);
  2009. usleep_range(50, 50);
  2010. tabla->clock_active = false;
  2011. }
  2012. static int tabla_codec_mclk_index(const struct tabla_priv *tabla)
  2013. {
  2014. if (tabla->mbhc_cfg.mclk_rate == TABLA_MCLK_RATE_12288KHZ)
  2015. return 0;
  2016. else if (tabla->mbhc_cfg.mclk_rate == TABLA_MCLK_RATE_9600KHZ)
  2017. return 1;
  2018. else {
  2019. BUG_ON(1);
  2020. return -EINVAL;
  2021. }
  2022. }
  2023. static void tabla_enable_rx_bias(struct snd_soc_codec *codec, u32 enable)
  2024. {
  2025. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  2026. if (enable) {
  2027. tabla->rx_bias_count++;
  2028. if (tabla->rx_bias_count == 1)
  2029. snd_soc_update_bits(codec, TABLA_A_RX_COM_BIAS,
  2030. 0x80, 0x80);
  2031. } else {
  2032. tabla->rx_bias_count--;
  2033. if (!tabla->rx_bias_count)
  2034. snd_soc_update_bits(codec, TABLA_A_RX_COM_BIAS,
  2035. 0x80, 0x00);
  2036. }
  2037. }
  2038. static int tabla_codec_enable_config_mode(struct snd_soc_codec *codec,
  2039. int enable)
  2040. {
  2041. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  2042. pr_debug("%s: enable = %d\n", __func__, enable);
  2043. if (enable) {
  2044. snd_soc_update_bits(codec, TABLA_A_CONFIG_MODE_FREQ, 0x10, 0);
  2045. /* bandgap mode to fast */
  2046. snd_soc_write(codec, TABLA_A_BIAS_CONFIG_MODE_BG_CTL, 0x17);
  2047. usleep_range(5, 5);
  2048. snd_soc_update_bits(codec, TABLA_A_CONFIG_MODE_FREQ, 0x80,
  2049. 0x80);
  2050. snd_soc_update_bits(codec, TABLA_A_CONFIG_MODE_TEST, 0x80,
  2051. 0x80);
  2052. usleep_range(10, 10);
  2053. snd_soc_update_bits(codec, TABLA_A_CONFIG_MODE_TEST, 0x80, 0);
  2054. usleep_range(10000, 10000);
  2055. snd_soc_update_bits(codec, TABLA_A_CLK_BUFF_EN1, 0x08, 0x08);
  2056. } else {
  2057. snd_soc_update_bits(codec, TABLA_A_BIAS_CONFIG_MODE_BG_CTL, 0x1,
  2058. 0);
  2059. snd_soc_update_bits(codec, TABLA_A_CONFIG_MODE_FREQ, 0x80, 0);
  2060. /* clk source to ext clk and clk buff ref to VBG */
  2061. snd_soc_update_bits(codec, TABLA_A_CLK_BUFF_EN1, 0x0C, 0x04);
  2062. }
  2063. tabla->config_mode_active = enable ? true : false;
  2064. return 0;
  2065. }
  2066. static int tabla_codec_enable_clock_block(struct snd_soc_codec *codec,
  2067. int config_mode)
  2068. {
  2069. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  2070. pr_debug("%s: config_mode = %d\n", __func__, config_mode);
  2071. /* transit to RCO requires mclk off */
  2072. WARN_ON(snd_soc_read(codec, TABLA_A_CLK_BUFF_EN2) & (1 << 2));
  2073. if (config_mode) {
  2074. /* enable RCO and switch to it */
  2075. tabla_codec_enable_config_mode(codec, 1);
  2076. snd_soc_write(codec, TABLA_A_CLK_BUFF_EN2, 0x02);
  2077. usleep_range(1000, 1000);
  2078. } else {
  2079. /* switch to MCLK */
  2080. snd_soc_update_bits(codec, TABLA_A_CLK_BUFF_EN1, 0x08, 0x00);
  2081. if (tabla->mbhc_polling_active) {
  2082. snd_soc_write(codec, TABLA_A_CLK_BUFF_EN2, 0x02);
  2083. tabla_codec_enable_config_mode(codec, 0);
  2084. }
  2085. }
  2086. snd_soc_update_bits(codec, TABLA_A_CLK_BUFF_EN1, 0x01, 0x01);
  2087. snd_soc_update_bits(codec, TABLA_A_CLK_BUFF_EN2, 0x02, 0x00);
  2088. /* on MCLK */
  2089. snd_soc_update_bits(codec, TABLA_A_CLK_BUFF_EN2, 0x04, 0x04);
  2090. snd_soc_update_bits(codec, TABLA_A_CDC_CLK_MCLK_CTL, 0x01, 0x01);
  2091. usleep_range(50, 50);
  2092. tabla->clock_active = true;
  2093. return 0;
  2094. }
  2095. static int tabla_codec_enable_aux_pga(struct snd_soc_dapm_widget *w,
  2096. struct snd_kcontrol *kcontrol, int event)
  2097. {
  2098. struct snd_soc_codec *codec = w->codec;
  2099. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  2100. pr_debug("%s: %d\n", __func__, event);
  2101. switch (event) {
  2102. case SND_SOC_DAPM_PRE_PMU:
  2103. tabla_codec_enable_bandgap(codec,
  2104. TABLA_BANDGAP_AUDIO_MODE);
  2105. tabla_enable_rx_bias(codec, 1);
  2106. snd_soc_update_bits(codec, TABLA_A_AUX_COM_CTL,
  2107. 0x08, 0x08);
  2108. /* Enable Zero Cross detect for AUX PGA channel
  2109. * and set the initial AUX PGA gain to NEG_0P0_DB
  2110. * to avoid glitches.
  2111. */
  2112. if (w->reg == TABLA_A_AUX_L_EN) {
  2113. snd_soc_update_bits(codec, TABLA_A_AUX_L_EN,
  2114. 0x20, 0x20);
  2115. tabla->aux_l_gain = snd_soc_read(codec,
  2116. TABLA_A_AUX_L_GAIN);
  2117. snd_soc_write(codec, TABLA_A_AUX_L_GAIN, 0x1F);
  2118. } else {
  2119. snd_soc_update_bits(codec, TABLA_A_AUX_R_EN,
  2120. 0x20, 0x20);
  2121. tabla->aux_r_gain = snd_soc_read(codec,
  2122. TABLA_A_AUX_R_GAIN);
  2123. snd_soc_write(codec, TABLA_A_AUX_R_GAIN, 0x1F);
  2124. }
  2125. if (tabla->aux_pga_cnt++ == 1
  2126. && !tabla->mclk_enabled) {
  2127. tabla_codec_enable_clock_block(codec, 1);
  2128. pr_debug("AUX PGA enabled RC osc\n");
  2129. }
  2130. break;
  2131. case SND_SOC_DAPM_POST_PMU:
  2132. if (w->reg == TABLA_A_AUX_L_EN)
  2133. snd_soc_write(codec, TABLA_A_AUX_L_GAIN,
  2134. tabla->aux_l_gain);
  2135. else
  2136. snd_soc_write(codec, TABLA_A_AUX_R_GAIN,
  2137. tabla->aux_r_gain);
  2138. break;
  2139. case SND_SOC_DAPM_PRE_PMD:
  2140. /* Mute AUX PGA channel in use before disabling AUX PGA */
  2141. if (w->reg == TABLA_A_AUX_L_EN) {
  2142. tabla->aux_l_gain = snd_soc_read(codec,
  2143. TABLA_A_AUX_L_GAIN);
  2144. snd_soc_write(codec, TABLA_A_AUX_L_GAIN, 0x1F);
  2145. } else {
  2146. tabla->aux_r_gain = snd_soc_read(codec,
  2147. TABLA_A_AUX_R_GAIN);
  2148. snd_soc_write(codec, TABLA_A_AUX_R_GAIN, 0x1F);
  2149. }
  2150. break;
  2151. case SND_SOC_DAPM_POST_PMD:
  2152. tabla_enable_rx_bias(codec, 0);
  2153. snd_soc_update_bits(codec, TABLA_A_AUX_COM_CTL,
  2154. 0x08, 0x00);
  2155. if (w->reg == TABLA_A_AUX_L_EN) {
  2156. snd_soc_write(codec, TABLA_A_AUX_L_GAIN,
  2157. tabla->aux_l_gain);
  2158. snd_soc_update_bits(codec, TABLA_A_AUX_L_EN,
  2159. 0x20, 0x00);
  2160. } else {
  2161. snd_soc_write(codec, TABLA_A_AUX_R_GAIN,
  2162. tabla->aux_r_gain);
  2163. snd_soc_update_bits(codec, TABLA_A_AUX_R_EN,
  2164. 0x20, 0x00);
  2165. }
  2166. if (tabla->aux_pga_cnt-- == 0) {
  2167. if (tabla->mbhc_polling_active)
  2168. tabla_codec_enable_bandgap(codec,
  2169. TABLA_BANDGAP_MBHC_MODE);
  2170. else
  2171. tabla_codec_enable_bandgap(codec,
  2172. TABLA_BANDGAP_OFF);
  2173. if (!tabla->mclk_enabled &&
  2174. !tabla->mbhc_polling_active) {
  2175. tabla_codec_enable_clock_block(codec, 0);
  2176. }
  2177. }
  2178. break;
  2179. }
  2180. return 0;
  2181. }
  2182. static int tabla_codec_enable_lineout(struct snd_soc_dapm_widget *w,
  2183. struct snd_kcontrol *kcontrol, int event)
  2184. {
  2185. struct snd_soc_codec *codec = w->codec;
  2186. u16 lineout_gain_reg;
  2187. pr_debug("%s %d %s\n", __func__, event, w->name);
  2188. switch (w->shift) {
  2189. case 0:
  2190. lineout_gain_reg = TABLA_A_RX_LINE_1_GAIN;
  2191. break;
  2192. case 1:
  2193. lineout_gain_reg = TABLA_A_RX_LINE_2_GAIN;
  2194. break;
  2195. case 2:
  2196. lineout_gain_reg = TABLA_A_RX_LINE_3_GAIN;
  2197. break;
  2198. case 3:
  2199. lineout_gain_reg = TABLA_A_RX_LINE_4_GAIN;
  2200. break;
  2201. case 4:
  2202. lineout_gain_reg = TABLA_A_RX_LINE_5_GAIN;
  2203. break;
  2204. default:
  2205. pr_err("%s: Error, incorrect lineout register value\n",
  2206. __func__);
  2207. return -EINVAL;
  2208. }
  2209. switch (event) {
  2210. case SND_SOC_DAPM_PRE_PMU:
  2211. snd_soc_update_bits(codec, lineout_gain_reg, 0x40, 0x40);
  2212. break;
  2213. case SND_SOC_DAPM_POST_PMU:
  2214. pr_debug("%s: sleeping 16 ms after %s PA turn on\n",
  2215. __func__, w->name);
  2216. usleep_range(16000, 16000);
  2217. break;
  2218. case SND_SOC_DAPM_POST_PMD:
  2219. snd_soc_update_bits(codec, lineout_gain_reg, 0x40, 0x00);
  2220. break;
  2221. }
  2222. return 0;
  2223. }
  2224. static int tabla_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  2225. struct snd_kcontrol *kcontrol, int event)
  2226. {
  2227. struct snd_soc_codec *codec = w->codec;
  2228. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  2229. u8 dmic_clk_en;
  2230. s32 *dmic_clk_cnt;
  2231. unsigned int dmic;
  2232. int ret;
  2233. ret = kstrtouint(strpbrk(w->name, "123456"), 10, &dmic);
  2234. if (ret < 0) {
  2235. pr_err("%s: Invalid DMIC line on the codec\n", __func__);
  2236. return -EINVAL;
  2237. }
  2238. switch (dmic) {
  2239. case 1:
  2240. case 2:
  2241. dmic_clk_en = 0x01;
  2242. dmic_clk_cnt = &(tabla->dmic_1_2_clk_cnt);
  2243. pr_debug("%s() event %d DMIC%d dmic_1_2_clk_cnt %d\n",
  2244. __func__, event, dmic, *dmic_clk_cnt);
  2245. break;
  2246. case 3:
  2247. case 4:
  2248. dmic_clk_en = 0x04;
  2249. dmic_clk_cnt = &(tabla->dmic_3_4_clk_cnt);
  2250. pr_debug("%s() event %d DMIC%d dmic_3_4_clk_cnt %d\n",
  2251. __func__, event, dmic, *dmic_clk_cnt);
  2252. break;
  2253. case 5:
  2254. case 6:
  2255. dmic_clk_en = 0x10;
  2256. dmic_clk_cnt = &(tabla->dmic_5_6_clk_cnt);
  2257. pr_debug("%s() event %d DMIC%d dmic_5_6_clk_cnt %d\n",
  2258. __func__, event, dmic, *dmic_clk_cnt);
  2259. break;
  2260. default:
  2261. pr_err("%s: Invalid DMIC Selection\n", __func__);
  2262. return -EINVAL;
  2263. }
  2264. switch (event) {
  2265. case SND_SOC_DAPM_PRE_PMU:
  2266. (*dmic_clk_cnt)++;
  2267. if (*dmic_clk_cnt == 1) {
  2268. snd_soc_update_bits(codec,
  2269. TABLA_A_CDC_DMIC_CLK0_MODE, 0x7, 0x0);
  2270. snd_soc_update_bits(codec,
  2271. TABLA_A_CDC_DMIC_CLK1_MODE, 0x7, 0x0);
  2272. snd_soc_update_bits(codec,
  2273. TABLA_A_CDC_DMIC_CLK2_MODE, 0x7, 0x0);
  2274. snd_soc_update_bits(codec, TABLA_A_CDC_CLK_DMIC_CTL,
  2275. dmic_clk_en, dmic_clk_en);
  2276. }
  2277. break;
  2278. case SND_SOC_DAPM_POST_PMD:
  2279. (*dmic_clk_cnt)--;
  2280. if (*dmic_clk_cnt == 0) {
  2281. snd_soc_update_bits(codec, TABLA_A_CDC_CLK_DMIC_CTL,
  2282. dmic_clk_en, 0);
  2283. snd_soc_update_bits(codec,
  2284. TABLA_A_CDC_DMIC_CLK0_MODE, 0x7, 0x4);
  2285. snd_soc_update_bits(codec,
  2286. TABLA_A_CDC_DMIC_CLK1_MODE, 0x7, 0x4);
  2287. snd_soc_update_bits(codec,
  2288. TABLA_A_CDC_DMIC_CLK2_MODE, 0x7, 0x4);
  2289. }
  2290. break;
  2291. }
  2292. return 0;
  2293. }
  2294. /* called under codec_resource_lock acquisition */
  2295. static void tabla_codec_start_hs_polling(struct snd_soc_codec *codec)
  2296. {
  2297. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  2298. struct wcd9xxx *tabla_core = dev_get_drvdata(codec->dev->parent);
  2299. int mbhc_state = tabla->mbhc_state;
  2300. pr_debug("%s: enter\n", __func__);
  2301. if (!tabla->mbhc_polling_active) {
  2302. pr_debug("Polling is not active, do not start polling\n");
  2303. return;
  2304. }
  2305. snd_soc_write(codec, TABLA_A_MBHC_SCALING_MUX_1, 0x84);
  2306. if (tabla->no_mic_headset_override) {
  2307. pr_debug("%s setting button threshold to min", __func__);
  2308. /* set to min */
  2309. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B4_CTL, 0x80);
  2310. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B3_CTL, 0x00);
  2311. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B6_CTL, 0x80);
  2312. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B5_CTL, 0x00);
  2313. } else if (unlikely(mbhc_state == MBHC_STATE_POTENTIAL)) {
  2314. pr_debug("%s recovering MBHC state machine\n", __func__);
  2315. tabla->mbhc_state = MBHC_STATE_POTENTIAL_RECOVERY;
  2316. /* set to max button press threshold */
  2317. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B2_CTL, 0x7F);
  2318. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B1_CTL, 0xFF);
  2319. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B4_CTL,
  2320. (TABLA_IS_1_X(tabla_core->version) ?
  2321. 0x07 : 0x7F));
  2322. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B3_CTL, 0xFF);
  2323. /* set to max */
  2324. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B6_CTL, 0x7F);
  2325. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B5_CTL, 0xFF);
  2326. }
  2327. snd_soc_write(codec, TABLA_A_CDC_MBHC_EN_CTL, 0x1);
  2328. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x8, 0x0);
  2329. snd_soc_write(codec, TABLA_A_CDC_MBHC_EN_CTL, 0x1);
  2330. pr_debug("%s: leave\n", __func__);
  2331. }
  2332. /* called under codec_resource_lock acquisition */
  2333. static void tabla_codec_pause_hs_polling(struct snd_soc_codec *codec)
  2334. {
  2335. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  2336. pr_debug("%s: enter\n", __func__);
  2337. if (!tabla->mbhc_polling_active) {
  2338. pr_debug("polling not active, nothing to pause\n");
  2339. return;
  2340. }
  2341. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.ctl_reg, 0x01, 0x01);
  2342. msleep(20);
  2343. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.ctl_reg, 0x01, 0x00);
  2344. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x8, 0x8);
  2345. pr_debug("%s: leave\n", __func__);
  2346. }
  2347. static void tabla_codec_switch_cfilt_mode(struct snd_soc_codec *codec, int mode)
  2348. {
  2349. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  2350. u8 reg_mode_val, cur_mode_val;
  2351. bool mbhc_was_polling = false;
  2352. if (mode)
  2353. reg_mode_val = TABLA_CFILT_FAST_MODE;
  2354. else
  2355. reg_mode_val = TABLA_CFILT_SLOW_MODE;
  2356. cur_mode_val = snd_soc_read(codec,
  2357. tabla->mbhc_bias_regs.cfilt_ctl) & 0x40;
  2358. if (cur_mode_val != reg_mode_val) {
  2359. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  2360. if (tabla->mbhc_polling_active) {
  2361. tabla_codec_pause_hs_polling(codec);
  2362. mbhc_was_polling = true;
  2363. }
  2364. snd_soc_update_bits(codec,
  2365. tabla->mbhc_bias_regs.cfilt_ctl, 0x40, reg_mode_val);
  2366. if (mbhc_was_polling)
  2367. tabla_codec_start_hs_polling(codec);
  2368. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  2369. pr_debug("%s: CFILT mode change (%x to %x)\n", __func__,
  2370. cur_mode_val, reg_mode_val);
  2371. } else {
  2372. pr_debug("%s: CFILT Value is already %x\n",
  2373. __func__, cur_mode_val);
  2374. }
  2375. }
  2376. static void tabla_codec_update_cfilt_usage(struct snd_soc_codec *codec,
  2377. u8 cfilt_sel, int inc)
  2378. {
  2379. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  2380. u32 *cfilt_cnt_ptr = NULL;
  2381. u16 micb_cfilt_reg;
  2382. switch (cfilt_sel) {
  2383. case TABLA_CFILT1_SEL:
  2384. cfilt_cnt_ptr = &tabla->cfilt1_cnt;
  2385. micb_cfilt_reg = TABLA_A_MICB_CFILT_1_CTL;
  2386. break;
  2387. case TABLA_CFILT2_SEL:
  2388. cfilt_cnt_ptr = &tabla->cfilt2_cnt;
  2389. micb_cfilt_reg = TABLA_A_MICB_CFILT_2_CTL;
  2390. break;
  2391. case TABLA_CFILT3_SEL:
  2392. cfilt_cnt_ptr = &tabla->cfilt3_cnt;
  2393. micb_cfilt_reg = TABLA_A_MICB_CFILT_3_CTL;
  2394. break;
  2395. default:
  2396. return; /* should not happen */
  2397. }
  2398. if (inc) {
  2399. if (!(*cfilt_cnt_ptr)++) {
  2400. /* Switch CFILT to slow mode if MBHC CFILT being used */
  2401. if (cfilt_sel == tabla->mbhc_bias_regs.cfilt_sel)
  2402. tabla_codec_switch_cfilt_mode(codec, 0);
  2403. snd_soc_update_bits(codec, micb_cfilt_reg, 0x80, 0x80);
  2404. }
  2405. } else {
  2406. /* check if count not zero, decrement
  2407. * then check if zero, go ahead disable cfilter
  2408. */
  2409. if ((*cfilt_cnt_ptr) && !--(*cfilt_cnt_ptr)) {
  2410. snd_soc_update_bits(codec, micb_cfilt_reg, 0x80, 0);
  2411. /* Switch CFILT to fast mode if MBHC CFILT being used */
  2412. if (cfilt_sel == tabla->mbhc_bias_regs.cfilt_sel)
  2413. tabla_codec_switch_cfilt_mode(codec, 1);
  2414. }
  2415. }
  2416. }
  2417. static int tabla_find_k_value(unsigned int ldoh_v, unsigned int cfilt_mv)
  2418. {
  2419. int rc = -EINVAL;
  2420. unsigned min_mv, max_mv;
  2421. switch (ldoh_v) {
  2422. case TABLA_LDOH_1P95_V:
  2423. min_mv = 160;
  2424. max_mv = 1800;
  2425. break;
  2426. case TABLA_LDOH_2P35_V:
  2427. min_mv = 200;
  2428. max_mv = 2200;
  2429. break;
  2430. case TABLA_LDOH_2P75_V:
  2431. min_mv = 240;
  2432. max_mv = 2600;
  2433. break;
  2434. case TABLA_LDOH_2P85_V:
  2435. min_mv = 250;
  2436. max_mv = 2700;
  2437. break;
  2438. default:
  2439. goto done;
  2440. }
  2441. if (cfilt_mv < min_mv || cfilt_mv > max_mv)
  2442. goto done;
  2443. for (rc = 4; rc <= 44; rc++) {
  2444. min_mv = max_mv * (rc) / 44;
  2445. if (min_mv >= cfilt_mv) {
  2446. rc -= 4;
  2447. break;
  2448. }
  2449. }
  2450. done:
  2451. return rc;
  2452. }
  2453. static bool tabla_is_hph_pa_on(struct snd_soc_codec *codec)
  2454. {
  2455. u8 hph_reg_val = 0;
  2456. hph_reg_val = snd_soc_read(codec, TABLA_A_RX_HPH_CNP_EN);
  2457. return (hph_reg_val & 0x30) ? true : false;
  2458. }
  2459. static bool tabla_is_hph_dac_on(struct snd_soc_codec *codec, int left)
  2460. {
  2461. u8 hph_reg_val = 0;
  2462. if (left)
  2463. hph_reg_val = snd_soc_read(codec,
  2464. TABLA_A_RX_HPH_L_DAC_CTL);
  2465. else
  2466. hph_reg_val = snd_soc_read(codec,
  2467. TABLA_A_RX_HPH_R_DAC_CTL);
  2468. return (hph_reg_val & 0xC0) ? true : false;
  2469. }
  2470. static void tabla_turn_onoff_override(struct snd_soc_codec *codec, bool on)
  2471. {
  2472. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x04, on << 2);
  2473. }
  2474. /* called under codec_resource_lock acquisition */
  2475. static void tabla_codec_drive_v_to_micbias(struct snd_soc_codec *codec,
  2476. int usec)
  2477. {
  2478. int cfilt_k_val;
  2479. bool set = true;
  2480. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  2481. if (tabla->mbhc_data.micb_mv != VDDIO_MICBIAS_MV &&
  2482. tabla->mbhc_micbias_switched) {
  2483. pr_debug("%s: set mic V to micbias V\n", __func__);
  2484. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x2, 0x2);
  2485. tabla_turn_onoff_override(codec, true);
  2486. while (1) {
  2487. cfilt_k_val = tabla_find_k_value(
  2488. tabla->pdata->micbias.ldoh_v,
  2489. set ? tabla->mbhc_data.micb_mv :
  2490. VDDIO_MICBIAS_MV);
  2491. snd_soc_update_bits(codec,
  2492. tabla->mbhc_bias_regs.cfilt_val,
  2493. 0xFC, (cfilt_k_val << 2));
  2494. if (!set)
  2495. break;
  2496. usleep_range(usec, usec);
  2497. set = false;
  2498. }
  2499. tabla_turn_onoff_override(codec, false);
  2500. }
  2501. }
  2502. /* called under codec_resource_lock acquisition */
  2503. static void __tabla_codec_switch_micbias(struct snd_soc_codec *codec,
  2504. int vddio_switch, bool restartpolling,
  2505. bool checkpolling)
  2506. {
  2507. int cfilt_k_val;
  2508. bool override;
  2509. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  2510. if (vddio_switch && !tabla->mbhc_micbias_switched &&
  2511. (!checkpolling || tabla->mbhc_polling_active)) {
  2512. if (restartpolling)
  2513. tabla_codec_pause_hs_polling(codec);
  2514. override = snd_soc_read(codec, TABLA_A_CDC_MBHC_B1_CTL) & 0x04;
  2515. if (!override)
  2516. tabla_turn_onoff_override(codec, true);
  2517. /* Adjust threshold if Mic Bias voltage changes */
  2518. if (tabla->mbhc_data.micb_mv != VDDIO_MICBIAS_MV) {
  2519. cfilt_k_val = tabla_find_k_value(
  2520. tabla->pdata->micbias.ldoh_v,
  2521. VDDIO_MICBIAS_MV);
  2522. snd_soc_update_bits(codec,
  2523. tabla->mbhc_bias_regs.cfilt_val,
  2524. 0xFC, (cfilt_k_val << 2));
  2525. usleep_range(cfilt_adjust_ms * 1000,
  2526. cfilt_adjust_ms * 1000);
  2527. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B1_CTL,
  2528. tabla->mbhc_data.adj_v_ins_hu & 0xFF);
  2529. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B2_CTL,
  2530. (tabla->mbhc_data.adj_v_ins_hu >> 8) &
  2531. 0xFF);
  2532. pr_debug("%s: Programmed MBHC thresholds to VDDIO\n",
  2533. __func__);
  2534. }
  2535. /* enable MIC BIAS Switch to VDDIO */
  2536. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg,
  2537. 0x80, 0x80);
  2538. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg,
  2539. 0x10, 0x00);
  2540. if (!override)
  2541. tabla_turn_onoff_override(codec, false);
  2542. if (restartpolling)
  2543. tabla_codec_start_hs_polling(codec);
  2544. tabla->mbhc_micbias_switched = true;
  2545. pr_debug("%s: VDDIO switch enabled\n", __func__);
  2546. } else if (!vddio_switch && tabla->mbhc_micbias_switched) {
  2547. if ((!checkpolling || tabla->mbhc_polling_active) &&
  2548. restartpolling)
  2549. tabla_codec_pause_hs_polling(codec);
  2550. /* Reprogram thresholds */
  2551. if (tabla->mbhc_data.micb_mv != VDDIO_MICBIAS_MV) {
  2552. cfilt_k_val = tabla_find_k_value(
  2553. tabla->pdata->micbias.ldoh_v,
  2554. tabla->mbhc_data.micb_mv);
  2555. snd_soc_update_bits(codec,
  2556. tabla->mbhc_bias_regs.cfilt_val,
  2557. 0xFC, (cfilt_k_val << 2));
  2558. usleep_range(cfilt_adjust_ms * 1000,
  2559. cfilt_adjust_ms * 1000);
  2560. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B1_CTL,
  2561. tabla->mbhc_data.v_ins_hu & 0xFF);
  2562. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B2_CTL,
  2563. (tabla->mbhc_data.v_ins_hu >> 8) & 0xFF);
  2564. pr_debug("%s: Programmed MBHC thresholds to MICBIAS\n",
  2565. __func__);
  2566. }
  2567. /* Disable MIC BIAS Switch to VDDIO */
  2568. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg,
  2569. 0x80, 0x00);
  2570. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg,
  2571. 0x10, 0x00);
  2572. if ((!checkpolling || tabla->mbhc_polling_active) &&
  2573. restartpolling)
  2574. tabla_codec_start_hs_polling(codec);
  2575. tabla->mbhc_micbias_switched = false;
  2576. pr_debug("%s: VDDIO switch disabled\n", __func__);
  2577. }
  2578. }
  2579. static void tabla_codec_switch_micbias(struct snd_soc_codec *codec,
  2580. int vddio_switch)
  2581. {
  2582. return __tabla_codec_switch_micbias(codec, vddio_switch, true, true);
  2583. }
  2584. static int tabla_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2585. struct snd_kcontrol *kcontrol, int event)
  2586. {
  2587. struct snd_soc_codec *codec = w->codec;
  2588. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  2589. u16 micb_int_reg;
  2590. int micb_line;
  2591. u8 cfilt_sel_val = 0;
  2592. char *internal1_text = "Internal1";
  2593. char *internal2_text = "Internal2";
  2594. char *internal3_text = "Internal3";
  2595. const char *micbias1_text = "MIC BIAS1 ";
  2596. const char *micbias2_text = "MIC BIAS2 ";
  2597. const char *micbias3_text = "MIC BIAS3 ";
  2598. const char *micbias4_text = "MIC BIAS4 ";
  2599. u32 *micbias_enable_count;
  2600. u16 wreg;
  2601. pr_debug("%s %d\n", __func__, event);
  2602. if (strnstr(w->name, micbias1_text, strlen(micbias1_text))) {
  2603. wreg = TABLA_A_MICB_1_CTL;
  2604. micb_int_reg = TABLA_A_MICB_1_INT_RBIAS;
  2605. cfilt_sel_val = tabla->pdata->micbias.bias1_cfilt_sel;
  2606. micb_line = TABLA_MICBIAS1;
  2607. } else if (strnstr(w->name, micbias2_text, strlen(micbias2_text))) {
  2608. wreg = TABLA_A_MICB_2_CTL;
  2609. micb_int_reg = TABLA_A_MICB_2_INT_RBIAS;
  2610. cfilt_sel_val = tabla->pdata->micbias.bias2_cfilt_sel;
  2611. micb_line = TABLA_MICBIAS2;
  2612. } else if (strnstr(w->name, micbias3_text, strlen(micbias3_text))) {
  2613. wreg = TABLA_A_MICB_3_CTL;
  2614. micb_int_reg = TABLA_A_MICB_3_INT_RBIAS;
  2615. cfilt_sel_val = tabla->pdata->micbias.bias3_cfilt_sel;
  2616. micb_line = TABLA_MICBIAS3;
  2617. } else if (strnstr(w->name, micbias4_text, strlen(micbias4_text))) {
  2618. wreg = tabla->reg_addr.micb_4_ctl;
  2619. micb_int_reg = tabla->reg_addr.micb_4_int_rbias;
  2620. cfilt_sel_val = tabla->pdata->micbias.bias4_cfilt_sel;
  2621. micb_line = TABLA_MICBIAS4;
  2622. } else {
  2623. pr_err("%s: Error, invalid micbias register\n", __func__);
  2624. return -EINVAL;
  2625. }
  2626. micbias_enable_count = &tabla->micbias_enable_count[micb_line];
  2627. pr_debug("%s: counter %d\n", __func__, *micbias_enable_count);
  2628. switch (event) {
  2629. case SND_SOC_DAPM_PRE_PMU:
  2630. if (++*micbias_enable_count > 1) {
  2631. pr_debug("%s: do nothing, counter %d\n",
  2632. __func__, *micbias_enable_count);
  2633. break;
  2634. }
  2635. /* Decide whether to switch the micbias for MBHC */
  2636. if (wreg == tabla->mbhc_bias_regs.ctl_reg) {
  2637. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  2638. tabla_codec_switch_micbias(codec, 0);
  2639. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  2640. }
  2641. snd_soc_update_bits(codec, wreg, 0x0E, 0x0A);
  2642. tabla_codec_update_cfilt_usage(codec, cfilt_sel_val, 1);
  2643. if (strnstr(w->name, internal1_text, 30))
  2644. snd_soc_update_bits(codec, micb_int_reg, 0xE0, 0xE0);
  2645. else if (strnstr(w->name, internal2_text, 30))
  2646. snd_soc_update_bits(codec, micb_int_reg, 0x1C, 0x1C);
  2647. else if (strnstr(w->name, internal3_text, 30))
  2648. snd_soc_update_bits(codec, micb_int_reg, 0x3, 0x3);
  2649. snd_soc_update_bits(codec, wreg, 1 << 7, 1 << 7);
  2650. break;
  2651. case SND_SOC_DAPM_POST_PMU:
  2652. if (*micbias_enable_count > 1) {
  2653. pr_debug("%s: do nothing, counter %d\n",
  2654. __func__, *micbias_enable_count);
  2655. break;
  2656. }
  2657. usleep_range(20000, 20000);
  2658. if (tabla->mbhc_polling_active &&
  2659. tabla->mbhc_cfg.micbias == micb_line) {
  2660. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  2661. tabla_codec_pause_hs_polling(codec);
  2662. tabla_codec_start_hs_polling(codec);
  2663. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  2664. }
  2665. break;
  2666. case SND_SOC_DAPM_POST_PMD:
  2667. if (--*micbias_enable_count > 0) {
  2668. pr_debug("%s: do nothing, counter %d\n",
  2669. __func__, *micbias_enable_count);
  2670. break;
  2671. }
  2672. snd_soc_update_bits(codec, wreg, 1 << 7, 0);
  2673. if ((wreg == tabla->mbhc_bias_regs.ctl_reg) &&
  2674. tabla_is_hph_pa_on(codec)) {
  2675. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  2676. tabla_codec_switch_micbias(codec, 1);
  2677. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  2678. }
  2679. if (strnstr(w->name, internal1_text, 30))
  2680. snd_soc_update_bits(codec, micb_int_reg, 0x80, 0x00);
  2681. else if (strnstr(w->name, internal2_text, 30))
  2682. snd_soc_update_bits(codec, micb_int_reg, 0x10, 0x00);
  2683. else if (strnstr(w->name, internal3_text, 30))
  2684. snd_soc_update_bits(codec, micb_int_reg, 0x2, 0x0);
  2685. tabla_codec_update_cfilt_usage(codec, cfilt_sel_val, 0);
  2686. break;
  2687. }
  2688. return 0;
  2689. }
  2690. static void tx_hpf_corner_freq_callback(struct work_struct *work)
  2691. {
  2692. struct delayed_work *hpf_delayed_work;
  2693. struct hpf_work *hpf_work;
  2694. struct tabla_priv *tabla;
  2695. struct snd_soc_codec *codec;
  2696. u16 tx_mux_ctl_reg;
  2697. u8 hpf_cut_of_freq;
  2698. hpf_delayed_work = to_delayed_work(work);
  2699. hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork);
  2700. tabla = hpf_work->tabla;
  2701. codec = hpf_work->tabla->codec;
  2702. hpf_cut_of_freq = hpf_work->tx_hpf_cut_of_freq;
  2703. tx_mux_ctl_reg = TABLA_A_CDC_TX1_MUX_CTL +
  2704. (hpf_work->decimator - 1) * 8;
  2705. pr_debug("%s(): decimator %u hpf_cut_of_freq 0x%x\n", __func__,
  2706. hpf_work->decimator, (unsigned int)hpf_cut_of_freq);
  2707. snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30, hpf_cut_of_freq << 4);
  2708. }
  2709. static void tx_digital_unmute_callback(struct work_struct *work)
  2710. {
  2711. struct delayed_work *mute_delayed_work;
  2712. struct mute_work *tx_mute_work;
  2713. struct tabla_priv *tabla;
  2714. struct snd_soc_codec *codec;
  2715. u16 tx_vol_ctl_reg;
  2716. mute_delayed_work = to_delayed_work(work);
  2717. tx_mute_work = container_of(mute_delayed_work, struct mute_work, dwork);
  2718. tabla = tx_mute_work->tabla;
  2719. codec = tx_mute_work->tabla->codec;
  2720. tx_vol_ctl_reg = TABLA_A_CDC_TX1_VOL_CTL_CFG +
  2721. (tx_mute_work->decimator - 1) * 8;
  2722. pr_debug("%s(): tabla %p decimator %u tx digital mute 0\n",
  2723. __func__, tx_mute_work->tabla, tx_mute_work->decimator);
  2724. snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x00);
  2725. }
  2726. #define TX_MUX_CTL_CUT_OFF_FREQ_MASK 0x30
  2727. #define CF_MIN_3DB_4HZ 0x0
  2728. #define CF_MIN_3DB_75HZ 0x1
  2729. #define CF_MIN_3DB_150HZ 0x2
  2730. static int tabla_codec_enable_ldo_h(struct snd_soc_dapm_widget *w,
  2731. struct snd_kcontrol *kcontrol, int event);
  2732. static int tabla_codec_enable_micbias_power(struct snd_soc_dapm_widget *w,
  2733. struct snd_kcontrol *kcontrol,
  2734. int event)
  2735. {
  2736. struct snd_soc_codec *codec = w->codec;
  2737. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  2738. pr_debug("%s %d\n", __func__, event);
  2739. switch (event) {
  2740. case SND_SOC_DAPM_PRE_PMU:
  2741. tabla->mbhc_cfg.mclk_cb_fn(codec, 1, true);
  2742. tabla_codec_enable_ldo_h(w, kcontrol, event);
  2743. tabla_codec_enable_micbias(w, kcontrol, event);
  2744. break;
  2745. case SND_SOC_DAPM_POST_PMU:
  2746. tabla->mbhc_cfg.mclk_cb_fn(codec, 0, true);
  2747. break;
  2748. case SND_SOC_DAPM_POST_PMD:
  2749. tabla_codec_enable_micbias(w, kcontrol, event);
  2750. tabla_codec_enable_ldo_h(w, kcontrol, event);
  2751. break;
  2752. }
  2753. return 0;
  2754. }
  2755. static int tabla_codec_enable_dec(struct snd_soc_dapm_widget *w,
  2756. struct snd_kcontrol *kcontrol, int event)
  2757. {
  2758. struct snd_soc_codec *codec = w->codec;
  2759. unsigned int decimator;
  2760. char *dec_name = NULL;
  2761. char *widget_name = NULL;
  2762. char *temp;
  2763. int ret = 0;
  2764. u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg;
  2765. u8 dec_hpf_cut_of_freq;
  2766. int offset;
  2767. pr_debug("%s %d\n", __func__, event);
  2768. widget_name = kstrndup(w->name, 15, GFP_KERNEL);
  2769. if (!widget_name)
  2770. return -ENOMEM;
  2771. temp = widget_name;
  2772. dec_name = strsep(&widget_name, " ");
  2773. widget_name = temp;
  2774. if (!dec_name) {
  2775. pr_err("%s: Invalid decimator = %s\n", __func__, w->name);
  2776. ret = -EINVAL;
  2777. goto out;
  2778. }
  2779. ret = kstrtouint(strpbrk(dec_name, "123456789"), 10, &decimator);
  2780. if (ret < 0) {
  2781. pr_err("%s: Invalid decimator = %s\n", __func__, dec_name);
  2782. ret = -EINVAL;
  2783. goto out;
  2784. }
  2785. pr_debug("%s(): widget = %s dec_name = %s decimator = %u\n", __func__,
  2786. w->name, dec_name, decimator);
  2787. if (w->reg == TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL) {
  2788. dec_reset_reg = TABLA_A_CDC_CLK_TX_RESET_B1_CTL;
  2789. offset = 0;
  2790. } else if (w->reg == TABLA_A_CDC_CLK_TX_CLK_EN_B2_CTL) {
  2791. dec_reset_reg = TABLA_A_CDC_CLK_TX_RESET_B2_CTL;
  2792. offset = 8;
  2793. } else {
  2794. pr_err("%s: Error, incorrect dec\n", __func__);
  2795. return -EINVAL;
  2796. }
  2797. tx_vol_ctl_reg = TABLA_A_CDC_TX1_VOL_CTL_CFG + 8 * (decimator -1);
  2798. tx_mux_ctl_reg = TABLA_A_CDC_TX1_MUX_CTL + 8 * (decimator - 1);
  2799. switch (event) {
  2800. case SND_SOC_DAPM_PRE_PMU:
  2801. // Enableable TX digital mute */
  2802. snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01);
  2803. snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift,
  2804. 1 << w->shift);
  2805. snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift, 0x0);
  2806. dec_hpf_cut_of_freq = snd_soc_read(codec, tx_mux_ctl_reg);
  2807. dec_hpf_cut_of_freq = (dec_hpf_cut_of_freq & 0x30) >> 4;
  2808. tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq =
  2809. dec_hpf_cut_of_freq;
  2810. if ((dec_hpf_cut_of_freq != CF_MIN_3DB_150HZ)) {
  2811. /* set cut of freq to CF_MIN_3DB_150HZ (0x1); */
  2812. snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30,
  2813. CF_MIN_3DB_150HZ << 4);
  2814. }
  2815. /* enable HPF */
  2816. snd_soc_update_bits(codec, tx_mux_ctl_reg , 0x08, 0x00);
  2817. break;
  2818. case SND_SOC_DAPM_POST_PMU:
  2819. /* Disable TX digital mute */
  2820. schedule_delayed_work(
  2821. &tx_mute_work[decimator - 1].dwork,
  2822. msecs_to_jiffies(100));
  2823. if (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq !=
  2824. CF_MIN_3DB_150HZ) {
  2825. schedule_delayed_work(&tx_hpf_work[decimator - 1].dwork,
  2826. msecs_to_jiffies(300));
  2827. }
  2828. /* apply the digital gain after the decimator is enabled*/
  2829. if ((w->shift + offset) < ARRAY_SIZE(tx_digital_gain_reg))
  2830. snd_soc_write(codec,
  2831. tx_digital_gain_reg[w->shift + offset],
  2832. snd_soc_read(codec,
  2833. tx_digital_gain_reg[w->shift + offset])
  2834. );
  2835. break;
  2836. case SND_SOC_DAPM_PRE_PMD:
  2837. snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01);
  2838. cancel_delayed_work_sync(&tx_hpf_work[decimator - 1].dwork);
  2839. cancel_delayed_work_sync(&tx_mute_work[decimator - 1].dwork);
  2840. break;
  2841. case SND_SOC_DAPM_POST_PMD:
  2842. snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x08, 0x08);
  2843. snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30,
  2844. (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq) << 4);
  2845. break;
  2846. }
  2847. out:
  2848. kfree(widget_name);
  2849. return ret;
  2850. }
  2851. static int tabla_codec_reset_interpolator(struct snd_soc_dapm_widget *w,
  2852. struct snd_kcontrol *kcontrol, int event)
  2853. {
  2854. struct snd_soc_codec *codec = w->codec;
  2855. pr_debug("%s %d %s\n", __func__, event, w->name);
  2856. switch (event) {
  2857. case SND_SOC_DAPM_PRE_PMU:
  2858. snd_soc_update_bits(codec, TABLA_A_CDC_CLK_RX_RESET_CTL,
  2859. 1 << w->shift, 1 << w->shift);
  2860. snd_soc_update_bits(codec, TABLA_A_CDC_CLK_RX_RESET_CTL,
  2861. 1 << w->shift, 0x0);
  2862. break;
  2863. case SND_SOC_DAPM_POST_PMU:
  2864. /* apply the digital gain after the interpolator is enabled*/
  2865. if ((w->shift) < ARRAY_SIZE(rx_digital_gain_reg))
  2866. snd_soc_write(codec,
  2867. rx_digital_gain_reg[w->shift],
  2868. snd_soc_read(codec,
  2869. rx_digital_gain_reg[w->shift])
  2870. );
  2871. break;
  2872. }
  2873. return 0;
  2874. }
  2875. static void tabla_enable_ldo_h(struct snd_soc_codec *codec, u32 enable)
  2876. {
  2877. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  2878. if (enable) {
  2879. if (++tabla->ldo_h_count == 1)
  2880. snd_soc_update_bits(codec, TABLA_A_LDO_H_MODE_1,
  2881. 0x80, 0x80);
  2882. } else {
  2883. if (--tabla->ldo_h_count == 0)
  2884. snd_soc_update_bits(codec, TABLA_A_LDO_H_MODE_1,
  2885. 0x80, 0x00);
  2886. }
  2887. }
  2888. static int tabla_codec_enable_ldo_h(struct snd_soc_dapm_widget *w,
  2889. struct snd_kcontrol *kcontrol, int event)
  2890. {
  2891. struct snd_soc_codec *codec = w->codec;
  2892. pr_debug("%s %d\n", __func__, event);
  2893. switch (event) {
  2894. case SND_SOC_DAPM_PRE_PMU:
  2895. tabla_enable_ldo_h(codec, 1);
  2896. usleep_range(1000, 1000);
  2897. break;
  2898. case SND_SOC_DAPM_POST_PMD:
  2899. tabla_enable_ldo_h(codec, 0);
  2900. usleep_range(1000, 1000);
  2901. break;
  2902. }
  2903. return 0;
  2904. }
  2905. static int tabla_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
  2906. struct snd_kcontrol *kcontrol, int event)
  2907. {
  2908. struct snd_soc_codec *codec = w->codec;
  2909. pr_debug("%s %d\n", __func__, event);
  2910. switch (event) {
  2911. case SND_SOC_DAPM_PRE_PMU:
  2912. tabla_enable_rx_bias(codec, 1);
  2913. break;
  2914. case SND_SOC_DAPM_POST_PMD:
  2915. tabla_enable_rx_bias(codec, 0);
  2916. break;
  2917. }
  2918. return 0;
  2919. }
  2920. static int tabla_hphr_dac_event(struct snd_soc_dapm_widget *w,
  2921. struct snd_kcontrol *kcontrol, int event)
  2922. {
  2923. struct snd_soc_codec *codec = w->codec;
  2924. pr_debug("%s %s %d\n", __func__, w->name, event);
  2925. switch (event) {
  2926. case SND_SOC_DAPM_PRE_PMU:
  2927. snd_soc_update_bits(codec, w->reg, 0x40, 0x40);
  2928. break;
  2929. case SND_SOC_DAPM_POST_PMD:
  2930. snd_soc_update_bits(codec, w->reg, 0x40, 0x00);
  2931. break;
  2932. }
  2933. return 0;
  2934. }
  2935. static void tabla_snd_soc_jack_report(struct tabla_priv *tabla,
  2936. struct snd_soc_jack *jack, int status,
  2937. int mask)
  2938. {
  2939. /* XXX: wake_lock_timeout()? */
  2940. snd_soc_jack_report_no_dapm(jack, status, mask);
  2941. }
  2942. static void hphocp_off_report(struct tabla_priv *tabla,
  2943. u32 jack_status, int irq)
  2944. {
  2945. struct snd_soc_codec *codec;
  2946. if (!tabla) {
  2947. pr_err("%s: Bad tabla private data\n", __func__);
  2948. return;
  2949. }
  2950. pr_debug("%s: clear ocp status %x\n", __func__, jack_status);
  2951. codec = tabla->codec;
  2952. if (tabla->hph_status & jack_status) {
  2953. tabla->hph_status &= ~jack_status;
  2954. if (tabla->mbhc_cfg.headset_jack)
  2955. tabla_snd_soc_jack_report(tabla,
  2956. tabla->mbhc_cfg.headset_jack,
  2957. tabla->hph_status,
  2958. TABLA_JACK_MASK);
  2959. snd_soc_update_bits(codec, TABLA_A_RX_HPH_OCP_CTL, 0x10, 0x00);
  2960. snd_soc_update_bits(codec, TABLA_A_RX_HPH_OCP_CTL, 0x10, 0x10);
  2961. /* reset retry counter as PA is turned off signifying
  2962. * start of new OCP detection session
  2963. */
  2964. if (WCD9XXX_IRQ_HPH_PA_OCPL_FAULT)
  2965. tabla->hphlocp_cnt = 0;
  2966. else
  2967. tabla->hphrocp_cnt = 0;
  2968. wcd9xxx_enable_irq(codec->control_data, irq);
  2969. }
  2970. }
  2971. static void hphlocp_off_report(struct work_struct *work)
  2972. {
  2973. struct tabla_priv *tabla = container_of(work, struct tabla_priv,
  2974. hphlocp_work);
  2975. hphocp_off_report(tabla, SND_JACK_OC_HPHL,
  2976. WCD9XXX_IRQ_HPH_PA_OCPL_FAULT);
  2977. }
  2978. static void hphrocp_off_report(struct work_struct *work)
  2979. {
  2980. struct tabla_priv *tabla = container_of(work, struct tabla_priv,
  2981. hphrocp_work);
  2982. hphocp_off_report(tabla, SND_JACK_OC_HPHR,
  2983. WCD9XXX_IRQ_HPH_PA_OCPR_FAULT);
  2984. }
  2985. static int tabla_codec_enable_anc(struct snd_soc_dapm_widget *w,
  2986. struct snd_kcontrol *kcontrol, int event)
  2987. {
  2988. struct snd_soc_codec *codec = w->codec;
  2989. const char *filename;
  2990. const struct firmware *fw;
  2991. int i;
  2992. int ret;
  2993. int num_anc_slots;
  2994. struct anc_header *anc_head;
  2995. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  2996. u32 anc_writes_size = 0;
  2997. int anc_size_remaining;
  2998. u32 *anc_ptr;
  2999. u16 reg;
  3000. u8 mask, val, old_val;
  3001. u8 mbhc_micb_ctl_val;
  3002. pr_debug("%s: DAPM Event %d ANC func is %d\n",
  3003. __func__, event, tabla->anc_func);
  3004. if (tabla->anc_func == 0)
  3005. return 0;
  3006. switch (event) {
  3007. case SND_SOC_DAPM_PRE_PMU:
  3008. mbhc_micb_ctl_val = snd_soc_read(codec,
  3009. tabla->mbhc_bias_regs.ctl_reg);
  3010. if (!(mbhc_micb_ctl_val & 0x80)) {
  3011. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  3012. tabla_codec_switch_micbias(codec, 1);
  3013. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  3014. }
  3015. filename = "wcd9310/wcd9310_anc.bin";
  3016. ret = request_firmware(&fw, filename, codec->dev);
  3017. if (ret != 0) {
  3018. dev_err(codec->dev, "Failed to acquire ANC data: %d\n",
  3019. ret);
  3020. return -ENODEV;
  3021. }
  3022. if (fw->size < sizeof(struct anc_header)) {
  3023. dev_err(codec->dev, "Not enough data\n");
  3024. release_firmware(fw);
  3025. return -ENOMEM;
  3026. }
  3027. /* First number is the number of register writes */
  3028. anc_head = (struct anc_header *)(fw->data);
  3029. anc_ptr = (u32 *)((u32)fw->data + sizeof(struct anc_header));
  3030. anc_size_remaining = fw->size - sizeof(struct anc_header);
  3031. num_anc_slots = anc_head->num_anc_slots;
  3032. if (tabla->anc_slot >= num_anc_slots) {
  3033. dev_err(codec->dev, "Invalid ANC slot selected\n");
  3034. release_firmware(fw);
  3035. return -EINVAL;
  3036. }
  3037. for (i = 0; i < num_anc_slots; i++) {
  3038. if (anc_size_remaining < TABLA_PACKED_REG_SIZE) {
  3039. dev_err(codec->dev, "Invalid register format\n");
  3040. release_firmware(fw);
  3041. return -EINVAL;
  3042. }
  3043. anc_writes_size = (u32)(*anc_ptr);
  3044. anc_size_remaining -= sizeof(u32);
  3045. anc_ptr += 1;
  3046. if (anc_writes_size * TABLA_PACKED_REG_SIZE
  3047. > anc_size_remaining) {
  3048. dev_err(codec->dev, "Invalid register format\n");
  3049. release_firmware(fw);
  3050. return -ENOMEM;
  3051. }
  3052. if (tabla->anc_slot == i)
  3053. break;
  3054. anc_size_remaining -= (anc_writes_size *
  3055. TABLA_PACKED_REG_SIZE);
  3056. anc_ptr += anc_writes_size;
  3057. }
  3058. if (i == num_anc_slots) {
  3059. dev_err(codec->dev, "Selected ANC slot not present\n");
  3060. release_firmware(fw);
  3061. return -ENOMEM;
  3062. }
  3063. for (i = 0; i < anc_writes_size; i++) {
  3064. TABLA_CODEC_UNPACK_ENTRY(anc_ptr[i], reg,
  3065. mask, val);
  3066. old_val = snd_soc_read(codec, reg);
  3067. snd_soc_write(codec, reg, (old_val & ~mask) |
  3068. (val & mask));
  3069. }
  3070. usleep_range(10000, 10000);
  3071. snd_soc_update_bits(codec, TABLA_A_RX_HPH_CNP_EN, 0x30, 0x30);
  3072. msleep(30);
  3073. release_firmware(fw);
  3074. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  3075. /* if MBHC polling is active, set TX7_MBHC_EN bit 7 */
  3076. if (tabla->mbhc_polling_active)
  3077. snd_soc_update_bits(codec, TABLA_A_TX_7_MBHC_EN, 0x80,
  3078. 0x80);
  3079. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  3080. break;
  3081. case SND_SOC_DAPM_POST_PMD:
  3082. /* schedule work is required because at the time HPH PA DAPM
  3083. * event callback is called by DAPM framework, CODEC dapm mutex
  3084. * would have been locked while snd_soc_jack_report also
  3085. * attempts to acquire same lock.
  3086. */
  3087. if (w->shift == 5) {
  3088. clear_bit(TABLA_HPHL_PA_OFF_ACK,
  3089. &tabla->hph_pa_dac_state);
  3090. clear_bit(TABLA_HPHL_DAC_OFF_ACK,
  3091. &tabla->hph_pa_dac_state);
  3092. if (tabla->hph_status & SND_JACK_OC_HPHL)
  3093. schedule_work(&tabla->hphlocp_work);
  3094. } else if (w->shift == 4) {
  3095. clear_bit(TABLA_HPHR_PA_OFF_ACK,
  3096. &tabla->hph_pa_dac_state);
  3097. clear_bit(TABLA_HPHR_DAC_OFF_ACK,
  3098. &tabla->hph_pa_dac_state);
  3099. if (tabla->hph_status & SND_JACK_OC_HPHR)
  3100. schedule_work(&tabla->hphrocp_work);
  3101. }
  3102. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  3103. tabla_codec_switch_micbias(codec, 0);
  3104. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  3105. break;
  3106. case SND_SOC_DAPM_PRE_PMD:
  3107. snd_soc_update_bits(codec, TABLA_A_RX_HPH_CNP_EN, 0x30, 0x00);
  3108. msleep(40);
  3109. /* unset TX7_MBHC_EN bit 7 */
  3110. snd_soc_update_bits(codec, TABLA_A_TX_7_MBHC_EN, 0x80, 0x00);
  3111. snd_soc_update_bits(codec, TABLA_A_CDC_ANC1_CTL, 0x01, 0x00);
  3112. snd_soc_update_bits(codec, TABLA_A_CDC_ANC2_CTL, 0x01, 0x00);
  3113. msleep(20);
  3114. snd_soc_write(codec, TABLA_A_CDC_CLK_ANC_RESET_CTL, 0x0F);
  3115. snd_soc_write(codec, TABLA_A_CDC_CLK_ANC_CLK_EN_CTL, 0);
  3116. snd_soc_write(codec, TABLA_A_CDC_CLK_ANC_RESET_CTL, 0xFF);
  3117. break;
  3118. }
  3119. return 0;
  3120. }
  3121. static int tabla_hph_pa_event(struct snd_soc_dapm_widget *w,
  3122. struct snd_kcontrol *kcontrol, int event)
  3123. {
  3124. struct snd_soc_codec *codec = w->codec;
  3125. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  3126. u8 mbhc_micb_ctl_val;
  3127. pr_debug("%s: event = %d\n", __func__, event);
  3128. switch (event) {
  3129. case SND_SOC_DAPM_PRE_PMU:
  3130. mbhc_micb_ctl_val = snd_soc_read(codec,
  3131. tabla->mbhc_bias_regs.ctl_reg);
  3132. if (!(mbhc_micb_ctl_val & 0x80)) {
  3133. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  3134. tabla_codec_switch_micbias(codec, 1);
  3135. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  3136. }
  3137. break;
  3138. case SND_SOC_DAPM_POST_PMD:
  3139. /* schedule work is required because at the time HPH PA DAPM
  3140. * event callback is called by DAPM framework, CODEC dapm mutex
  3141. * would have been locked while snd_soc_jack_report also
  3142. * attempts to acquire same lock.
  3143. */
  3144. if (w->shift == 5) {
  3145. clear_bit(TABLA_HPHL_PA_OFF_ACK,
  3146. &tabla->hph_pa_dac_state);
  3147. clear_bit(TABLA_HPHL_DAC_OFF_ACK,
  3148. &tabla->hph_pa_dac_state);
  3149. if (tabla->hph_status & SND_JACK_OC_HPHL)
  3150. schedule_work(&tabla->hphlocp_work);
  3151. } else if (w->shift == 4) {
  3152. clear_bit(TABLA_HPHR_PA_OFF_ACK,
  3153. &tabla->hph_pa_dac_state);
  3154. clear_bit(TABLA_HPHR_DAC_OFF_ACK,
  3155. &tabla->hph_pa_dac_state);
  3156. if (tabla->hph_status & SND_JACK_OC_HPHR)
  3157. schedule_work(&tabla->hphrocp_work);
  3158. }
  3159. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  3160. tabla_codec_switch_micbias(codec, 0);
  3161. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  3162. pr_debug("%s: sleep 10 ms after %s PA disable.\n", __func__,
  3163. w->name);
  3164. usleep_range(10000, 10000);
  3165. break;
  3166. }
  3167. return 0;
  3168. }
  3169. static void tabla_get_mbhc_micbias_regs(struct snd_soc_codec *codec,
  3170. struct mbhc_micbias_regs *micbias_regs)
  3171. {
  3172. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  3173. unsigned int cfilt;
  3174. switch (tabla->mbhc_cfg.micbias) {
  3175. case TABLA_MICBIAS1:
  3176. cfilt = tabla->pdata->micbias.bias1_cfilt_sel;
  3177. micbias_regs->mbhc_reg = TABLA_A_MICB_1_MBHC;
  3178. micbias_regs->int_rbias = TABLA_A_MICB_1_INT_RBIAS;
  3179. micbias_regs->ctl_reg = TABLA_A_MICB_1_CTL;
  3180. break;
  3181. case TABLA_MICBIAS2:
  3182. cfilt = tabla->pdata->micbias.bias2_cfilt_sel;
  3183. micbias_regs->mbhc_reg = TABLA_A_MICB_2_MBHC;
  3184. micbias_regs->int_rbias = TABLA_A_MICB_2_INT_RBIAS;
  3185. micbias_regs->ctl_reg = TABLA_A_MICB_2_CTL;
  3186. break;
  3187. case TABLA_MICBIAS3:
  3188. cfilt = tabla->pdata->micbias.bias3_cfilt_sel;
  3189. micbias_regs->mbhc_reg = TABLA_A_MICB_3_MBHC;
  3190. micbias_regs->int_rbias = TABLA_A_MICB_3_INT_RBIAS;
  3191. micbias_regs->ctl_reg = TABLA_A_MICB_3_CTL;
  3192. break;
  3193. case TABLA_MICBIAS4:
  3194. cfilt = tabla->pdata->micbias.bias4_cfilt_sel;
  3195. micbias_regs->mbhc_reg = tabla->reg_addr.micb_4_mbhc;
  3196. micbias_regs->int_rbias = tabla->reg_addr.micb_4_int_rbias;
  3197. micbias_regs->ctl_reg = tabla->reg_addr.micb_4_ctl;
  3198. break;
  3199. default:
  3200. /* Should never reach here */
  3201. pr_err("%s: Invalid MIC BIAS for MBHC\n", __func__);
  3202. return;
  3203. }
  3204. micbias_regs->cfilt_sel = cfilt;
  3205. switch (cfilt) {
  3206. case TABLA_CFILT1_SEL:
  3207. micbias_regs->cfilt_val = TABLA_A_MICB_CFILT_1_VAL;
  3208. micbias_regs->cfilt_ctl = TABLA_A_MICB_CFILT_1_CTL;
  3209. tabla->mbhc_data.micb_mv = tabla->pdata->micbias.cfilt1_mv;
  3210. break;
  3211. case TABLA_CFILT2_SEL:
  3212. micbias_regs->cfilt_val = TABLA_A_MICB_CFILT_2_VAL;
  3213. micbias_regs->cfilt_ctl = TABLA_A_MICB_CFILT_2_CTL;
  3214. tabla->mbhc_data.micb_mv = tabla->pdata->micbias.cfilt2_mv;
  3215. break;
  3216. case TABLA_CFILT3_SEL:
  3217. micbias_regs->cfilt_val = TABLA_A_MICB_CFILT_3_VAL;
  3218. micbias_regs->cfilt_ctl = TABLA_A_MICB_CFILT_3_CTL;
  3219. tabla->mbhc_data.micb_mv = tabla->pdata->micbias.cfilt3_mv;
  3220. break;
  3221. }
  3222. }
  3223. static const struct snd_soc_dapm_widget tabla_dapm_i2s_widgets[] = {
  3224. SND_SOC_DAPM_SUPPLY("RX_I2S_CLK", TABLA_A_CDC_CLK_RX_I2S_CTL,
  3225. 4, 0, NULL, 0),
  3226. SND_SOC_DAPM_SUPPLY("TX_I2S_CLK", TABLA_A_CDC_CLK_TX_I2S_CTL, 4,
  3227. 0, NULL, 0),
  3228. };
  3229. static int tabla_lineout_dac_event(struct snd_soc_dapm_widget *w,
  3230. struct snd_kcontrol *kcontrol, int event)
  3231. {
  3232. struct snd_soc_codec *codec = w->codec;
  3233. pr_debug("%s %s %d\n", __func__, w->name, event);
  3234. switch (event) {
  3235. case SND_SOC_DAPM_PRE_PMU:
  3236. snd_soc_update_bits(codec, w->reg, 0x40, 0x40);
  3237. break;
  3238. case SND_SOC_DAPM_POST_PMD:
  3239. snd_soc_update_bits(codec, w->reg, 0x40, 0x00);
  3240. break;
  3241. }
  3242. return 0;
  3243. }
  3244. static int tabla_ear_pa_event(struct snd_soc_dapm_widget *w,
  3245. struct snd_kcontrol *kcontrol, int event)
  3246. {
  3247. struct snd_soc_codec *codec = w->codec;
  3248. pr_debug("%s %d\n", __func__, event);
  3249. switch (event) {
  3250. case SND_SOC_DAPM_PRE_PMU:
  3251. snd_soc_update_bits(codec, TABLA_A_RX_EAR_EN, 0x50, 0x50);
  3252. break;
  3253. case SND_SOC_DAPM_PRE_PMD:
  3254. snd_soc_update_bits(codec, TABLA_A_RX_EAR_EN, 0x10, 0x00);
  3255. snd_soc_update_bits(codec, TABLA_A_RX_EAR_EN, 0x40, 0x00);
  3256. break;
  3257. }
  3258. return 0;
  3259. }
  3260. static const struct snd_soc_dapm_widget tabla_1_x_dapm_widgets[] = {
  3261. SND_SOC_DAPM_MICBIAS_E("MIC BIAS4 External", SND_SOC_NOPM, 0,
  3262. 0, tabla_codec_enable_micbias,
  3263. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3264. SND_SOC_DAPM_POST_PMD),
  3265. };
  3266. static const struct snd_soc_dapm_widget tabla_2_higher_dapm_widgets[] = {
  3267. SND_SOC_DAPM_MICBIAS_E("MIC BIAS4 External", SND_SOC_NOPM, 0,
  3268. 0, tabla_codec_enable_micbias,
  3269. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3270. SND_SOC_DAPM_POST_PMD),
  3271. };
  3272. static const struct snd_soc_dapm_route audio_i2s_map[] = {
  3273. {"RX_I2S_CLK", NULL, "CDC_CONN"},
  3274. {"SLIM RX1", NULL, "RX_I2S_CLK"},
  3275. {"SLIM RX2", NULL, "RX_I2S_CLK"},
  3276. {"SLIM RX3", NULL, "RX_I2S_CLK"},
  3277. {"SLIM RX4", NULL, "RX_I2S_CLK"},
  3278. {"SLIM TX7", NULL, "TX_I2S_CLK"},
  3279. {"SLIM TX8", NULL, "TX_I2S_CLK"},
  3280. {"SLIM TX9", NULL, "TX_I2S_CLK"},
  3281. {"SLIM TX10", NULL, "TX_I2S_CLK"},
  3282. };
  3283. static const struct snd_soc_dapm_route audio_map[] = {
  3284. /* SLIMBUS Connections */
  3285. {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
  3286. {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
  3287. {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
  3288. /* SLIM_MIXER("AIF1_CAP Mixer"),*/
  3289. {"AIF1_CAP Mixer", "SLIM TX1", "SLIM TX1 MUX"},
  3290. {"AIF1_CAP Mixer", "SLIM TX2", "SLIM TX2 MUX"},
  3291. {"AIF1_CAP Mixer", "SLIM TX3", "SLIM TX3 MUX"},
  3292. {"AIF1_CAP Mixer", "SLIM TX4", "SLIM TX4 MUX"},
  3293. {"AIF1_CAP Mixer", "SLIM TX5", "SLIM TX5 MUX"},
  3294. {"AIF1_CAP Mixer", "SLIM TX6", "SLIM TX6 MUX"},
  3295. {"AIF1_CAP Mixer", "SLIM TX7", "SLIM TX7 MUX"},
  3296. {"AIF1_CAP Mixer", "SLIM TX8", "SLIM TX8 MUX"},
  3297. {"AIF1_CAP Mixer", "SLIM TX9", "SLIM TX9 MUX"},
  3298. {"AIF1_CAP Mixer", "SLIM TX10", "SLIM TX10 MUX"},
  3299. /* SLIM_MIXER("AIF2_CAP Mixer"),*/
  3300. {"AIF2_CAP Mixer", "SLIM TX1", "SLIM TX1 MUX"},
  3301. {"AIF2_CAP Mixer", "SLIM TX2", "SLIM TX2 MUX"},
  3302. {"AIF2_CAP Mixer", "SLIM TX3", "SLIM TX3 MUX"},
  3303. {"AIF2_CAP Mixer", "SLIM TX4", "SLIM TX4 MUX"},
  3304. {"AIF2_CAP Mixer", "SLIM TX5", "SLIM TX5 MUX"},
  3305. {"AIF2_CAP Mixer", "SLIM TX6", "SLIM TX6 MUX"},
  3306. {"AIF2_CAP Mixer", "SLIM TX7", "SLIM TX7 MUX"},
  3307. {"AIF2_CAP Mixer", "SLIM TX8", "SLIM TX8 MUX"},
  3308. {"AIF2_CAP Mixer", "SLIM TX9", "SLIM TX9 MUX"},
  3309. {"AIF2_CAP Mixer", "SLIM TX10", "SLIM TX10 MUX"},
  3310. /* SLIM_MIXER("AIF3_CAP Mixer"),*/
  3311. {"AIF3_CAP Mixer", "SLIM TX1", "SLIM TX1 MUX"},
  3312. {"AIF3_CAP Mixer", "SLIM TX2", "SLIM TX2 MUX"},
  3313. {"AIF3_CAP Mixer", "SLIM TX3", "SLIM TX3 MUX"},
  3314. {"AIF3_CAP Mixer", "SLIM TX4", "SLIM TX4 MUX"},
  3315. {"AIF3_CAP Mixer", "SLIM TX5", "SLIM TX5 MUX"},
  3316. {"AIF3_CAP Mixer", "SLIM TX6", "SLIM TX6 MUX"},
  3317. {"AIF3_CAP Mixer", "SLIM TX7", "SLIM TX7 MUX"},
  3318. {"AIF3_CAP Mixer", "SLIM TX8", "SLIM TX8 MUX"},
  3319. {"AIF3_CAP Mixer", "SLIM TX9", "SLIM TX9 MUX"},
  3320. {"AIF3_CAP Mixer", "SLIM TX10", "SLIM TX10 MUX"},
  3321. {"SLIM TX1 MUX", "DEC1", "DEC1 MUX"},
  3322. {"SLIM TX2 MUX", "DEC2", "DEC2 MUX"},
  3323. {"SLIM TX3 MUX", "DEC3", "DEC3 MUX"},
  3324. {"SLIM TX3 MUX", "RMIX1", "RX1 MIX1"},
  3325. {"SLIM TX3 MUX", "RMIX2", "RX2 MIX1"},
  3326. {"SLIM TX3 MUX", "RMIX3", "RX3 MIX1"},
  3327. {"SLIM TX3 MUX", "RMIX4", "RX4 MIX1"},
  3328. {"SLIM TX3 MUX", "RMIX5", "RX5 MIX1"},
  3329. {"SLIM TX3 MUX", "RMIX6", "RX6 MIX1"},
  3330. {"SLIM TX3 MUX", "RMIX7", "RX7 MIX1"},
  3331. {"SLIM TX4 MUX", "DEC4", "DEC4 MUX"},
  3332. {"SLIM TX5 MUX", "DEC5", "DEC5 MUX"},
  3333. {"SLIM TX5 MUX", "RMIX1", "RX1 MIX1"},
  3334. {"SLIM TX5 MUX", "RMIX2", "RX2 MIX1"},
  3335. {"SLIM TX5 MUX", "RMIX3", "RX3 MIX1"},
  3336. {"SLIM TX5 MUX", "RMIX4", "RX4 MIX1"},
  3337. {"SLIM TX5 MUX", "RMIX5", "RX5 MIX1"},
  3338. {"SLIM TX5 MUX", "RMIX6", "RX6 MIX1"},
  3339. {"SLIM TX5 MUX", "RMIX7", "RX7 MIX1"},
  3340. {"SLIM TX6 MUX", "DEC6", "DEC6 MUX"},
  3341. {"SLIM TX7 MUX", "DEC1", "DEC1 MUX"},
  3342. {"SLIM TX7 MUX", "DEC2", "DEC2 MUX"},
  3343. {"SLIM TX7 MUX", "DEC3", "DEC3 MUX"},
  3344. {"SLIM TX7 MUX", "DEC4", "DEC4 MUX"},
  3345. {"SLIM TX7 MUX", "DEC5", "DEC5 MUX"},
  3346. {"SLIM TX7 MUX", "DEC6", "DEC6 MUX"},
  3347. {"SLIM TX7 MUX", "DEC7", "DEC7 MUX"},
  3348. {"SLIM TX7 MUX", "DEC8", "DEC8 MUX"},
  3349. {"SLIM TX7 MUX", "DEC9", "DEC9 MUX"},
  3350. {"SLIM TX7 MUX", "DEC10", "DEC10 MUX"},
  3351. {"SLIM TX7 MUX", "RMIX1", "RX1 MIX1"},
  3352. {"SLIM TX7 MUX", "RMIX2", "RX2 MIX1"},
  3353. {"SLIM TX7 MUX", "RMIX3", "RX3 MIX1"},
  3354. {"SLIM TX7 MUX", "RMIX4", "RX4 MIX1"},
  3355. {"SLIM TX7 MUX", "RMIX5", "RX5 MIX1"},
  3356. {"SLIM TX7 MUX", "RMIX6", "RX6 MIX1"},
  3357. {"SLIM TX7 MUX", "RMIX7", "RX7 MIX1"},
  3358. {"SLIM TX8 MUX", "DEC1", "DEC1 MUX"},
  3359. {"SLIM TX8 MUX", "DEC2", "DEC2 MUX"},
  3360. {"SLIM TX8 MUX", "DEC3", "DEC3 MUX"},
  3361. {"SLIM TX8 MUX", "DEC4", "DEC4 MUX"},
  3362. {"SLIM TX8 MUX", "DEC5", "DEC5 MUX"},
  3363. {"SLIM TX8 MUX", "DEC6", "DEC6 MUX"},
  3364. {"SLIM TX8 MUX", "DEC7", "DEC7 MUX"},
  3365. {"SLIM TX8 MUX", "DEC8", "DEC8 MUX"},
  3366. {"SLIM TX8 MUX", "DEC9", "DEC9 MUX"},
  3367. {"SLIM TX8 MUX", "DEC10", "DEC10 MUX"},
  3368. {"SLIM TX9 MUX", "DEC1", "DEC1 MUX"},
  3369. {"SLIM TX9 MUX", "DEC2", "DEC2 MUX"},
  3370. {"SLIM TX9 MUX", "DEC3", "DEC3 MUX"},
  3371. {"SLIM TX9 MUX", "DEC4", "DEC4 MUX"},
  3372. {"SLIM TX9 MUX", "DEC5", "DEC5 MUX"},
  3373. {"SLIM TX9 MUX", "DEC6", "DEC6 MUX"},
  3374. {"SLIM TX9 MUX", "DEC7", "DEC7 MUX"},
  3375. {"SLIM TX9 MUX", "DEC8", "DEC8 MUX"},
  3376. {"SLIM TX9 MUX", "DEC9", "DEC9 MUX"},
  3377. {"SLIM TX9 MUX", "DEC10", "DEC10 MUX"},
  3378. {"SLIM TX10 MUX", "DEC1", "DEC1 MUX"},
  3379. {"SLIM TX10 MUX", "DEC2", "DEC2 MUX"},
  3380. {"SLIM TX10 MUX", "DEC3", "DEC3 MUX"},
  3381. {"SLIM TX10 MUX", "DEC4", "DEC4 MUX"},
  3382. {"SLIM TX10 MUX", "DEC5", "DEC5 MUX"},
  3383. {"SLIM TX10 MUX", "DEC6", "DEC6 MUX"},
  3384. {"SLIM TX10 MUX", "DEC7", "DEC7 MUX"},
  3385. {"SLIM TX10 MUX", "DEC8", "DEC8 MUX"},
  3386. {"SLIM TX10 MUX", "DEC9", "DEC9 MUX"},
  3387. {"SLIM TX10 MUX", "DEC10", "DEC10 MUX"},
  3388. /* Earpiece (RX MIX1) */
  3389. {"EAR", NULL, "EAR PA"},
  3390. {"EAR PA", NULL, "EAR_PA_MIXER"},
  3391. {"EAR_PA_MIXER", NULL, "DAC1"},
  3392. {"DAC1", NULL, "CP"},
  3393. {"ANC1 FB MUX", "EAR_HPH_L", "RX1 MIX2"},
  3394. {"ANC1 FB MUX", "EAR_LINE_1", "RX2 MIX2"},
  3395. /* Headset (RX MIX1 and RX MIX2) */
  3396. {"HEADPHONE", NULL, "HPHL"},
  3397. {"HEADPHONE", NULL, "HPHR"},
  3398. {"HPHL", NULL, "HPHL_PA_MIXER"},
  3399. {"HPHL_PA_MIXER", NULL, "HPHL DAC"},
  3400. {"HPHR", NULL, "HPHR_PA_MIXER"},
  3401. {"HPHR_PA_MIXER", NULL, "HPHR DAC"},
  3402. {"HPHL DAC", NULL, "CP"},
  3403. {"HPHR DAC", NULL, "CP"},
  3404. {"ANC HEADPHONE", NULL, "ANC HPHL"},
  3405. {"ANC HEADPHONE", NULL, "ANC HPHR"},
  3406. {"ANC HPHL", NULL, "HPHL_PA_MIXER"},
  3407. {"ANC HPHR", NULL, "HPHR_PA_MIXER"},
  3408. {"ANC1 MUX", "ADC1", "ADC1"},
  3409. {"ANC1 MUX", "ADC2", "ADC2"},
  3410. {"ANC1 MUX", "ADC3", "ADC3"},
  3411. {"ANC1 MUX", "ADC4", "ADC4"},
  3412. {"ANC1 MUX", "DMIC1", "DMIC1"},
  3413. {"ANC1 MUX", "DMIC2", "DMIC2"},
  3414. {"ANC1 MUX", "DMIC3", "DMIC3"},
  3415. {"ANC1 MUX", "DMIC4", "DMIC4"},
  3416. {"ANC2 MUX", "ADC1", "ADC1"},
  3417. {"ANC2 MUX", "ADC2", "ADC2"},
  3418. {"ANC2 MUX", "ADC3", "ADC3"},
  3419. {"ANC2 MUX", "ADC4", "ADC4"},
  3420. {"ANC HPHR", NULL, "CDC_CONN"},
  3421. {"DAC1", "Switch", "RX1 CHAIN"},
  3422. {"HPHL DAC", "Switch", "RX1 CHAIN"},
  3423. {"HPHR DAC", NULL, "RX2 CHAIN"},
  3424. {"LINEOUT1", NULL, "LINEOUT1 PA"},
  3425. {"LINEOUT2", NULL, "LINEOUT2 PA"},
  3426. {"LINEOUT3", NULL, "LINEOUT3 PA"},
  3427. {"LINEOUT4", NULL, "LINEOUT4 PA"},
  3428. {"LINEOUT5", NULL, "LINEOUT5 PA"},
  3429. {"LINEOUT1 PA", NULL, "LINEOUT1_PA_MIXER"},
  3430. {"LINEOUT1_PA_MIXER", NULL, "LINEOUT1 DAC"},
  3431. {"LINEOUT2 PA", NULL, "LINEOUT2_PA_MIXER"},
  3432. {"LINEOUT2_PA_MIXER", NULL, "LINEOUT2 DAC"},
  3433. {"LINEOUT3 PA", NULL, "LINEOUT3_PA_MIXER"},
  3434. {"LINEOUT3_PA_MIXER", NULL, "LINEOUT3 DAC"},
  3435. {"LINEOUT4 PA", NULL, "LINEOUT4_PA_MIXER"},
  3436. {"LINEOUT4_PA_MIXER", NULL, "LINEOUT4 DAC"},
  3437. {"LINEOUT5 PA", NULL, "LINEOUT5_PA_MIXER"},
  3438. {"LINEOUT5_PA_MIXER", NULL, "LINEOUT5 DAC"},
  3439. {"LINEOUT1 DAC", NULL, "RX3 MIX2"},
  3440. {"LINEOUT5 DAC", NULL, "RX7 MIX1"},
  3441. {"RX1 CHAIN", NULL, "RX1 MIX2"},
  3442. {"RX2 CHAIN", NULL, "RX2 MIX2"},
  3443. {"RX1 MIX2", NULL, "ANC1 MUX"},
  3444. {"RX2 MIX2", NULL, "ANC2 MUX"},
  3445. {"CP", NULL, "RX_BIAS"},
  3446. {"LINEOUT1 DAC", NULL, "RX_BIAS"},
  3447. {"LINEOUT2 DAC", NULL, "RX_BIAS"},
  3448. {"LINEOUT3 DAC", NULL, "RX_BIAS"},
  3449. {"LINEOUT4 DAC", NULL, "RX_BIAS"},
  3450. {"LINEOUT5 DAC", NULL, "RX_BIAS"},
  3451. {"RX1 MIX1", NULL, "COMP1_CLK"},
  3452. {"RX2 MIX1", NULL, "COMP1_CLK"},
  3453. {"RX3 MIX1", NULL, "COMP2_CLK"},
  3454. {"RX5 MIX1", NULL, "COMP2_CLK"},
  3455. {"RX1 MIX1", NULL, "RX1 MIX1 INP1"},
  3456. {"RX1 MIX1", NULL, "RX1 MIX1 INP2"},
  3457. {"RX1 MIX1", NULL, "RX1 MIX1 INP3"},
  3458. {"RX2 MIX1", NULL, "RX2 MIX1 INP1"},
  3459. {"RX2 MIX1", NULL, "RX2 MIX1 INP2"},
  3460. {"RX3 MIX1", NULL, "RX3 MIX1 INP1"},
  3461. {"RX3 MIX1", NULL, "RX3 MIX1 INP2"},
  3462. {"RX4 MIX1", NULL, "RX4 MIX1 INP1"},
  3463. {"RX4 MIX1", NULL, "RX4 MIX1 INP2"},
  3464. {"RX5 MIX1", NULL, "RX5 MIX1 INP1"},
  3465. {"RX5 MIX1", NULL, "RX5 MIX1 INP2"},
  3466. {"RX6 MIX1", NULL, "RX6 MIX1 INP1"},
  3467. {"RX6 MIX1", NULL, "RX6 MIX1 INP2"},
  3468. {"RX7 MIX1", NULL, "RX7 MIX1 INP1"},
  3469. {"RX7 MIX1", NULL, "RX7 MIX1 INP2"},
  3470. {"RX1 MIX2", NULL, "RX1 MIX1"},
  3471. {"RX1 MIX2", NULL, "RX1 MIX2 INP1"},
  3472. {"RX1 MIX2", NULL, "RX1 MIX2 INP2"},
  3473. {"RX2 MIX2", NULL, "RX2 MIX1"},
  3474. {"RX2 MIX2", NULL, "RX2 MIX2 INP1"},
  3475. {"RX2 MIX2", NULL, "RX2 MIX2 INP2"},
  3476. {"RX3 MIX2", NULL, "RX3 MIX1"},
  3477. {"RX3 MIX2", NULL, "RX3 MIX2 INP1"},
  3478. {"RX3 MIX2", NULL, "RX3 MIX2 INP2"},
  3479. /* SLIM_MUX("AIF1_PB", "AIF1 PB"),*/
  3480. {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"},
  3481. {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"},
  3482. {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"},
  3483. {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"},
  3484. {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"},
  3485. {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"},
  3486. {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"},
  3487. /* SLIM_MUX("AIF2_PB", "AIF2 PB"),*/
  3488. {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"},
  3489. {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"},
  3490. {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"},
  3491. {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"},
  3492. {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"},
  3493. {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"},
  3494. {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"},
  3495. /* SLIM_MUX("AIF3_PB", "AIF3 PB"),*/
  3496. {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"},
  3497. {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"},
  3498. {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"},
  3499. {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"},
  3500. {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"},
  3501. {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"},
  3502. {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"},
  3503. {"SLIM RX1", NULL, "SLIM RX1 MUX"},
  3504. {"SLIM RX2", NULL, "SLIM RX2 MUX"},
  3505. {"SLIM RX3", NULL, "SLIM RX3 MUX"},
  3506. {"SLIM RX4", NULL, "SLIM RX4 MUX"},
  3507. {"SLIM RX5", NULL, "SLIM RX5 MUX"},
  3508. {"SLIM RX6", NULL, "SLIM RX6 MUX"},
  3509. {"SLIM RX7", NULL, "SLIM RX7 MUX"},
  3510. /* Mixer control for output path */
  3511. {"RX1 MIX1 INP1", "RX1", "SLIM RX1"},
  3512. {"RX1 MIX1 INP1", "RX2", "SLIM RX2"},
  3513. {"RX1 MIX1 INP1", "RX3", "SLIM RX3"},
  3514. {"RX1 MIX1 INP1", "RX4", "SLIM RX4"},
  3515. {"RX1 MIX1 INP1", "RX5", "SLIM RX5"},
  3516. {"RX1 MIX1 INP1", "RX6", "SLIM RX6"},
  3517. {"RX1 MIX1 INP1", "RX7", "SLIM RX7"},
  3518. {"RX1 MIX1 INP1", "IIR1", "IIR1"},
  3519. {"RX1 MIX1 INP1", "IIR2", "IIR2"},
  3520. {"RX1 MIX1 INP2", "RX1", "SLIM RX1"},
  3521. {"RX1 MIX1 INP2", "RX2", "SLIM RX2"},
  3522. {"RX1 MIX1 INP2", "RX3", "SLIM RX3"},
  3523. {"RX1 MIX1 INP2", "RX4", "SLIM RX4"},
  3524. {"RX1 MIX1 INP2", "RX5", "SLIM RX5"},
  3525. {"RX1 MIX1 INP2", "RX6", "SLIM RX6"},
  3526. {"RX1 MIX1 INP2", "RX7", "SLIM RX7"},
  3527. {"RX1 MIX1 INP2", "IIR1", "IIR1"},
  3528. {"RX1 MIX1 INP2", "IIR2", "IIR2"},
  3529. {"RX1 MIX1 INP3", "RX1", "SLIM RX1"},
  3530. {"RX1 MIX1 INP3", "RX2", "SLIM RX2"},
  3531. {"RX1 MIX1 INP3", "RX3", "SLIM RX3"},
  3532. {"RX1 MIX1 INP3", "RX4", "SLIM RX4"},
  3533. {"RX1 MIX1 INP3", "RX5", "SLIM RX5"},
  3534. {"RX1 MIX1 INP3", "RX6", "SLIM RX6"},
  3535. {"RX1 MIX1 INP3", "RX7", "SLIM RX7"},
  3536. {"RX2 MIX1 INP1", "RX1", "SLIM RX1"},
  3537. {"RX2 MIX1 INP1", "RX2", "SLIM RX2"},
  3538. {"RX2 MIX1 INP1", "RX3", "SLIM RX3"},
  3539. {"RX2 MIX1 INP1", "RX4", "SLIM RX4"},
  3540. {"RX2 MIX1 INP1", "RX5", "SLIM RX5"},
  3541. {"RX2 MIX1 INP1", "RX6", "SLIM RX6"},
  3542. {"RX2 MIX1 INP1", "RX7", "SLIM RX7"},
  3543. {"RX2 MIX1 INP1", "IIR1", "IIR1"},
  3544. {"RX2 MIX1 INP1", "IIR2", "IIR2"},
  3545. {"RX2 MIX1 INP2", "RX1", "SLIM RX1"},
  3546. {"RX2 MIX1 INP2", "RX2", "SLIM RX2"},
  3547. {"RX2 MIX1 INP2", "RX3", "SLIM RX3"},
  3548. {"RX2 MIX1 INP2", "RX4", "SLIM RX4"},
  3549. {"RX2 MIX1 INP2", "RX5", "SLIM RX5"},
  3550. {"RX2 MIX1 INP2", "RX6", "SLIM RX6"},
  3551. {"RX2 MIX1 INP2", "RX7", "SLIM RX7"},
  3552. {"RX2 MIX1 INP2", "IIR1", "IIR1"},
  3553. {"RX2 MIX1 INP2", "IIR2", "IIR2"},
  3554. {"RX3 MIX1 INP1", "RX1", "SLIM RX1"},
  3555. {"RX3 MIX1 INP1", "RX2", "SLIM RX2"},
  3556. {"RX3 MIX1 INP1", "RX3", "SLIM RX3"},
  3557. {"RX3 MIX1 INP1", "RX4", "SLIM RX4"},
  3558. {"RX3 MIX1 INP1", "RX5", "SLIM RX5"},
  3559. {"RX3 MIX1 INP1", "RX6", "SLIM RX6"},
  3560. {"RX3 MIX1 INP1", "RX7", "SLIM RX7"},
  3561. {"RX3 MIX1 INP1", "IIR1", "IIR1"},
  3562. {"RX3 MIX1 INP1", "IIR2", "IIR2"},
  3563. {"RX3 MIX1 INP2", "RX1", "SLIM RX1"},
  3564. {"RX3 MIX1 INP2", "RX2", "SLIM RX2"},
  3565. {"RX3 MIX1 INP2", "RX3", "SLIM RX3"},
  3566. {"RX3 MIX1 INP2", "RX4", "SLIM RX4"},
  3567. {"RX3 MIX1 INP2", "RX5", "SLIM RX5"},
  3568. {"RX3 MIX1 INP2", "RX6", "SLIM RX6"},
  3569. {"RX3 MIX1 INP2", "RX7", "SLIM RX7"},
  3570. {"RX3 MIX1 INP2", "IIR1", "IIR1"},
  3571. {"RX3 MIX1 INP2", "IIR2", "IIR2"},
  3572. {"RX4 MIX1 INP1", "RX1", "SLIM RX1"},
  3573. {"RX4 MIX1 INP1", "RX2", "SLIM RX2"},
  3574. {"RX4 MIX1 INP1", "RX3", "SLIM RX3"},
  3575. {"RX4 MIX1 INP1", "RX4", "SLIM RX4"},
  3576. {"RX4 MIX1 INP1", "RX5", "SLIM RX5"},
  3577. {"RX4 MIX1 INP1", "RX6", "SLIM RX6"},
  3578. {"RX4 MIX1 INP1", "RX7", "SLIM RX7"},
  3579. {"RX4 MIX1 INP1", "IIR1", "IIR1"},
  3580. {"RX4 MIX1 INP1", "IIR2", "IIR2"},
  3581. {"RX4 MIX1 INP2", "RX1", "SLIM RX1"},
  3582. {"RX4 MIX1 INP2", "RX2", "SLIM RX2"},
  3583. {"RX4 MIX1 INP2", "RX3", "SLIM RX3"},
  3584. {"RX4 MIX1 INP2", "RX5", "SLIM RX5"},
  3585. {"RX4 MIX1 INP2", "RX4", "SLIM RX4"},
  3586. {"RX4 MIX1 INP2", "RX6", "SLIM RX6"},
  3587. {"RX4 MIX1 INP2", "RX7", "SLIM RX7"},
  3588. {"RX4 MIX1 INP2", "IIR1", "IIR1"},
  3589. {"RX4 MIX1 INP2", "IIR2", "IIR2"},
  3590. {"RX5 MIX1 INP1", "RX1", "SLIM RX1"},
  3591. {"RX5 MIX1 INP1", "RX2", "SLIM RX2"},
  3592. {"RX5 MIX1 INP1", "RX3", "SLIM RX3"},
  3593. {"RX5 MIX1 INP1", "RX4", "SLIM RX4"},
  3594. {"RX5 MIX1 INP1", "RX5", "SLIM RX5"},
  3595. {"RX5 MIX1 INP1", "RX6", "SLIM RX6"},
  3596. {"RX5 MIX1 INP1", "RX7", "SLIM RX7"},
  3597. {"RX5 MIX1 INP1", "IIR1", "IIR1"},
  3598. {"RX5 MIX1 INP1", "IIR2", "IIR2"},
  3599. {"RX5 MIX1 INP2", "RX1", "SLIM RX1"},
  3600. {"RX5 MIX1 INP2", "RX2", "SLIM RX2"},
  3601. {"RX5 MIX1 INP2", "RX3", "SLIM RX3"},
  3602. {"RX5 MIX1 INP2", "RX4", "SLIM RX4"},
  3603. {"RX5 MIX1 INP2", "RX5", "SLIM RX5"},
  3604. {"RX5 MIX1 INP2", "RX6", "SLIM RX6"},
  3605. {"RX5 MIX1 INP2", "RX7", "SLIM RX7"},
  3606. {"RX5 MIX1 INP2", "IIR1", "IIR1"},
  3607. {"RX5 MIX1 INP2", "IIR2", "IIR2"},
  3608. {"RX6 MIX1 INP1", "RX1", "SLIM RX1"},
  3609. {"RX6 MIX1 INP1", "RX2", "SLIM RX2"},
  3610. {"RX6 MIX1 INP1", "RX3", "SLIM RX3"},
  3611. {"RX6 MIX1 INP1", "RX4", "SLIM RX4"},
  3612. {"RX6 MIX1 INP1", "RX5", "SLIM RX5"},
  3613. {"RX6 MIX1 INP1", "RX6", "SLIM RX6"},
  3614. {"RX6 MIX1 INP1", "RX7", "SLIM RX7"},
  3615. {"RX6 MIX1 INP1", "IIR1", "IIR1"},
  3616. {"RX6 MIX1 INP1", "IIR2", "IIR2"},
  3617. {"RX6 MIX1 INP2", "RX1", "SLIM RX1"},
  3618. {"RX6 MIX1 INP2", "RX2", "SLIM RX2"},
  3619. {"RX6 MIX1 INP2", "RX3", "SLIM RX3"},
  3620. {"RX6 MIX1 INP2", "RX4", "SLIM RX4"},
  3621. {"RX6 MIX1 INP2", "RX5", "SLIM RX5"},
  3622. {"RX6 MIX1 INP2", "RX6", "SLIM RX6"},
  3623. {"RX6 MIX1 INP2", "RX7", "SLIM RX7"},
  3624. {"RX6 MIX1 INP2", "IIR1", "IIR1"},
  3625. {"RX6 MIX1 INP2", "IIR2", "IIR2"},
  3626. {"RX7 MIX1 INP1", "RX1", "SLIM RX1"},
  3627. {"RX7 MIX1 INP1", "RX2", "SLIM RX2"},
  3628. {"RX7 MIX1 INP1", "RX3", "SLIM RX3"},
  3629. {"RX7 MIX1 INP1", "RX4", "SLIM RX4"},
  3630. {"RX7 MIX1 INP1", "RX5", "SLIM RX5"},
  3631. {"RX7 MIX1 INP1", "RX6", "SLIM RX6"},
  3632. {"RX7 MIX1 INP1", "RX7", "SLIM RX7"},
  3633. {"RX7 MIX1 INP1", "IIR1", "IIR1"},
  3634. {"RX7 MIX1 INP1", "IIR2", "IIR2"},
  3635. {"RX7 MIX1 INP2", "RX1", "SLIM RX1"},
  3636. {"RX7 MIX1 INP2", "RX2", "SLIM RX2"},
  3637. {"RX7 MIX1 INP2", "RX3", "SLIM RX3"},
  3638. {"RX7 MIX1 INP2", "RX4", "SLIM RX4"},
  3639. {"RX7 MIX1 INP2", "RX5", "SLIM RX5"},
  3640. {"RX7 MIX1 INP2", "RX6", "SLIM RX6"},
  3641. {"RX7 MIX1 INP2", "RX7", "SLIM RX7"},
  3642. {"RX7 MIX1 INP2", "IIR1", "IIR1"},
  3643. {"RX7 MIX1 INP2", "IIR2", "IIR2"},
  3644. {"RX1 MIX2 INP1", "IIR1", "IIR1"},
  3645. {"RX1 MIX2 INP1", "IIR2", "IIR2"},
  3646. {"RX1 MIX2 INP2", "IIR1", "IIR1"},
  3647. {"RX1 MIX2 INP2", "IIR2", "IIR2"},
  3648. {"RX2 MIX2 INP1", "IIR1", "IIR1"},
  3649. {"RX2 MIX2 INP1", "IIR2", "IIR2"},
  3650. {"RX2 MIX2 INP2", "IIR1", "IIR1"},
  3651. {"RX2 MIX2 INP2", "IIR2", "IIR2"},
  3652. {"RX3 MIX2 INP1", "IIR1", "IIR1"},
  3653. {"RX3 MIX2 INP1", "IIR2", "IIR2"},
  3654. {"RX3 MIX2 INP2", "IIR1", "IIR1"},
  3655. {"RX3 MIX2 INP2", "IIR2", "IIR2"},
  3656. /* Decimator Inputs */
  3657. {"DEC1 MUX", "DMIC1", "DMIC1"},
  3658. {"DEC1 MUX", "ADC6", "ADC6"},
  3659. {"DEC1 MUX", NULL, "CDC_CONN"},
  3660. {"DEC2 MUX", "DMIC2", "DMIC2"},
  3661. {"DEC2 MUX", "ADC5", "ADC5"},
  3662. {"DEC2 MUX", NULL, "CDC_CONN"},
  3663. {"DEC3 MUX", "DMIC3", "DMIC3"},
  3664. {"DEC3 MUX", "ADC4", "ADC4"},
  3665. {"DEC3 MUX", NULL, "CDC_CONN"},
  3666. {"DEC4 MUX", "DMIC4", "DMIC4"},
  3667. {"DEC4 MUX", "ADC3", "ADC3"},
  3668. {"DEC4 MUX", NULL, "CDC_CONN"},
  3669. {"DEC5 MUX", "DMIC5", "DMIC5"},
  3670. {"DEC5 MUX", "ADC2", "ADC2"},
  3671. {"DEC5 MUX", NULL, "CDC_CONN"},
  3672. {"DEC6 MUX", "DMIC6", "DMIC6"},
  3673. {"DEC6 MUX", "ADC1", "ADC1"},
  3674. {"DEC6 MUX", NULL, "CDC_CONN"},
  3675. {"DEC7 MUX", "DMIC1", "DMIC1"},
  3676. {"DEC7 MUX", "DMIC6", "DMIC6"},
  3677. {"DEC7 MUX", "ADC1", "ADC1"},
  3678. {"DEC7 MUX", "ADC6", "ADC6"},
  3679. {"DEC7 MUX", NULL, "CDC_CONN"},
  3680. {"DEC8 MUX", "DMIC2", "DMIC2"},
  3681. {"DEC8 MUX", "DMIC5", "DMIC5"},
  3682. {"DEC8 MUX", "ADC2", "ADC2"},
  3683. {"DEC8 MUX", "ADC5", "ADC5"},
  3684. {"DEC8 MUX", NULL, "CDC_CONN"},
  3685. {"DEC9 MUX", "DMIC4", "DMIC4"},
  3686. {"DEC9 MUX", "DMIC5", "DMIC5"},
  3687. {"DEC9 MUX", "ADC2", "ADC2"},
  3688. {"DEC9 MUX", "ADC3", "ADC3"},
  3689. {"DEC9 MUX", NULL, "CDC_CONN"},
  3690. {"DEC10 MUX", "DMIC3", "DMIC3"},
  3691. {"DEC10 MUX", "DMIC6", "DMIC6"},
  3692. {"DEC10 MUX", "ADC1", "ADC1"},
  3693. {"DEC10 MUX", "ADC4", "ADC4"},
  3694. {"DEC10 MUX", NULL, "CDC_CONN"},
  3695. /* ADC Connections */
  3696. {"ADC1", NULL, "AMIC1"},
  3697. {"ADC2", NULL, "AMIC2"},
  3698. {"ADC3", NULL, "AMIC3"},
  3699. {"ADC4", NULL, "AMIC4"},
  3700. {"ADC5", NULL, "AMIC5"},
  3701. {"ADC6", NULL, "AMIC6"},
  3702. /* AUX PGA Connections */
  3703. {"HPHL_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
  3704. {"HPHL_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
  3705. {"HPHL_PA_MIXER", "AUX_PGA_L_INV Switch", "AUX_PGA_Left"},
  3706. {"HPHL_PA_MIXER", "AUX_PGA_R_INV Switch", "AUX_PGA_Right"},
  3707. {"HPHR_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
  3708. {"HPHR_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
  3709. {"HPHR_PA_MIXER", "AUX_PGA_L_INV Switch", "AUX_PGA_Left"},
  3710. {"HPHR_PA_MIXER", "AUX_PGA_R_INV Switch", "AUX_PGA_Right"},
  3711. {"LINEOUT1_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
  3712. {"LINEOUT1_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
  3713. {"LINEOUT1_PA_MIXER", "AUX_PGA_L_INV Switch", "AUX_PGA_Left"},
  3714. {"LINEOUT1_PA_MIXER", "AUX_PGA_R_INV Switch", "AUX_PGA_Right"},
  3715. {"LINEOUT2_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
  3716. {"LINEOUT2_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
  3717. {"LINEOUT2_PA_MIXER", "AUX_PGA_L_INV Switch", "AUX_PGA_Left"},
  3718. {"LINEOUT2_PA_MIXER", "AUX_PGA_R_INV Switch", "AUX_PGA_Right"},
  3719. {"LINEOUT3_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
  3720. {"LINEOUT3_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
  3721. {"LINEOUT3_PA_MIXER", "AUX_PGA_L_INV Switch", "AUX_PGA_Left"},
  3722. {"LINEOUT3_PA_MIXER", "AUX_PGA_R_INV Switch", "AUX_PGA_Right"},
  3723. {"LINEOUT4_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
  3724. {"LINEOUT4_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
  3725. {"LINEOUT4_PA_MIXER", "AUX_PGA_L_INV Switch", "AUX_PGA_Left"},
  3726. {"LINEOUT4_PA_MIXER", "AUX_PGA_R_INV Switch", "AUX_PGA_Right"},
  3727. {"LINEOUT5_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
  3728. {"LINEOUT5_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
  3729. {"LINEOUT5_PA_MIXER", "AUX_PGA_L_INV Switch", "AUX_PGA_Left"},
  3730. {"LINEOUT5_PA_MIXER", "AUX_PGA_R_INV Switch", "AUX_PGA_Right"},
  3731. {"EAR_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
  3732. {"EAR_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
  3733. {"EAR_PA_MIXER", "AUX_PGA_L_INV Switch", "AUX_PGA_Left"},
  3734. {"EAR_PA_MIXER", "AUX_PGA_R_INV Switch", "AUX_PGA_Right"},
  3735. {"AUX_PGA_Left", NULL, "AMIC5"},
  3736. {"AUX_PGA_Right", NULL, "AMIC6"},
  3737. {"IIR1", NULL, "IIR1 INP1 MUX"},
  3738. {"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"},
  3739. {"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"},
  3740. {"IIR1 INP1 MUX", "DEC3", "DEC3 MUX"},
  3741. {"IIR1 INP1 MUX", "DEC4", "DEC4 MUX"},
  3742. {"IIR1 INP1 MUX", "DEC5", "DEC5 MUX"},
  3743. {"IIR1 INP1 MUX", "DEC6", "DEC6 MUX"},
  3744. {"IIR1 INP1 MUX", "DEC7", "DEC7 MUX"},
  3745. {"IIR1 INP1 MUX", "DEC8", "DEC8 MUX"},
  3746. {"IIR1 INP1 MUX", "DEC9", "DEC9 MUX"},
  3747. {"IIR1 INP1 MUX", "DEC10", "DEC10 MUX"},
  3748. {"IIR2", NULL, "IIR2 INP1 MUX"},
  3749. {"IIR2 INP1 MUX", "DEC1", "DEC1 MUX"},
  3750. {"IIR2 INP1 MUX", "DEC2", "DEC2 MUX"},
  3751. {"IIR2 INP1 MUX", "DEC3", "DEC3 MUX"},
  3752. {"IIR2 INP1 MUX", "DEC4", "DEC4 MUX"},
  3753. {"IIR2 INP1 MUX", "DEC5", "DEC5 MUX"},
  3754. {"IIR2 INP1 MUX", "DEC6", "DEC6 MUX"},
  3755. {"IIR2 INP1 MUX", "DEC7", "DEC7 MUX"},
  3756. {"IIR2 INP1 MUX", "DEC8", "DEC8 MUX"},
  3757. {"IIR2 INP1 MUX", "DEC9", "DEC9 MUX"},
  3758. {"IIR2 INP1 MUX", "DEC10", "DEC10 MUX"},
  3759. {"MIC BIAS1 Internal1", NULL, "LDO_H"},
  3760. {"MIC BIAS1 Internal2", NULL, "LDO_H"},
  3761. {"MIC BIAS1 External", NULL, "LDO_H"},
  3762. {"MIC BIAS2 Internal1", NULL, "LDO_H"},
  3763. {"MIC BIAS2 Internal2", NULL, "LDO_H"},
  3764. {"MIC BIAS2 Internal3", NULL, "LDO_H"},
  3765. {"MIC BIAS2 External", NULL, "LDO_H"},
  3766. {"MIC BIAS3 Internal1", NULL, "LDO_H"},
  3767. {"MIC BIAS3 Internal2", NULL, "LDO_H"},
  3768. {"MIC BIAS3 External", NULL, "LDO_H"},
  3769. {"MIC BIAS4 External", NULL, "LDO_H"},
  3770. };
  3771. static const struct snd_soc_dapm_route tabla_1_x_lineout_2_to_4_map[] = {
  3772. {"RX4 DSM MUX", "DSM_INV", "RX3 MIX2"},
  3773. {"RX4 DSM MUX", "CIC_OUT", "RX4 MIX1"},
  3774. {"LINEOUT2 DAC", NULL, "RX4 DSM MUX"},
  3775. {"LINEOUT3 DAC", NULL, "RX5 MIX1"},
  3776. {"LINEOUT3 DAC GROUND", "Switch", "RX3 MIX2"},
  3777. {"LINEOUT3 DAC", NULL, "LINEOUT3 DAC GROUND"},
  3778. {"RX6 DSM MUX", "DSM_INV", "RX5 MIX1"},
  3779. {"RX6 DSM MUX", "CIC_OUT", "RX6 MIX1"},
  3780. {"LINEOUT4 DAC", NULL, "RX6 DSM MUX"},
  3781. {"LINEOUT4 DAC GROUND", "Switch", "RX4 DSM MUX"},
  3782. {"LINEOUT4 DAC", NULL, "LINEOUT4 DAC GROUND"},
  3783. };
  3784. static const struct snd_soc_dapm_route tabla_2_x_lineout_2_to_4_map[] = {
  3785. {"RX4 DSM MUX", "DSM_INV", "RX3 MIX2"},
  3786. {"RX4 DSM MUX", "CIC_OUT", "RX4 MIX1"},
  3787. {"LINEOUT3 DAC", NULL, "RX4 DSM MUX"},
  3788. {"LINEOUT2 DAC", NULL, "RX5 MIX1"},
  3789. {"RX6 DSM MUX", "DSM_INV", "RX5 MIX1"},
  3790. {"RX6 DSM MUX", "CIC_OUT", "RX6 MIX1"},
  3791. {"LINEOUT4 DAC", NULL, "RX6 DSM MUX"},
  3792. };
  3793. static int tabla_readable(struct snd_soc_codec *ssc, unsigned int reg)
  3794. {
  3795. int i;
  3796. struct wcd9xxx *tabla_core = dev_get_drvdata(ssc->dev->parent);
  3797. if (TABLA_IS_1_X(tabla_core->version)) {
  3798. for (i = 0; i < ARRAY_SIZE(tabla_1_reg_readable); i++) {
  3799. if (tabla_1_reg_readable[i] == reg)
  3800. return 1;
  3801. }
  3802. } else {
  3803. for (i = 0; i < ARRAY_SIZE(tabla_2_reg_readable); i++) {
  3804. if (tabla_2_reg_readable[i] == reg)
  3805. return 1;
  3806. }
  3807. }
  3808. return tabla_reg_readable[reg];
  3809. }
  3810. static bool tabla_is_digital_gain_register(unsigned int reg)
  3811. {
  3812. bool rtn = false;
  3813. switch (reg) {
  3814. case TABLA_A_CDC_RX1_VOL_CTL_B2_CTL:
  3815. case TABLA_A_CDC_RX2_VOL_CTL_B2_CTL:
  3816. case TABLA_A_CDC_RX3_VOL_CTL_B2_CTL:
  3817. case TABLA_A_CDC_RX4_VOL_CTL_B2_CTL:
  3818. case TABLA_A_CDC_RX5_VOL_CTL_B2_CTL:
  3819. case TABLA_A_CDC_RX6_VOL_CTL_B2_CTL:
  3820. case TABLA_A_CDC_RX7_VOL_CTL_B2_CTL:
  3821. case TABLA_A_CDC_TX1_VOL_CTL_GAIN:
  3822. case TABLA_A_CDC_TX2_VOL_CTL_GAIN:
  3823. case TABLA_A_CDC_TX3_VOL_CTL_GAIN:
  3824. case TABLA_A_CDC_TX4_VOL_CTL_GAIN:
  3825. case TABLA_A_CDC_TX5_VOL_CTL_GAIN:
  3826. case TABLA_A_CDC_TX6_VOL_CTL_GAIN:
  3827. case TABLA_A_CDC_TX7_VOL_CTL_GAIN:
  3828. case TABLA_A_CDC_TX8_VOL_CTL_GAIN:
  3829. case TABLA_A_CDC_TX9_VOL_CTL_GAIN:
  3830. case TABLA_A_CDC_TX10_VOL_CTL_GAIN:
  3831. rtn = true;
  3832. break;
  3833. default:
  3834. break;
  3835. }
  3836. return rtn;
  3837. }
  3838. static int tabla_volatile(struct snd_soc_codec *ssc, unsigned int reg)
  3839. {
  3840. /* Registers lower than 0x100 are top level registers which can be
  3841. * written by the Tabla core driver.
  3842. */
  3843. if ((reg >= TABLA_A_CDC_MBHC_EN_CTL) || (reg < 0x100))
  3844. return 1;
  3845. /* IIR Coeff registers are not cacheable */
  3846. if ((reg >= TABLA_A_CDC_IIR1_COEF_B1_CTL) &&
  3847. (reg <= TABLA_A_CDC_IIR2_COEF_B5_CTL))
  3848. return 1;
  3849. /* ANC filter registers are not cacheable */
  3850. if ((reg >= TABLA_A_CDC_ANC1_FILT1_B1_CTL) &&
  3851. (reg <= TABLA_A_CDC_ANC1_FILT2_B3_CTL))
  3852. return 1;
  3853. if ((reg >= TABLA_A_CDC_ANC2_FILT1_B1_CTL) &&
  3854. (reg <= TABLA_A_CDC_ANC2_FILT2_B3_CTL))
  3855. return 1;
  3856. /* Digital gain register is not cacheable so we have to write
  3857. * the setting even it is the same
  3858. */
  3859. if (tabla_is_digital_gain_register(reg))
  3860. return 1;
  3861. /* HPH status registers */
  3862. if (reg == TABLA_A_RX_HPH_L_STATUS || reg == TABLA_A_RX_HPH_R_STATUS)
  3863. return 1;
  3864. if (reg == TABLA_A_CDC_COMP1_SHUT_DOWN_STATUS ||
  3865. reg == TABLA_A_CDC_COMP2_SHUT_DOWN_STATUS)
  3866. return 1;
  3867. return 0;
  3868. }
  3869. #define TABLA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
  3870. static int tabla_write(struct snd_soc_codec *codec, unsigned int reg,
  3871. unsigned int value)
  3872. {
  3873. int ret;
  3874. if (reg == SND_SOC_NOPM)
  3875. return 0;
  3876. BUG_ON(reg > TABLA_MAX_REGISTER);
  3877. if (!tabla_volatile(codec, reg)) {
  3878. ret = snd_soc_cache_write(codec, reg, value);
  3879. if (ret != 0)
  3880. dev_err(codec->dev, "Cache write to %x failed: %d\n",
  3881. reg, ret);
  3882. }
  3883. return wcd9xxx_reg_write(codec->control_data, reg, value);
  3884. }
  3885. static unsigned int tabla_read(struct snd_soc_codec *codec,
  3886. unsigned int reg)
  3887. {
  3888. unsigned int val;
  3889. int ret;
  3890. if (reg == SND_SOC_NOPM)
  3891. return 0;
  3892. BUG_ON(reg > TABLA_MAX_REGISTER);
  3893. if (!tabla_volatile(codec, reg) && tabla_readable(codec, reg) &&
  3894. reg < codec->driver->reg_cache_size) {
  3895. ret = snd_soc_cache_read(codec, reg, &val);
  3896. if (ret >= 0) {
  3897. return val;
  3898. } else
  3899. dev_err(codec->dev, "Cache read from %x failed: %d\n",
  3900. reg, ret);
  3901. }
  3902. val = wcd9xxx_reg_read(codec->control_data, reg);
  3903. return val;
  3904. }
  3905. static s16 tabla_get_current_v_ins(struct tabla_priv *tabla, bool hu)
  3906. {
  3907. s16 v_ins;
  3908. if ((tabla->mbhc_data.micb_mv != VDDIO_MICBIAS_MV) &&
  3909. tabla->mbhc_micbias_switched)
  3910. v_ins = hu ? (s16)tabla->mbhc_data.adj_v_ins_hu :
  3911. (s16)tabla->mbhc_data.adj_v_ins_h;
  3912. else
  3913. v_ins = hu ? (s16)tabla->mbhc_data.v_ins_hu :
  3914. (s16)tabla->mbhc_data.v_ins_h;
  3915. return v_ins;
  3916. }
  3917. static s16 tabla_get_current_v_hs_max(struct tabla_priv *tabla)
  3918. {
  3919. s16 v_hs_max;
  3920. struct tabla_mbhc_plug_type_cfg *plug_type;
  3921. plug_type = TABLA_MBHC_CAL_PLUG_TYPE_PTR(tabla->mbhc_cfg.calibration);
  3922. if ((tabla->mbhc_data.micb_mv != VDDIO_MICBIAS_MV) &&
  3923. tabla->mbhc_micbias_switched)
  3924. v_hs_max = tabla->mbhc_data.adj_v_hs_max;
  3925. else
  3926. v_hs_max = plug_type->v_hs_max;
  3927. return v_hs_max;
  3928. }
  3929. static void tabla_codec_calibrate_rel(struct snd_soc_codec *codec)
  3930. {
  3931. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  3932. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B3_CTL,
  3933. tabla->mbhc_data.v_b1_hu & 0xFF);
  3934. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B4_CTL,
  3935. (tabla->mbhc_data.v_b1_hu >> 8) & 0xFF);
  3936. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B5_CTL,
  3937. tabla->mbhc_data.v_b1_h & 0xFF);
  3938. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B6_CTL,
  3939. (tabla->mbhc_data.v_b1_h >> 8) & 0xFF);
  3940. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B9_CTL,
  3941. tabla->mbhc_data.v_brh & 0xFF);
  3942. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B10_CTL,
  3943. (tabla->mbhc_data.v_brh >> 8) & 0xFF);
  3944. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B11_CTL,
  3945. tabla->mbhc_data.v_brl & 0xFF);
  3946. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B12_CTL,
  3947. (tabla->mbhc_data.v_brl >> 8) & 0xFF);
  3948. }
  3949. static void tabla_codec_calibrate_hs_polling(struct snd_soc_codec *codec)
  3950. {
  3951. u8 *n_ready, *n_cic;
  3952. struct tabla_mbhc_btn_detect_cfg *btn_det;
  3953. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  3954. const s16 v_ins_hu = tabla_get_current_v_ins(tabla, true);
  3955. btn_det = TABLA_MBHC_CAL_BTN_DET_PTR(tabla->mbhc_cfg.calibration);
  3956. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B1_CTL,
  3957. v_ins_hu & 0xFF);
  3958. snd_soc_write(codec, TABLA_A_CDC_MBHC_VOLT_B2_CTL,
  3959. (v_ins_hu >> 8) & 0xFF);
  3960. tabla_codec_calibrate_rel(codec);
  3961. n_ready = tabla_mbhc_cal_btn_det_mp(btn_det, TABLA_BTN_DET_N_READY);
  3962. snd_soc_write(codec, TABLA_A_CDC_MBHC_TIMER_B1_CTL,
  3963. n_ready[tabla_codec_mclk_index(tabla)]);
  3964. snd_soc_write(codec, TABLA_A_CDC_MBHC_TIMER_B2_CTL,
  3965. tabla->mbhc_data.npoll);
  3966. snd_soc_write(codec, TABLA_A_CDC_MBHC_TIMER_B3_CTL,
  3967. tabla->mbhc_data.nbounce_wait);
  3968. n_cic = tabla_mbhc_cal_btn_det_mp(btn_det, TABLA_BTN_DET_N_CIC);
  3969. snd_soc_write(codec, TABLA_A_CDC_MBHC_TIMER_B6_CTL,
  3970. n_cic[tabla_codec_mclk_index(tabla)]);
  3971. }
  3972. static int tabla_startup(struct snd_pcm_substream *substream,
  3973. struct snd_soc_dai *dai)
  3974. {
  3975. struct wcd9xxx *tabla_core = dev_get_drvdata(dai->codec->dev->parent);
  3976. pr_debug("%s(): substream = %s stream = %d\n" , __func__,
  3977. substream->name, substream->stream);
  3978. if ((tabla_core != NULL) &&
  3979. (tabla_core->dev != NULL) &&
  3980. (tabla_core->dev->parent != NULL))
  3981. pm_runtime_get_sync(tabla_core->dev->parent);
  3982. return 0;
  3983. }
  3984. static void tabla_shutdown(struct snd_pcm_substream *substream,
  3985. struct snd_soc_dai *dai)
  3986. {
  3987. struct wcd9xxx *tabla_core = dev_get_drvdata(dai->codec->dev->parent);
  3988. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(dai->codec);
  3989. u32 active = 0;
  3990. pr_debug("%s(): substream = %s stream = %d\n" , __func__,
  3991. substream->name, substream->stream);
  3992. if (tabla->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS)
  3993. return;
  3994. if (dai->id <= NUM_CODEC_DAIS) {
  3995. if (tabla->dai[dai->id].ch_mask) {
  3996. active = 1;
  3997. pr_debug("%s(): Codec DAI: chmask[%d] = 0x%lx\n",
  3998. __func__, dai->id, tabla->dai[dai->id].ch_mask);
  3999. }
  4000. }
  4001. if ((tabla_core != NULL) &&
  4002. (tabla_core->dev != NULL) &&
  4003. (tabla_core->dev->parent != NULL) &&
  4004. (active == 0)) {
  4005. pm_runtime_mark_last_busy(tabla_core->dev->parent);
  4006. pm_runtime_put(tabla_core->dev->parent);
  4007. }
  4008. }
  4009. int tabla_mclk_enable(struct snd_soc_codec *codec, int mclk_enable, bool dapm)
  4010. {
  4011. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  4012. pr_debug("%s: mclk_enable = %u, dapm = %d\n", __func__, mclk_enable,
  4013. dapm);
  4014. if (dapm)
  4015. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  4016. if (mclk_enable) {
  4017. tabla->mclk_enabled = true;
  4018. if (tabla->mbhc_polling_active) {
  4019. tabla_codec_pause_hs_polling(codec);
  4020. tabla_codec_disable_clock_block(codec);
  4021. tabla_codec_enable_bandgap(codec,
  4022. TABLA_BANDGAP_AUDIO_MODE);
  4023. tabla_codec_enable_clock_block(codec, 0);
  4024. tabla_codec_calibrate_hs_polling(codec);
  4025. tabla_codec_start_hs_polling(codec);
  4026. } else {
  4027. tabla_codec_disable_clock_block(codec);
  4028. tabla_codec_enable_bandgap(codec,
  4029. TABLA_BANDGAP_AUDIO_MODE);
  4030. tabla_codec_enable_clock_block(codec, 0);
  4031. }
  4032. } else {
  4033. if (!tabla->mclk_enabled) {
  4034. if (dapm)
  4035. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  4036. pr_err("Error, MCLK already diabled\n");
  4037. return -EINVAL;
  4038. }
  4039. tabla->mclk_enabled = false;
  4040. if (tabla->mbhc_polling_active) {
  4041. tabla_codec_pause_hs_polling(codec);
  4042. tabla_codec_disable_clock_block(codec);
  4043. tabla_codec_enable_bandgap(codec,
  4044. TABLA_BANDGAP_MBHC_MODE);
  4045. tabla_enable_rx_bias(codec, 1);
  4046. tabla_codec_enable_clock_block(codec, 1);
  4047. tabla_codec_calibrate_hs_polling(codec);
  4048. tabla_codec_start_hs_polling(codec);
  4049. snd_soc_update_bits(codec, TABLA_A_CLK_BUFF_EN1,
  4050. 0x05, 0x01);
  4051. } else {
  4052. tabla_codec_disable_clock_block(codec);
  4053. tabla_codec_enable_bandgap(codec,
  4054. TABLA_BANDGAP_OFF);
  4055. }
  4056. }
  4057. if (dapm)
  4058. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  4059. return 0;
  4060. }
  4061. static int tabla_set_dai_sysclk(struct snd_soc_dai *dai,
  4062. int clk_id, unsigned int freq, int dir)
  4063. {
  4064. pr_debug("%s\n", __func__);
  4065. return 0;
  4066. }
  4067. static int tabla_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  4068. {
  4069. u8 val = 0;
  4070. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(dai->codec);
  4071. pr_debug("%s\n", __func__);
  4072. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  4073. case SND_SOC_DAIFMT_CBS_CFS:
  4074. /* CPU is master */
  4075. if (tabla->intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
  4076. if (dai->id == AIF1_CAP)
  4077. snd_soc_update_bits(dai->codec,
  4078. TABLA_A_CDC_CLK_TX_I2S_CTL,
  4079. TABLA_I2S_MASTER_MODE_MASK, 0);
  4080. else if (dai->id == AIF1_PB)
  4081. snd_soc_update_bits(dai->codec,
  4082. TABLA_A_CDC_CLK_RX_I2S_CTL,
  4083. TABLA_I2S_MASTER_MODE_MASK, 0);
  4084. }
  4085. break;
  4086. case SND_SOC_DAIFMT_CBM_CFM:
  4087. /* CPU is slave */
  4088. if (tabla->intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
  4089. val = TABLA_I2S_MASTER_MODE_MASK;
  4090. if (dai->id == AIF1_CAP)
  4091. snd_soc_update_bits(dai->codec,
  4092. TABLA_A_CDC_CLK_TX_I2S_CTL, val, val);
  4093. else if (dai->id == AIF1_PB)
  4094. snd_soc_update_bits(dai->codec,
  4095. TABLA_A_CDC_CLK_RX_I2S_CTL, val, val);
  4096. }
  4097. break;
  4098. default:
  4099. return -EINVAL;
  4100. }
  4101. return 0;
  4102. }
  4103. static int tabla_set_channel_map(struct snd_soc_dai *dai,
  4104. unsigned int tx_num, unsigned int *tx_slot,
  4105. unsigned int rx_num, unsigned int *rx_slot)
  4106. {
  4107. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(dai->codec);
  4108. struct wcd9xxx *core = dev_get_drvdata(dai->codec->dev->parent);
  4109. if (!tx_slot && !rx_slot) {
  4110. pr_err("%s: Invalid\n", __func__);
  4111. return -EINVAL;
  4112. }
  4113. pr_debug("%s(): dai_name = %s DAI-ID %x tx_ch %d rx_ch %d\n"
  4114. "tabla->intf_type %d\n",
  4115. __func__, dai->name, dai->id, tx_num, rx_num,
  4116. tabla->intf_type);
  4117. if (tabla->intf_type == WCD9XXX_INTERFACE_TYPE_SLIMBUS)
  4118. wcd9xxx_init_slimslave(core, core->slim->laddr,
  4119. tx_num, tx_slot, rx_num, rx_slot);
  4120. return 0;
  4121. }
  4122. static int tabla_get_channel_map(struct snd_soc_dai *dai,
  4123. unsigned int *tx_num, unsigned int *tx_slot,
  4124. unsigned int *rx_num, unsigned int *rx_slot)
  4125. {
  4126. struct tabla_priv *tabla_p = snd_soc_codec_get_drvdata(dai->codec);
  4127. u32 i = 0;
  4128. struct wcd9xxx_ch *ch;
  4129. switch (dai->id) {
  4130. case AIF1_PB:
  4131. case AIF2_PB:
  4132. case AIF3_PB:
  4133. if (!rx_slot || !rx_num) {
  4134. pr_err("%s: Invalid rx_slot %d or rx_num %d\n",
  4135. __func__, (u32) rx_slot, (u32) rx_num);
  4136. return -EINVAL;
  4137. }
  4138. list_for_each_entry(ch, &tabla_p->dai[dai->id].wcd9xxx_ch_list,
  4139. list) {
  4140. rx_slot[i++] = ch->ch_num;
  4141. }
  4142. *rx_num = i;
  4143. break;
  4144. case AIF1_CAP:
  4145. case AIF2_CAP:
  4146. case AIF3_CAP:
  4147. if (!tx_slot || !tx_num) {
  4148. pr_err("%s: Invalid tx_slot %d or tx_num %d\n",
  4149. __func__, (u32) tx_slot, (u32) tx_num);
  4150. return -EINVAL;
  4151. }
  4152. list_for_each_entry(ch, &tabla_p->dai[dai->id].wcd9xxx_ch_list,
  4153. list) {
  4154. tx_slot[i++] = ch->ch_num;
  4155. }
  4156. *tx_num = i;
  4157. break;
  4158. default:
  4159. pr_err("%s: Invalid DAI ID %x\n", __func__, dai->id);
  4160. break;
  4161. }
  4162. return 0;
  4163. }
  4164. static int tabla_set_interpolator_rate(struct snd_soc_dai *dai,
  4165. u8 rx_fs_rate_reg_val,
  4166. u32 compander_fs,
  4167. u32 sample_rate)
  4168. {
  4169. u32 j;
  4170. u8 rx_mix1_inp;
  4171. u16 rx_mix_1_reg_1, rx_mix_1_reg_2;
  4172. u16 rx_fs_reg;
  4173. u8 rx_mix_1_reg_1_val, rx_mix_1_reg_2_val;
  4174. struct snd_soc_codec *codec = dai->codec;
  4175. struct wcd9xxx_ch *ch;
  4176. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  4177. list_for_each_entry(ch, &tabla->dai[dai->id].wcd9xxx_ch_list, list) {
  4178. rx_mix1_inp = ch->port - RX_MIX1_INP_SEL_RX1;
  4179. if ((rx_mix1_inp < RX_MIX1_INP_SEL_RX1) ||
  4180. (rx_mix1_inp > RX_MIX1_INP_SEL_RX7)) {
  4181. pr_err("%s: Invalid TABLA_RX%u port. Dai ID is %d\n",
  4182. __func__, rx_mix1_inp - 5 , dai->id);
  4183. return -EINVAL;
  4184. }
  4185. rx_mix_1_reg_1 = TABLA_A_CDC_CONN_RX1_B1_CTL;
  4186. for (j = 0; j < NUM_INTERPOLATORS; j++) {
  4187. rx_mix_1_reg_2 = rx_mix_1_reg_1 + 1;
  4188. rx_mix_1_reg_1_val = snd_soc_read(codec,
  4189. rx_mix_1_reg_1);
  4190. rx_mix_1_reg_2_val = snd_soc_read(codec,
  4191. rx_mix_1_reg_2);
  4192. if (((rx_mix_1_reg_1_val & 0x0F) == rx_mix1_inp) ||
  4193. (((rx_mix_1_reg_1_val >> 4) & 0x0F) == rx_mix1_inp) ||
  4194. ((rx_mix_1_reg_2_val & 0x0F) == rx_mix1_inp)) {
  4195. rx_fs_reg = TABLA_A_CDC_RX1_B5_CTL + 8 * j;
  4196. pr_debug("%s: AIF_PB DAI(%d) connected to RX%u\n",
  4197. __func__, dai->id, j + 1);
  4198. pr_debug("%s: set RX%u sample rate to %u\n",
  4199. __func__, j + 1, sample_rate);
  4200. snd_soc_update_bits(codec, rx_fs_reg,
  4201. 0xE0, rx_fs_rate_reg_val);
  4202. if (comp_rx_path[j] < COMPANDER_MAX)
  4203. tabla->comp_fs[comp_rx_path[j]]
  4204. = compander_fs;
  4205. }
  4206. if (j <= 2)
  4207. rx_mix_1_reg_1 += 3;
  4208. else
  4209. rx_mix_1_reg_1 += 2;
  4210. }
  4211. }
  4212. return 0;
  4213. }
  4214. static int tabla_set_decimator_rate(struct snd_soc_dai *dai,
  4215. u8 tx_fs_rate_reg_val,
  4216. u32 sample_rate)
  4217. {
  4218. struct snd_soc_codec *codec = dai->codec;
  4219. struct wcd9xxx_ch *ch;
  4220. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  4221. u32 tx_port;
  4222. u16 tx_port_reg, tx_fs_reg;
  4223. u8 tx_port_reg_val;
  4224. s8 decimator;
  4225. list_for_each_entry(ch, &tabla->dai[dai->id].wcd9xxx_ch_list, list) {
  4226. tx_port = ch->port + 1;
  4227. pr_debug("%s: dai->id = %d, tx_port = %d",
  4228. __func__, dai->id, tx_port);
  4229. if ((tx_port < 1) || (tx_port > NUM_DECIMATORS)) {
  4230. pr_err("%s: Invalid SLIM TX%u port. DAI ID is %d\n",
  4231. __func__, tx_port, dai->id);
  4232. return -EINVAL;
  4233. }
  4234. tx_port_reg = TABLA_A_CDC_CONN_TX_SB_B1_CTL + (tx_port - 1);
  4235. tx_port_reg_val = snd_soc_read(codec, tx_port_reg);
  4236. decimator = 0;
  4237. if ((tx_port >= 1) && (tx_port <= 6)) {
  4238. tx_port_reg_val = tx_port_reg_val & 0x0F;
  4239. if (tx_port_reg_val == 0x8)
  4240. decimator = tx_port;
  4241. } else if ((tx_port >= 7) && (tx_port <= NUM_DECIMATORS)) {
  4242. tx_port_reg_val = tx_port_reg_val & 0x1F;
  4243. if ((tx_port_reg_val >= 0x8) &&
  4244. (tx_port_reg_val <= 0x11)) {
  4245. decimator = (tx_port_reg_val - 0x8) + 1;
  4246. }
  4247. }
  4248. if (decimator) { /* SLIM_TX port has a DEC as input */
  4249. tx_fs_reg = TABLA_A_CDC_TX1_CLK_FS_CTL +
  4250. 8 * (decimator - 1);
  4251. pr_debug("%s: set DEC%u (-> SLIM_TX%u) rate to %u\n",
  4252. __func__, decimator, tx_port, sample_rate);
  4253. snd_soc_update_bits(codec, tx_fs_reg, 0x07,
  4254. tx_fs_rate_reg_val);
  4255. } else {
  4256. if ((tx_port_reg_val >= 0x1) &&
  4257. (tx_port_reg_val <= 0x7)) {
  4258. pr_debug("%s: RMIX%u going to SLIM TX%u\n",
  4259. __func__, tx_port_reg_val, tx_port);
  4260. } else if ((tx_port_reg_val >= 0x8) &&
  4261. (tx_port_reg_val <= 0x11)) {
  4262. pr_err("%s: ERROR: Should not be here\n",
  4263. __func__);
  4264. pr_err("%s: ERROR: DEC connected to SLIM TX%u\n",
  4265. __func__, tx_port);
  4266. return -EINVAL;
  4267. } else if (tx_port_reg_val == 0) {
  4268. pr_debug("%s: no signal to SLIM TX%u\n",
  4269. __func__, tx_port);
  4270. } else {
  4271. pr_err("%s: ERROR: wrong signal to SLIM TX%u\n",
  4272. __func__, tx_port);
  4273. pr_err("%s: ERROR: wrong signal = %u\n",
  4274. __func__, tx_port_reg_val);
  4275. return -EINVAL;
  4276. }
  4277. }
  4278. }
  4279. return 0;
  4280. }
  4281. static int tabla_hw_params(struct snd_pcm_substream *substream,
  4282. struct snd_pcm_hw_params *params,
  4283. struct snd_soc_dai *dai)
  4284. {
  4285. struct snd_soc_codec *codec = dai->codec;
  4286. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(dai->codec);
  4287. u8 tx_fs_rate_reg_val, rx_fs_rate_reg_val;
  4288. u32 compander_fs;
  4289. int ret;
  4290. pr_debug("%s: dai_name = %s DAI-ID %x rate %d num_ch %d\n", __func__,
  4291. dai->name, dai->id, params_rate(params),
  4292. params_channels(params));
  4293. switch (params_rate(params)) {
  4294. case 8000:
  4295. tx_fs_rate_reg_val = 0x00;
  4296. rx_fs_rate_reg_val = 0x00;
  4297. compander_fs = COMPANDER_FS_8KHZ;
  4298. break;
  4299. case 16000:
  4300. tx_fs_rate_reg_val = 0x01;
  4301. rx_fs_rate_reg_val = 0x20;
  4302. compander_fs = COMPANDER_FS_16KHZ;
  4303. break;
  4304. case 32000:
  4305. tx_fs_rate_reg_val = 0x02;
  4306. rx_fs_rate_reg_val = 0x40;
  4307. compander_fs = COMPANDER_FS_32KHZ;
  4308. break;
  4309. case 48000:
  4310. tx_fs_rate_reg_val = 0x03;
  4311. rx_fs_rate_reg_val = 0x60;
  4312. compander_fs = COMPANDER_FS_48KHZ;
  4313. break;
  4314. case 96000:
  4315. tx_fs_rate_reg_val = 0x04;
  4316. rx_fs_rate_reg_val = 0x80;
  4317. compander_fs = COMPANDER_FS_96KHZ;
  4318. break;
  4319. case 192000:
  4320. tx_fs_rate_reg_val = 0x05;
  4321. rx_fs_rate_reg_val = 0xA0;
  4322. compander_fs = COMPANDER_FS_192KHZ;
  4323. break;
  4324. default:
  4325. pr_err("%s: Invalid sampling rate %d\n", __func__,
  4326. params_rate(params));
  4327. return -EINVAL;
  4328. }
  4329. switch (substream->stream) {
  4330. case SNDRV_PCM_STREAM_CAPTURE:
  4331. ret = tabla_set_decimator_rate(dai, tx_fs_rate_reg_val,
  4332. params_rate(params));
  4333. if (ret < 0) {
  4334. pr_err("%s: set decimator rate failed %d\n", __func__,
  4335. ret);
  4336. return ret;
  4337. }
  4338. if (tabla->intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
  4339. switch (params_format(params)) {
  4340. case SNDRV_PCM_FORMAT_S16_LE:
  4341. snd_soc_update_bits(codec,
  4342. TABLA_A_CDC_CLK_TX_I2S_CTL, 0x20, 0x20);
  4343. break;
  4344. case SNDRV_PCM_FORMAT_S32_LE:
  4345. snd_soc_update_bits(codec,
  4346. TABLA_A_CDC_CLK_TX_I2S_CTL, 0x20, 0x00);
  4347. break;
  4348. default:
  4349. pr_err("%s: Invalid format %d\n", __func__,
  4350. params_format(params));
  4351. return -EINVAL;
  4352. }
  4353. snd_soc_update_bits(codec, TABLA_A_CDC_CLK_TX_I2S_CTL,
  4354. 0x07, tx_fs_rate_reg_val);
  4355. } else {
  4356. switch (params_format(params)) {
  4357. case SNDRV_PCM_FORMAT_S16_LE:
  4358. tabla->dai[dai->id].bit_width = 16;
  4359. break;
  4360. default:
  4361. pr_err("%s: Invalid TX format %d\n", __func__,
  4362. params_format(params));
  4363. return -EINVAL;
  4364. }
  4365. tabla->dai[dai->id].rate = params_rate(params);
  4366. }
  4367. break;
  4368. case SNDRV_PCM_STREAM_PLAYBACK:
  4369. ret = tabla_set_interpolator_rate(dai, rx_fs_rate_reg_val,
  4370. compander_fs,
  4371. params_rate(params));
  4372. if (ret < 0) {
  4373. pr_err("%s: set decimator rate failed %d\n", __func__,
  4374. ret);
  4375. return ret;
  4376. }
  4377. if (tabla->intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
  4378. switch (params_format(params)) {
  4379. case SNDRV_PCM_FORMAT_S16_LE:
  4380. snd_soc_update_bits(codec,
  4381. TABLA_A_CDC_CLK_RX_I2S_CTL, 0x20, 0x20);
  4382. break;
  4383. case SNDRV_PCM_FORMAT_S32_LE:
  4384. snd_soc_update_bits(codec,
  4385. TABLA_A_CDC_CLK_RX_I2S_CTL, 0x20, 0x00);
  4386. break;
  4387. default:
  4388. pr_err("%s: Invalid RX format %d\n", __func__,
  4389. params_format(params));
  4390. return -EINVAL;
  4391. }
  4392. snd_soc_update_bits(codec, TABLA_A_CDC_CLK_RX_I2S_CTL,
  4393. 0x03, (rx_fs_rate_reg_val >> 0x05));
  4394. } else {
  4395. switch (params_format(params)) {
  4396. case SNDRV_PCM_FORMAT_S16_LE:
  4397. tabla->dai[dai->id].bit_width = 16;
  4398. break;
  4399. default:
  4400. pr_err("%s: Invalid format %d\n", __func__,
  4401. params_format(params));
  4402. return -EINVAL;
  4403. }
  4404. tabla->dai[dai->id].rate = params_rate(params);
  4405. }
  4406. break;
  4407. default:
  4408. pr_err("%s: Invalid stream type %d\n", __func__,
  4409. substream->stream);
  4410. return -EINVAL;
  4411. }
  4412. return 0;
  4413. }
  4414. static struct snd_soc_dai_ops tabla_dai_ops = {
  4415. .startup = tabla_startup,
  4416. .shutdown = tabla_shutdown,
  4417. .hw_params = tabla_hw_params,
  4418. .set_sysclk = tabla_set_dai_sysclk,
  4419. .set_fmt = tabla_set_dai_fmt,
  4420. .set_channel_map = tabla_set_channel_map,
  4421. .get_channel_map = tabla_get_channel_map,
  4422. };
  4423. static struct snd_soc_dai_driver tabla_dai[] = {
  4424. {
  4425. .name = "tabla_rx1",
  4426. .id = AIF1_PB,
  4427. .playback = {
  4428. .stream_name = "AIF1 Playback",
  4429. .rates = WCD9310_RATES,
  4430. .formats = TABLA_FORMATS,
  4431. .rate_max = 192000,
  4432. .rate_min = 8000,
  4433. .channels_min = 1,
  4434. .channels_max = 2,
  4435. },
  4436. .ops = &tabla_dai_ops,
  4437. },
  4438. {
  4439. .name = "tabla_tx1",
  4440. .id = AIF1_CAP,
  4441. .capture = {
  4442. .stream_name = "AIF1 Capture",
  4443. .rates = WCD9310_RATES,
  4444. .formats = TABLA_FORMATS,
  4445. .rate_max = 192000,
  4446. .rate_min = 8000,
  4447. .channels_min = 1,
  4448. .channels_max = 4,
  4449. },
  4450. .ops = &tabla_dai_ops,
  4451. },
  4452. {
  4453. .name = "tabla_rx2",
  4454. .id = AIF2_PB,
  4455. .playback = {
  4456. .stream_name = "AIF2 Playback",
  4457. .rates = WCD9310_RATES,
  4458. .formats = TABLA_FORMATS,
  4459. .rate_min = 8000,
  4460. .rate_max = 192000,
  4461. .channels_min = 1,
  4462. .channels_max = 2,
  4463. },
  4464. .ops = &tabla_dai_ops,
  4465. },
  4466. {
  4467. .name = "tabla_tx2",
  4468. .id = AIF2_CAP,
  4469. .capture = {
  4470. .stream_name = "AIF2 Capture",
  4471. .rates = WCD9310_RATES,
  4472. .formats = TABLA_FORMATS,
  4473. .rate_max = 192000,
  4474. .rate_min = 8000,
  4475. .channels_min = 1,
  4476. .channels_max = 4,
  4477. },
  4478. .ops = &tabla_dai_ops,
  4479. },
  4480. {
  4481. .name = "tabla_tx3",
  4482. .id = AIF3_CAP,
  4483. .capture = {
  4484. .stream_name = "AIF3 Capture",
  4485. .rates = WCD9310_RATES,
  4486. .formats = TABLA_FORMATS,
  4487. .rate_max = 48000,
  4488. .rate_min = 8000,
  4489. .channels_min = 1,
  4490. .channels_max = 2,
  4491. },
  4492. .ops = &tabla_dai_ops,
  4493. },
  4494. {
  4495. .name = "tabla_rx3",
  4496. .id = AIF3_PB,
  4497. .playback = {
  4498. .stream_name = "AIF3 Playback",
  4499. .rates = WCD9310_RATES,
  4500. .formats = TABLA_FORMATS,
  4501. .rate_min = 8000,
  4502. .rate_max = 192000,
  4503. .channels_min = 1,
  4504. .channels_max = 2,
  4505. },
  4506. .ops = &tabla_dai_ops,
  4507. },
  4508. };
  4509. static struct snd_soc_dai_driver tabla_i2s_dai[] = {
  4510. {
  4511. .name = "tabla_i2s_rx1",
  4512. .id = AIF1_PB,
  4513. .playback = {
  4514. .stream_name = "AIF1 Playback",
  4515. .rates = WCD9310_RATES,
  4516. .formats = TABLA_FORMATS,
  4517. .rate_max = 192000,
  4518. .rate_min = 8000,
  4519. .channels_min = 1,
  4520. .channels_max = 4,
  4521. },
  4522. .ops = &tabla_dai_ops,
  4523. },
  4524. {
  4525. .name = "tabla_i2s_tx1",
  4526. .id = AIF1_CAP,
  4527. .capture = {
  4528. .stream_name = "AIF1 Capture",
  4529. .rates = WCD9310_RATES,
  4530. .formats = TABLA_FORMATS,
  4531. .rate_max = 192000,
  4532. .rate_min = 8000,
  4533. .channels_min = 1,
  4534. .channels_max = 4,
  4535. },
  4536. .ops = &tabla_dai_ops,
  4537. },
  4538. };
  4539. static int tabla_codec_enable_chmask(struct tabla_priv *tabla_p,
  4540. int event, int index)
  4541. {
  4542. int ret = 0;
  4543. struct wcd9xxx_ch *ch;
  4544. switch (event) {
  4545. case SND_SOC_DAPM_POST_PMU:
  4546. list_for_each_entry(ch,
  4547. &tabla_p->dai[index].wcd9xxx_ch_list, list) {
  4548. ret = wcd9xxx_get_slave_port(ch->ch_num);
  4549. if (ret < 0) {
  4550. pr_err("%s: Invalid slave port ID: %d\n",
  4551. __func__, ret);
  4552. ret = -EINVAL;
  4553. break;
  4554. }
  4555. tabla_p->dai[index].ch_mask |= 1 << ret;
  4556. }
  4557. break;
  4558. case SND_SOC_DAPM_POST_PMD:
  4559. ret = wait_event_timeout(tabla_p->dai[index].dai_wait,
  4560. (tabla_p->dai[index].ch_mask == 0),
  4561. msecs_to_jiffies(SLIM_CLOSE_TIMEOUT));
  4562. if (!ret) {
  4563. pr_err("%s: Slim close tx/rx wait timeout\n",
  4564. __func__);
  4565. ret = -EINVAL;
  4566. }
  4567. break;
  4568. }
  4569. return ret;
  4570. }
  4571. static int tabla_codec_enable_slimrx(struct snd_soc_dapm_widget *w,
  4572. struct snd_kcontrol *kcontrol,
  4573. int event)
  4574. {
  4575. struct wcd9xxx *core;
  4576. struct snd_soc_codec *codec = w->codec;
  4577. struct tabla_priv *tabla_p = snd_soc_codec_get_drvdata(codec);
  4578. u32 ret = 0;
  4579. struct wcd9xxx_codec_dai_data *dai;
  4580. core = dev_get_drvdata(codec->dev->parent);
  4581. pr_debug("%s: event called! codec name %s num_dai %d\n"
  4582. "stream name %s event %d\n",
  4583. __func__, w->codec->name, w->codec->num_dai,
  4584. w->sname, event);
  4585. /* Execute the callback only if interface type is slimbus */
  4586. if (tabla_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
  4587. if (event == SND_SOC_DAPM_POST_PMD && (core != NULL) &&
  4588. (core->dev != NULL) &&
  4589. (core->dev->parent != NULL)) {
  4590. pm_runtime_mark_last_busy(core->dev->parent);
  4591. pm_runtime_put(core->dev->parent);
  4592. }
  4593. return 0;
  4594. }
  4595. pr_debug("%s: w->name %s w->shift %d event %d\n",
  4596. __func__, w->name, w->shift, event);
  4597. dai = &tabla_p->dai[w->shift];
  4598. switch (event) {
  4599. case SND_SOC_DAPM_POST_PMU:
  4600. ret = tabla_codec_enable_chmask(tabla_p, SND_SOC_DAPM_POST_PMU,
  4601. w->shift);
  4602. ret = wcd9xxx_cfg_slim_sch_rx(core, &dai->wcd9xxx_ch_list,
  4603. dai->rate, dai->bit_width,
  4604. &dai->grph);
  4605. break;
  4606. case SND_SOC_DAPM_POST_PMD:
  4607. ret = wcd9xxx_close_slim_sch_rx(core,
  4608. &dai->wcd9xxx_ch_list,
  4609. dai->grph);
  4610. ret = tabla_codec_enable_chmask(tabla_p, SND_SOC_DAPM_POST_PMD,
  4611. w->shift);
  4612. if (ret < 0) {
  4613. ret = wcd9xxx_disconnect_port(core,
  4614. &dai->wcd9xxx_ch_list,
  4615. dai->grph);
  4616. pr_info("%s: Disconnect RX port, ret = %d\n",
  4617. __func__, ret);
  4618. }
  4619. if ((core != NULL) &&
  4620. (core->dev != NULL) &&
  4621. (core->dev->parent != NULL)) {
  4622. pm_runtime_mark_last_busy(core->dev->parent);
  4623. pm_runtime_put(core->dev->parent);
  4624. }
  4625. break;
  4626. }
  4627. return ret;
  4628. }
  4629. static int tabla_codec_enable_slimtx(struct snd_soc_dapm_widget *w,
  4630. struct snd_kcontrol *kcontrol,
  4631. int event)
  4632. {
  4633. struct wcd9xxx *core;
  4634. struct snd_soc_codec *codec = w->codec;
  4635. struct tabla_priv *tabla_p = snd_soc_codec_get_drvdata(codec);
  4636. u32 ret = 0;
  4637. struct wcd9xxx_codec_dai_data *dai;
  4638. core = dev_get_drvdata(codec->dev->parent);
  4639. pr_debug("%s: event called! codec name %s num_dai %d\n"
  4640. "stream name %s\n", __func__, w->codec->name,
  4641. w->codec->num_dai, w->sname);
  4642. /* Execute the callback only if interface type is slimbus */
  4643. if (tabla_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
  4644. if (event == SND_SOC_DAPM_POST_PMD && (core != NULL) &&
  4645. (core->dev != NULL) &&
  4646. (core->dev->parent != NULL)) {
  4647. pm_runtime_mark_last_busy(core->dev->parent);
  4648. pm_runtime_put(core->dev->parent);
  4649. }
  4650. return 0;
  4651. }
  4652. pr_debug("%s(): %s %d\n", __func__, w->name, event);
  4653. dai = &tabla_p->dai[w->shift];
  4654. switch (event) {
  4655. case SND_SOC_DAPM_POST_PMU:
  4656. ret = tabla_codec_enable_chmask(tabla_p, SND_SOC_DAPM_POST_PMU,
  4657. w->shift);
  4658. ret = wcd9xxx_cfg_slim_sch_tx(core, &dai->wcd9xxx_ch_list,
  4659. dai->rate,
  4660. dai->bit_width,
  4661. &dai->grph);
  4662. break;
  4663. case SND_SOC_DAPM_POST_PMD:
  4664. ret = wcd9xxx_close_slim_sch_tx(core, &dai->wcd9xxx_ch_list,
  4665. dai->grph);
  4666. ret = tabla_codec_enable_chmask(tabla_p, SND_SOC_DAPM_POST_PMD,
  4667. w->shift);
  4668. if (ret < 0) {
  4669. ret = wcd9xxx_disconnect_port(core,
  4670. &dai->wcd9xxx_ch_list,
  4671. dai->grph);
  4672. pr_info("%s: Disconnect TX port, ret = %d\n",
  4673. __func__, ret);
  4674. }
  4675. if ((core != NULL) &&
  4676. (core->dev != NULL) &&
  4677. (core->dev->parent != NULL)) {
  4678. pm_runtime_mark_last_busy(core->dev->parent);
  4679. pm_runtime_put(core->dev->parent);
  4680. }
  4681. break;
  4682. }
  4683. return ret;
  4684. }
  4685. /* Todo: Have seperate dapm widgets for I2S and Slimbus.
  4686. * Might Need to have callbacks registered only for slimbus
  4687. */
  4688. static const struct snd_soc_dapm_widget tabla_dapm_widgets[] = {
  4689. /*RX stuff */
  4690. SND_SOC_DAPM_OUTPUT("EAR"),
  4691. SND_SOC_DAPM_PGA_E("EAR PA", SND_SOC_NOPM, 0, 0, NULL,
  4692. 0, tabla_ear_pa_event, SND_SOC_DAPM_PRE_PMU |
  4693. SND_SOC_DAPM_PRE_PMD),
  4694. SND_SOC_DAPM_MIXER("DAC1", SND_SOC_NOPM, 0, 0, dac1_switch,
  4695. ARRAY_SIZE(dac1_switch)),
  4696. SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
  4697. AIF1_PB, 0, tabla_codec_enable_slimrx,
  4698. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4699. SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
  4700. AIF2_PB, 0, tabla_codec_enable_slimrx,
  4701. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4702. SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
  4703. AIF3_PB, 0, tabla_codec_enable_slimrx,
  4704. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4705. SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, TABLA_RX1, 0,
  4706. &slim_rx_mux[TABLA_RX1]),
  4707. SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, TABLA_RX2, 0,
  4708. &slim_rx_mux[TABLA_RX2]),
  4709. SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, TABLA_RX3, 0,
  4710. &slim_rx_mux[TABLA_RX3]),
  4711. SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, TABLA_RX4, 0,
  4712. &slim_rx_mux[TABLA_RX4]),
  4713. SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, TABLA_RX5, 0,
  4714. &slim_rx_mux[TABLA_RX5]),
  4715. SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, TABLA_RX6, 0,
  4716. &slim_rx_mux[TABLA_RX6]),
  4717. SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, TABLA_RX7, 0,
  4718. &slim_rx_mux[TABLA_RX7]),
  4719. SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  4720. SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
  4721. SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
  4722. SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
  4723. SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
  4724. SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
  4725. SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
  4726. /* Headphone */
  4727. SND_SOC_DAPM_OUTPUT("HEADPHONE"),
  4728. SND_SOC_DAPM_PGA_E("HPHL", TABLA_A_RX_HPH_CNP_EN, 5, 0, NULL, 0,
  4729. tabla_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
  4730. SND_SOC_DAPM_POST_PMD),
  4731. SND_SOC_DAPM_MIXER("HPHL DAC", TABLA_A_RX_HPH_L_DAC_CTL, 7, 0,
  4732. hphl_switch, ARRAY_SIZE(hphl_switch)),
  4733. SND_SOC_DAPM_PGA_E("HPHR", TABLA_A_RX_HPH_CNP_EN, 4, 0, NULL, 0,
  4734. tabla_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
  4735. SND_SOC_DAPM_POST_PMD),
  4736. SND_SOC_DAPM_DAC_E("HPHR DAC", NULL, TABLA_A_RX_HPH_R_DAC_CTL, 7, 0,
  4737. tabla_hphr_dac_event,
  4738. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4739. /* Speaker */
  4740. SND_SOC_DAPM_OUTPUT("LINEOUT1"),
  4741. SND_SOC_DAPM_OUTPUT("LINEOUT2"),
  4742. SND_SOC_DAPM_OUTPUT("LINEOUT3"),
  4743. SND_SOC_DAPM_OUTPUT("LINEOUT4"),
  4744. SND_SOC_DAPM_OUTPUT("LINEOUT5"),
  4745. SND_SOC_DAPM_PGA_E("LINEOUT1 PA", TABLA_A_RX_LINE_CNP_EN, 0, 0, NULL,
  4746. 0, tabla_codec_enable_lineout, SND_SOC_DAPM_PRE_PMU |
  4747. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4748. SND_SOC_DAPM_PGA_E("LINEOUT2 PA", TABLA_A_RX_LINE_CNP_EN, 1, 0, NULL,
  4749. 0, tabla_codec_enable_lineout, SND_SOC_DAPM_PRE_PMU |
  4750. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4751. SND_SOC_DAPM_PGA_E("LINEOUT3 PA", TABLA_A_RX_LINE_CNP_EN, 2, 0, NULL,
  4752. 0, tabla_codec_enable_lineout, SND_SOC_DAPM_PRE_PMU |
  4753. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4754. SND_SOC_DAPM_PGA_E("LINEOUT4 PA", TABLA_A_RX_LINE_CNP_EN, 3, 0, NULL,
  4755. 0, tabla_codec_enable_lineout, SND_SOC_DAPM_PRE_PMU |
  4756. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4757. SND_SOC_DAPM_PGA_E("LINEOUT5 PA", TABLA_A_RX_LINE_CNP_EN, 4, 0, NULL, 0,
  4758. tabla_codec_enable_lineout, SND_SOC_DAPM_PRE_PMU |
  4759. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4760. SND_SOC_DAPM_DAC_E("LINEOUT1 DAC", NULL, TABLA_A_RX_LINE_1_DAC_CTL, 7, 0
  4761. , tabla_lineout_dac_event,
  4762. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4763. SND_SOC_DAPM_DAC_E("LINEOUT2 DAC", NULL, TABLA_A_RX_LINE_2_DAC_CTL, 7, 0
  4764. , tabla_lineout_dac_event,
  4765. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4766. SND_SOC_DAPM_DAC_E("LINEOUT3 DAC", NULL, TABLA_A_RX_LINE_3_DAC_CTL, 7, 0
  4767. , tabla_lineout_dac_event,
  4768. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4769. SND_SOC_DAPM_SWITCH("LINEOUT3 DAC GROUND", SND_SOC_NOPM, 0, 0,
  4770. &lineout3_ground_switch),
  4771. SND_SOC_DAPM_DAC_E("LINEOUT4 DAC", NULL, TABLA_A_RX_LINE_4_DAC_CTL, 7, 0
  4772. , tabla_lineout_dac_event,
  4773. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4774. SND_SOC_DAPM_SWITCH("LINEOUT4 DAC GROUND", SND_SOC_NOPM, 0, 0,
  4775. &lineout4_ground_switch),
  4776. SND_SOC_DAPM_DAC_E("LINEOUT5 DAC", NULL, TABLA_A_RX_LINE_5_DAC_CTL, 7, 0
  4777. , tabla_lineout_dac_event,
  4778. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4779. SND_SOC_DAPM_MIXER_E("RX1 MIX2", TABLA_A_CDC_CLK_RX_B1_CTL, 0, 0, NULL,
  4780. 0, tabla_codec_reset_interpolator, SND_SOC_DAPM_PRE_PMU |
  4781. SND_SOC_DAPM_POST_PMU),
  4782. SND_SOC_DAPM_MIXER_E("RX2 MIX2", TABLA_A_CDC_CLK_RX_B1_CTL, 1, 0, NULL,
  4783. 0, tabla_codec_reset_interpolator, SND_SOC_DAPM_PRE_PMU |
  4784. SND_SOC_DAPM_POST_PMU),
  4785. SND_SOC_DAPM_MIXER_E("RX3 MIX2", TABLA_A_CDC_CLK_RX_B1_CTL, 2, 0, NULL,
  4786. 0, tabla_codec_reset_interpolator, SND_SOC_DAPM_PRE_PMU |
  4787. SND_SOC_DAPM_POST_PMU),
  4788. SND_SOC_DAPM_MIXER_E("RX4 MIX1", TABLA_A_CDC_CLK_RX_B1_CTL, 3, 0, NULL,
  4789. 0, tabla_codec_reset_interpolator, SND_SOC_DAPM_PRE_PMU |
  4790. SND_SOC_DAPM_POST_PMU),
  4791. SND_SOC_DAPM_MIXER_E("RX5 MIX1", TABLA_A_CDC_CLK_RX_B1_CTL, 4, 0, NULL,
  4792. 0, tabla_codec_reset_interpolator, SND_SOC_DAPM_PRE_PMU |
  4793. SND_SOC_DAPM_POST_PMU),
  4794. SND_SOC_DAPM_MIXER_E("RX6 MIX1", TABLA_A_CDC_CLK_RX_B1_CTL, 5, 0, NULL,
  4795. 0, tabla_codec_reset_interpolator, SND_SOC_DAPM_PRE_PMU |
  4796. SND_SOC_DAPM_POST_PMU),
  4797. SND_SOC_DAPM_MIXER_E("RX7 MIX1", TABLA_A_CDC_CLK_RX_B1_CTL, 6, 0, NULL,
  4798. 0, tabla_codec_reset_interpolator, SND_SOC_DAPM_PRE_PMU |
  4799. SND_SOC_DAPM_POST_PMU),
  4800. SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  4801. SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  4802. SND_SOC_DAPM_MIXER("RX3 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  4803. SND_SOC_DAPM_MUX_E("RX4 DSM MUX", TABLA_A_CDC_CLK_RX_B1_CTL, 3, 0,
  4804. &rx4_dsm_mux, tabla_codec_reset_interpolator,
  4805. SND_SOC_DAPM_PRE_PMU),
  4806. SND_SOC_DAPM_MUX_E("RX6 DSM MUX", TABLA_A_CDC_CLK_RX_B1_CTL, 5, 0,
  4807. &rx6_dsm_mux, tabla_codec_reset_interpolator,
  4808. SND_SOC_DAPM_PRE_PMU),
  4809. SND_SOC_DAPM_MIXER_E("RX1 CHAIN", SND_SOC_NOPM, 5, 0, NULL,
  4810. 0, tabla_codec_hphr_dem_input_selection,
  4811. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
  4812. SND_SOC_DAPM_MIXER_E("RX2 CHAIN", SND_SOC_NOPM, 5, 0, NULL,
  4813. 0, tabla_codec_hphl_dem_input_selection,
  4814. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
  4815. SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  4816. &rx_mix1_inp1_mux),
  4817. SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  4818. &rx_mix1_inp2_mux),
  4819. SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0,
  4820. &rx_mix1_inp3_mux),
  4821. SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  4822. &rx2_mix1_inp1_mux),
  4823. SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  4824. &rx2_mix1_inp2_mux),
  4825. SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  4826. &rx3_mix1_inp1_mux),
  4827. SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  4828. &rx3_mix1_inp2_mux),
  4829. SND_SOC_DAPM_MUX("RX4 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  4830. &rx4_mix1_inp1_mux),
  4831. SND_SOC_DAPM_MUX("RX4 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  4832. &rx4_mix1_inp2_mux),
  4833. SND_SOC_DAPM_MUX("RX5 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  4834. &rx5_mix1_inp1_mux),
  4835. SND_SOC_DAPM_MUX("RX5 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  4836. &rx5_mix1_inp2_mux),
  4837. SND_SOC_DAPM_MUX("RX6 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  4838. &rx6_mix1_inp1_mux),
  4839. SND_SOC_DAPM_MUX("RX6 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  4840. &rx6_mix1_inp2_mux),
  4841. SND_SOC_DAPM_MUX("RX7 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  4842. &rx7_mix1_inp1_mux),
  4843. SND_SOC_DAPM_MUX("RX7 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  4844. &rx7_mix1_inp2_mux),
  4845. SND_SOC_DAPM_MUX("RX1 MIX2 INP1", SND_SOC_NOPM, 0, 0,
  4846. &rx1_mix2_inp1_mux),
  4847. SND_SOC_DAPM_MUX("RX1 MIX2 INP2", SND_SOC_NOPM, 0, 0,
  4848. &rx1_mix2_inp2_mux),
  4849. SND_SOC_DAPM_MUX("RX2 MIX2 INP1", SND_SOC_NOPM, 0, 0,
  4850. &rx2_mix2_inp1_mux),
  4851. SND_SOC_DAPM_MUX("RX2 MIX2 INP2", SND_SOC_NOPM, 0, 0,
  4852. &rx2_mix2_inp2_mux),
  4853. SND_SOC_DAPM_MUX("RX3 MIX2 INP1", SND_SOC_NOPM, 0, 0,
  4854. &rx3_mix2_inp1_mux),
  4855. SND_SOC_DAPM_MUX("RX3 MIX2 INP2", SND_SOC_NOPM, 0, 0,
  4856. &rx3_mix2_inp2_mux),
  4857. SND_SOC_DAPM_SUPPLY("CP", TABLA_A_CP_EN, 0, 0,
  4858. tabla_codec_enable_charge_pump, SND_SOC_DAPM_POST_PMU |
  4859. SND_SOC_DAPM_PRE_PMD),
  4860. SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0,
  4861. tabla_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
  4862. SND_SOC_DAPM_POST_PMD),
  4863. /* TX */
  4864. SND_SOC_DAPM_SUPPLY("CDC_CONN", TABLA_A_CDC_CLK_OTHR_CTL, 2, 0, NULL,
  4865. 0),
  4866. SND_SOC_DAPM_SUPPLY("LDO_H", SND_SOC_NOPM, 0, 0,
  4867. tabla_codec_enable_ldo_h, SND_SOC_DAPM_PRE_PMU |
  4868. SND_SOC_DAPM_POST_PMD),
  4869. SND_SOC_DAPM_SUPPLY("COMP1_CLK", SND_SOC_NOPM, 0, 0,
  4870. tabla_config_compander, SND_SOC_DAPM_PRE_PMU |
  4871. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
  4872. SND_SOC_DAPM_SUPPLY("COMP2_CLK", SND_SOC_NOPM, 1, 0,
  4873. tabla_config_compander, SND_SOC_DAPM_PRE_PMU |
  4874. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
  4875. SND_SOC_DAPM_INPUT("AMIC1"),
  4876. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 External", SND_SOC_NOPM, 0, 0,
  4877. tabla_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
  4878. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4879. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 Internal1", SND_SOC_NOPM, 0, 0,
  4880. tabla_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
  4881. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4882. SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 Internal2", SND_SOC_NOPM, 0, 0,
  4883. tabla_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
  4884. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4885. SND_SOC_DAPM_ADC_E("ADC1", NULL, TABLA_A_TX_1_2_EN, 7, 0,
  4886. tabla_codec_enable_adc, SND_SOC_DAPM_PRE_PMU |
  4887. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4888. SND_SOC_DAPM_INPUT("AMIC3"),
  4889. SND_SOC_DAPM_ADC_E("ADC3", NULL, TABLA_A_TX_3_4_EN, 7, 0,
  4890. tabla_codec_enable_adc, SND_SOC_DAPM_PRE_PMU |
  4891. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4892. SND_SOC_DAPM_INPUT("AMIC4"),
  4893. SND_SOC_DAPM_ADC_E("ADC4", NULL, TABLA_A_TX_3_4_EN, 3, 0,
  4894. tabla_codec_enable_adc, SND_SOC_DAPM_PRE_PMU |
  4895. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4896. SND_SOC_DAPM_INPUT("AMIC5"),
  4897. SND_SOC_DAPM_ADC_E("ADC5", NULL, TABLA_A_TX_5_6_EN, 7, 0,
  4898. tabla_codec_enable_adc, SND_SOC_DAPM_POST_PMU),
  4899. SND_SOC_DAPM_INPUT("AMIC6"),
  4900. SND_SOC_DAPM_ADC_E("ADC6", NULL, TABLA_A_TX_5_6_EN, 3, 0,
  4901. tabla_codec_enable_adc, SND_SOC_DAPM_POST_PMU),
  4902. SND_SOC_DAPM_MUX_E("DEC1 MUX", TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL, 0, 0,
  4903. &dec1_mux, tabla_codec_enable_dec,
  4904. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4905. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4906. SND_SOC_DAPM_MUX_E("DEC2 MUX", TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL, 1, 0,
  4907. &dec2_mux, tabla_codec_enable_dec,
  4908. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4909. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4910. SND_SOC_DAPM_MUX_E("DEC3 MUX", TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL, 2, 0,
  4911. &dec3_mux, tabla_codec_enable_dec,
  4912. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4913. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4914. SND_SOC_DAPM_MUX_E("DEC4 MUX", TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL, 3, 0,
  4915. &dec4_mux, tabla_codec_enable_dec,
  4916. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4917. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4918. SND_SOC_DAPM_MUX_E("DEC5 MUX", TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL, 4, 0,
  4919. &dec5_mux, tabla_codec_enable_dec,
  4920. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4921. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4922. SND_SOC_DAPM_MUX_E("DEC6 MUX", TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL, 5, 0,
  4923. &dec6_mux, tabla_codec_enable_dec,
  4924. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4925. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4926. SND_SOC_DAPM_MUX_E("DEC7 MUX", TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL, 6, 0,
  4927. &dec7_mux, tabla_codec_enable_dec,
  4928. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4929. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4930. SND_SOC_DAPM_MUX_E("DEC8 MUX", TABLA_A_CDC_CLK_TX_CLK_EN_B1_CTL, 7, 0,
  4931. &dec8_mux, tabla_codec_enable_dec,
  4932. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4933. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4934. SND_SOC_DAPM_MUX_E("DEC9 MUX", TABLA_A_CDC_CLK_TX_CLK_EN_B2_CTL, 0, 0,
  4935. &dec9_mux, tabla_codec_enable_dec,
  4936. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4937. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4938. SND_SOC_DAPM_MUX_E("DEC10 MUX", TABLA_A_CDC_CLK_TX_CLK_EN_B2_CTL, 1, 0,
  4939. &dec10_mux, tabla_codec_enable_dec,
  4940. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4941. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4942. SND_SOC_DAPM_MUX("ANC1 MUX", SND_SOC_NOPM, 0, 0, &anc1_mux),
  4943. SND_SOC_DAPM_MUX("ANC2 MUX", SND_SOC_NOPM, 0, 0, &anc2_mux),
  4944. SND_SOC_DAPM_OUTPUT("ANC HEADPHONE"),
  4945. SND_SOC_DAPM_PGA_E("ANC HPHL", SND_SOC_NOPM, 0, 0, NULL, 0,
  4946. tabla_codec_enable_anc,
  4947. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4948. SND_SOC_DAPM_PGA_E("ANC HPHR", SND_SOC_NOPM, 0, 0, NULL, 0,
  4949. tabla_codec_enable_anc, SND_SOC_DAPM_PRE_PMU),
  4950. SND_SOC_DAPM_MUX("ANC1 FB MUX", SND_SOC_NOPM, 0, 0, &anc1_fb_mux),
  4951. SND_SOC_DAPM_INPUT("AMIC2"),
  4952. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 External", SND_SOC_NOPM, 0, 0,
  4953. tabla_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
  4954. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4955. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 Power External",
  4956. TABLA_A_MICB_2_CTL, 7, 0,
  4957. tabla_codec_enable_micbias_power,
  4958. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4959. SND_SOC_DAPM_POST_PMD),
  4960. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 Internal1", SND_SOC_NOPM, 0, 0,
  4961. tabla_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
  4962. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4963. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 Internal2", SND_SOC_NOPM, 0, 0,
  4964. tabla_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
  4965. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4966. SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 Internal3", SND_SOC_NOPM, 0, 0,
  4967. tabla_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
  4968. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4969. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3 External", SND_SOC_NOPM, 0, 0,
  4970. tabla_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
  4971. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4972. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3 Internal1", SND_SOC_NOPM, 0, 0,
  4973. tabla_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
  4974. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4975. SND_SOC_DAPM_MICBIAS_E("MIC BIAS3 Internal2", SND_SOC_NOPM, 0, 0,
  4976. tabla_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
  4977. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4978. SND_SOC_DAPM_ADC_E("ADC2", NULL, TABLA_A_TX_1_2_EN, 3, 0,
  4979. tabla_codec_enable_adc, SND_SOC_DAPM_PRE_PMU |
  4980. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4981. SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
  4982. AIF1_CAP, 0, tabla_codec_enable_slimtx,
  4983. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4984. SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
  4985. AIF2_CAP, 0, tabla_codec_enable_slimtx,
  4986. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4987. SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
  4988. AIF3_CAP, 0, tabla_codec_enable_slimtx,
  4989. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4990. SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
  4991. aif_cap_mixer, ARRAY_SIZE(aif_cap_mixer)),
  4992. SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
  4993. aif_cap_mixer, ARRAY_SIZE(aif_cap_mixer)),
  4994. SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
  4995. aif_cap_mixer, ARRAY_SIZE(aif_cap_mixer)),
  4996. SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, TABLA_TX1, 0,
  4997. &sb_tx1_mux),
  4998. SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, TABLA_TX2, 0,
  4999. &sb_tx2_mux),
  5000. SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, TABLA_TX3, 0,
  5001. &sb_tx3_mux),
  5002. SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, TABLA_TX4, 0,
  5003. &sb_tx4_mux),
  5004. SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, TABLA_TX5, 0,
  5005. &sb_tx5_mux),
  5006. SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, TABLA_TX6, 0,
  5007. &sb_tx6_mux),
  5008. SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, TABLA_TX7, 0,
  5009. &sb_tx7_mux),
  5010. SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, TABLA_TX8, 0,
  5011. &sb_tx8_mux),
  5012. SND_SOC_DAPM_MUX("SLIM TX9 MUX", SND_SOC_NOPM, TABLA_TX9, 0,
  5013. &sb_tx9_mux),
  5014. SND_SOC_DAPM_MUX("SLIM TX10 MUX", SND_SOC_NOPM, TABLA_TX10, 0,
  5015. &sb_tx10_mux),
  5016. /* Digital Mic Inputs */
  5017. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  5018. tabla_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
  5019. SND_SOC_DAPM_POST_PMD),
  5020. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
  5021. tabla_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
  5022. SND_SOC_DAPM_POST_PMD),
  5023. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
  5024. tabla_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
  5025. SND_SOC_DAPM_POST_PMD),
  5026. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
  5027. tabla_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
  5028. SND_SOC_DAPM_POST_PMD),
  5029. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
  5030. tabla_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
  5031. SND_SOC_DAPM_POST_PMD),
  5032. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 0, 0,
  5033. tabla_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
  5034. SND_SOC_DAPM_POST_PMD),
  5035. /* Sidetone */
  5036. SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
  5037. SND_SOC_DAPM_PGA("IIR1", TABLA_A_CDC_CLK_SD_CTL, 0, 0, NULL, 0),
  5038. SND_SOC_DAPM_MUX("IIR2 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir2_inp1_mux),
  5039. SND_SOC_DAPM_PGA("IIR2", TABLA_A_CDC_CLK_SD_CTL, 1, 0, NULL, 0),
  5040. /* AUX PGA */
  5041. SND_SOC_DAPM_ADC_E("AUX_PGA_Left", NULL, TABLA_A_AUX_L_EN, 7, 0,
  5042. tabla_codec_enable_aux_pga, SND_SOC_DAPM_PRE_PMU |
  5043. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
  5044. SND_SOC_DAPM_POST_PMD),
  5045. SND_SOC_DAPM_ADC_E("AUX_PGA_Right", NULL, TABLA_A_AUX_R_EN, 7, 0,
  5046. tabla_codec_enable_aux_pga, SND_SOC_DAPM_PRE_PMU |
  5047. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
  5048. SND_SOC_DAPM_POST_PMD),
  5049. /* Lineout, ear and HPH PA Mixers */
  5050. SND_SOC_DAPM_MIXER("HPHL_PA_MIXER", SND_SOC_NOPM, 0, 0,
  5051. hphl_pa_mix, ARRAY_SIZE(hphl_pa_mix)),
  5052. SND_SOC_DAPM_MIXER("HPHR_PA_MIXER", SND_SOC_NOPM, 0, 0,
  5053. hphr_pa_mix, ARRAY_SIZE(hphr_pa_mix)),
  5054. SND_SOC_DAPM_MIXER("LINEOUT1_PA_MIXER", SND_SOC_NOPM, 0, 0,
  5055. lineout1_pa_mix, ARRAY_SIZE(lineout1_pa_mix)),
  5056. SND_SOC_DAPM_MIXER("LINEOUT2_PA_MIXER", SND_SOC_NOPM, 0, 0,
  5057. lineout2_pa_mix, ARRAY_SIZE(lineout2_pa_mix)),
  5058. SND_SOC_DAPM_MIXER("LINEOUT3_PA_MIXER", SND_SOC_NOPM, 0, 0,
  5059. lineout3_pa_mix, ARRAY_SIZE(lineout3_pa_mix)),
  5060. SND_SOC_DAPM_MIXER("LINEOUT4_PA_MIXER", SND_SOC_NOPM, 0, 0,
  5061. lineout4_pa_mix, ARRAY_SIZE(lineout4_pa_mix)),
  5062. SND_SOC_DAPM_MIXER("LINEOUT5_PA_MIXER", SND_SOC_NOPM, 0, 0,
  5063. lineout5_pa_mix, ARRAY_SIZE(lineout5_pa_mix)),
  5064. SND_SOC_DAPM_MIXER("EAR_PA_MIXER", SND_SOC_NOPM, 0, 0,
  5065. ear_pa_mix, ARRAY_SIZE(ear_pa_mix)),
  5066. };
  5067. static short tabla_codec_read_sta_result(struct snd_soc_codec *codec)
  5068. {
  5069. u8 bias_msb, bias_lsb;
  5070. short bias_value;
  5071. bias_msb = snd_soc_read(codec, TABLA_A_CDC_MBHC_B3_STATUS);
  5072. bias_lsb = snd_soc_read(codec, TABLA_A_CDC_MBHC_B2_STATUS);
  5073. bias_value = (bias_msb << 8) | bias_lsb;
  5074. return bias_value;
  5075. }
  5076. static short tabla_codec_read_dce_result(struct snd_soc_codec *codec)
  5077. {
  5078. u8 bias_msb, bias_lsb;
  5079. short bias_value;
  5080. bias_msb = snd_soc_read(codec, TABLA_A_CDC_MBHC_B5_STATUS);
  5081. bias_lsb = snd_soc_read(codec, TABLA_A_CDC_MBHC_B4_STATUS);
  5082. bias_value = (bias_msb << 8) | bias_lsb;
  5083. return bias_value;
  5084. }
  5085. static void tabla_turn_onoff_rel_detection(struct snd_soc_codec *codec, bool on)
  5086. {
  5087. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x02, on << 1);
  5088. }
  5089. static short __tabla_codec_sta_dce(struct snd_soc_codec *codec, int dce,
  5090. bool override_bypass, bool noreldetection)
  5091. {
  5092. short bias_value;
  5093. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  5094. wcd9xxx_disable_irq(codec->control_data, WCD9XXX_IRQ_MBHC_POTENTIAL);
  5095. if (noreldetection)
  5096. tabla_turn_onoff_rel_detection(codec, false);
  5097. /* Turn on the override */
  5098. if (!override_bypass)
  5099. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x4, 0x4);
  5100. if (dce) {
  5101. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x8, 0x8);
  5102. snd_soc_write(codec, TABLA_A_CDC_MBHC_EN_CTL, 0x4);
  5103. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x8, 0x0);
  5104. usleep_range(tabla->mbhc_data.t_sta_dce,
  5105. tabla->mbhc_data.t_sta_dce);
  5106. snd_soc_write(codec, TABLA_A_CDC_MBHC_EN_CTL, 0x4);
  5107. usleep_range(tabla->mbhc_data.t_dce,
  5108. tabla->mbhc_data.t_dce);
  5109. bias_value = tabla_codec_read_dce_result(codec);
  5110. } else {
  5111. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x8, 0x8);
  5112. snd_soc_write(codec, TABLA_A_CDC_MBHC_EN_CTL, 0x2);
  5113. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x8, 0x0);
  5114. usleep_range(tabla->mbhc_data.t_sta_dce,
  5115. tabla->mbhc_data.t_sta_dce);
  5116. snd_soc_write(codec, TABLA_A_CDC_MBHC_EN_CTL, 0x2);
  5117. usleep_range(tabla->mbhc_data.t_sta,
  5118. tabla->mbhc_data.t_sta);
  5119. bias_value = tabla_codec_read_sta_result(codec);
  5120. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x8, 0x8);
  5121. snd_soc_write(codec, TABLA_A_CDC_MBHC_EN_CTL, 0x0);
  5122. }
  5123. /* Turn off the override after measuring mic voltage */
  5124. if (!override_bypass)
  5125. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x04, 0x00);
  5126. if (noreldetection)
  5127. tabla_turn_onoff_rel_detection(codec, true);
  5128. wcd9xxx_enable_irq(codec->control_data, WCD9XXX_IRQ_MBHC_POTENTIAL);
  5129. return bias_value;
  5130. }
  5131. static short tabla_codec_sta_dce(struct snd_soc_codec *codec, int dce,
  5132. bool norel)
  5133. {
  5134. return __tabla_codec_sta_dce(codec, dce, false, norel);
  5135. }
  5136. /* called only from interrupt which is under codec_resource_lock acquisition */
  5137. static short tabla_codec_setup_hs_polling(struct snd_soc_codec *codec)
  5138. {
  5139. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  5140. short bias_value;
  5141. u8 cfilt_mode = 0;
  5142. pr_debug("%s: enter, mclk_enabled %d\n", __func__, tabla->mclk_enabled);
  5143. if (!tabla->mbhc_cfg.calibration) {
  5144. pr_err("Error, no tabla calibration\n");
  5145. return -ENODEV;
  5146. }
  5147. if (!tabla->mclk_enabled) {
  5148. tabla_codec_disable_clock_block(codec);
  5149. tabla_codec_enable_bandgap(codec, TABLA_BANDGAP_MBHC_MODE);
  5150. tabla_enable_rx_bias(codec, 1);
  5151. tabla_codec_enable_clock_block(codec, 1);
  5152. }
  5153. snd_soc_update_bits(codec, TABLA_A_CLK_BUFF_EN1, 0x05, 0x01);
  5154. if (!tabla->mbhc_cfg.micbias_always_on) {
  5155. /* Make sure CFILT is in fast mode, save current mode */
  5156. cfilt_mode = snd_soc_read(codec,
  5157. tabla->mbhc_bias_regs.cfilt_ctl);
  5158. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.cfilt_ctl,
  5159. 0x70, 0x00);
  5160. }
  5161. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.ctl_reg, 0x1F, 0x16);
  5162. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x2, 0x2);
  5163. snd_soc_write(codec, TABLA_A_MBHC_SCALING_MUX_1, 0x84);
  5164. snd_soc_update_bits(codec, TABLA_A_TX_7_MBHC_EN, 0x80, 0x80);
  5165. snd_soc_update_bits(codec, TABLA_A_TX_7_MBHC_EN, 0x1F, 0x1C);
  5166. snd_soc_update_bits(codec, TABLA_A_TX_7_MBHC_TEST_CTL, 0x40, 0x40);
  5167. snd_soc_update_bits(codec, TABLA_A_TX_7_MBHC_EN, 0x80, 0x00);
  5168. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x8, 0x8);
  5169. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x8, 0x00);
  5170. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x2, 0x2);
  5171. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x8, 0x8);
  5172. tabla_codec_calibrate_hs_polling(codec);
  5173. /* don't flip override */
  5174. bias_value = __tabla_codec_sta_dce(codec, 1, true, true);
  5175. if (!tabla->mbhc_cfg.micbias_always_on)
  5176. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.cfilt_ctl,
  5177. 0x40, cfilt_mode);
  5178. snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x13, 0x00);
  5179. return bias_value;
  5180. }
  5181. static int tabla_cancel_btn_work(struct tabla_priv *tabla)
  5182. {
  5183. int r = 0;
  5184. struct wcd9xxx *core = dev_get_drvdata(tabla->codec->dev->parent);
  5185. struct wcd9xxx_core_resource *core_res = &core->core_res;
  5186. if (cancel_delayed_work_sync(&tabla->mbhc_btn_dwork)) {
  5187. /* if scheduled mbhc_btn_dwork is canceled from here,
  5188. * we have to unlock from here instead btn_work */
  5189. wcd9xxx_unlock_sleep(core_res);
  5190. r = 1;
  5191. }
  5192. return r;
  5193. }
  5194. /* called under codec_resource_lock acquisition */
  5195. void tabla_set_and_turnoff_hph_padac(struct snd_soc_codec *codec)
  5196. {
  5197. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  5198. u8 wg_time;
  5199. wg_time = snd_soc_read(codec, TABLA_A_RX_HPH_CNP_WG_TIME) ;
  5200. wg_time += 1;
  5201. /* If headphone PA is on, check if userspace receives
  5202. * removal event to sync-up PA's state */
  5203. if (tabla_is_hph_pa_on(codec)) {
  5204. pr_debug("%s PA is on, setting PA_OFF_ACK\n", __func__);
  5205. set_bit(TABLA_HPHL_PA_OFF_ACK, &tabla->hph_pa_dac_state);
  5206. set_bit(TABLA_HPHR_PA_OFF_ACK, &tabla->hph_pa_dac_state);
  5207. } else {
  5208. pr_debug("%s PA is off\n", __func__);
  5209. }
  5210. if (tabla_is_hph_dac_on(codec, 1))
  5211. set_bit(TABLA_HPHL_DAC_OFF_ACK, &tabla->hph_pa_dac_state);
  5212. if (tabla_is_hph_dac_on(codec, 0))
  5213. set_bit(TABLA_HPHR_DAC_OFF_ACK, &tabla->hph_pa_dac_state);
  5214. snd_soc_update_bits(codec, TABLA_A_RX_HPH_CNP_EN, 0x30, 0x00);
  5215. snd_soc_update_bits(codec, TABLA_A_RX_HPH_L_DAC_CTL,
  5216. 0x80, 0x00);
  5217. snd_soc_update_bits(codec, TABLA_A_RX_HPH_R_DAC_CTL,
  5218. 0xC0, 0x00);
  5219. usleep_range(wg_time * 1000, wg_time * 1000);
  5220. }
  5221. static void tabla_clr_and_turnon_hph_padac(struct tabla_priv *tabla)
  5222. {
  5223. bool pa_turned_on = false;
  5224. struct snd_soc_codec *codec = tabla->codec;
  5225. u8 wg_time;
  5226. wg_time = snd_soc_read(codec, TABLA_A_RX_HPH_CNP_WG_TIME) ;
  5227. wg_time += 1;
  5228. if (test_and_clear_bit(TABLA_HPHR_DAC_OFF_ACK,
  5229. &tabla->hph_pa_dac_state)) {
  5230. pr_debug("%s: HPHR clear flag and enable DAC\n", __func__);
  5231. snd_soc_update_bits(tabla->codec, TABLA_A_RX_HPH_R_DAC_CTL,
  5232. 0xC0, 0xC0);
  5233. }
  5234. if (test_and_clear_bit(TABLA_HPHL_DAC_OFF_ACK,
  5235. &tabla->hph_pa_dac_state)) {
  5236. pr_debug("%s: HPHL clear flag and enable DAC\n", __func__);
  5237. snd_soc_update_bits(tabla->codec, TABLA_A_RX_HPH_L_DAC_CTL,
  5238. 0xC0, 0xC0);
  5239. }
  5240. if (test_and_clear_bit(TABLA_HPHR_PA_OFF_ACK,
  5241. &tabla->hph_pa_dac_state)) {
  5242. pr_debug("%s: HPHR clear flag and enable PA\n", __func__);
  5243. snd_soc_update_bits(tabla->codec, TABLA_A_RX_HPH_CNP_EN, 0x10,
  5244. 1 << 4);
  5245. pa_turned_on = true;
  5246. }
  5247. if (test_and_clear_bit(TABLA_HPHL_PA_OFF_ACK,
  5248. &tabla->hph_pa_dac_state)) {
  5249. pr_debug("%s: HPHL clear flag and enable PA\n", __func__);
  5250. snd_soc_update_bits(tabla->codec, TABLA_A_RX_HPH_CNP_EN, 0x20,
  5251. 1 << 5);
  5252. pa_turned_on = true;
  5253. }
  5254. if (pa_turned_on) {
  5255. pr_debug("%s: PA was turned off by MBHC and not by DAPM\n",
  5256. __func__);
  5257. usleep_range(wg_time * 1000, wg_time * 1000);
  5258. }
  5259. }
  5260. /* called under codec_resource_lock acquisition */
  5261. static void tabla_codec_enable_mbhc_micbias(struct snd_soc_codec *codec,
  5262. bool enable)
  5263. {
  5264. int r;
  5265. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  5266. if (!tabla->mbhc_cfg.micbias_always_on)
  5267. return;
  5268. if (enable) {
  5269. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  5270. tabla_codec_update_cfilt_usage(codec,
  5271. tabla->mbhc_bias_regs.cfilt_sel, 1);
  5272. r = snd_soc_dapm_force_enable_pin(&codec->dapm,
  5273. "MIC BIAS2 Power External");
  5274. snd_soc_dapm_sync(&codec->dapm);
  5275. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  5276. pr_debug("%s: Turning on MICBIAS2 r %d\n", __func__, r);
  5277. } else {
  5278. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  5279. r = snd_soc_dapm_disable_pin(&codec->dapm,
  5280. "MIC BIAS2 Power External");
  5281. snd_soc_dapm_sync(&codec->dapm);
  5282. tabla_codec_update_cfilt_usage(codec,
  5283. tabla->mbhc_bias_regs.cfilt_sel, 0);
  5284. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  5285. pr_debug("%s: Turning off MICBIAS2 r %d\n", __func__, r);
  5286. }
  5287. }
  5288. /* called under codec_resource_lock acquisition */
  5289. static void tabla_codec_report_plug(struct snd_soc_codec *codec, int insertion,
  5290. enum snd_jack_types jack_type)
  5291. {
  5292. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  5293. pr_debug("%s: enter insertion %d hph_status %x\n",
  5294. __func__, insertion, tabla->hph_status);
  5295. if (!insertion) {
  5296. /* Report removal */
  5297. tabla->hph_status &= ~jack_type;
  5298. if (tabla->mbhc_cfg.headset_jack) {
  5299. /* cancel possibly scheduled btn work and
  5300. * report release if we reported button press */
  5301. if (tabla_cancel_btn_work(tabla)) {
  5302. pr_debug("%s: button press is canceled\n",
  5303. __func__);
  5304. } else if (tabla->buttons_pressed) {
  5305. pr_debug("%s: Reporting release for reported "
  5306. "button press %d\n", __func__,
  5307. jack_type);
  5308. tabla_snd_soc_jack_report(tabla,
  5309. tabla->mbhc_cfg.button_jack, 0,
  5310. tabla->buttons_pressed);
  5311. tabla->buttons_pressed &=
  5312. ~TABLA_JACK_BUTTON_MASK;
  5313. }
  5314. if (jack_type == SND_JACK_HEADSET)
  5315. tabla_codec_enable_mbhc_micbias(codec, false);
  5316. pr_debug("%s: Reporting removal %d(%x)\n", __func__,
  5317. jack_type, tabla->hph_status);
  5318. tabla_snd_soc_jack_report(tabla,
  5319. tabla->mbhc_cfg.headset_jack,
  5320. tabla->hph_status,
  5321. TABLA_JACK_MASK);
  5322. }
  5323. tabla_set_and_turnoff_hph_padac(codec);
  5324. hphocp_off_report(tabla, SND_JACK_OC_HPHR,
  5325. WCD9XXX_IRQ_HPH_PA_OCPR_FAULT);
  5326. hphocp_off_report(tabla, SND_JACK_OC_HPHL,
  5327. WCD9XXX_IRQ_HPH_PA_OCPL_FAULT);
  5328. tabla->current_plug = PLUG_TYPE_NONE;
  5329. tabla->mbhc_polling_active = false;
  5330. } else {
  5331. if (tabla->mbhc_cfg.detect_extn_cable) {
  5332. /* Report removal of current jack type */
  5333. if (tabla->hph_status != jack_type &&
  5334. tabla->mbhc_cfg.headset_jack) {
  5335. pr_debug("%s: Reporting removal (%x)\n",
  5336. __func__, tabla->hph_status);
  5337. tabla_snd_soc_jack_report(tabla,
  5338. tabla->mbhc_cfg.headset_jack,
  5339. 0, TABLA_JACK_MASK);
  5340. tabla->hph_status = 0;
  5341. }
  5342. }
  5343. /* Report insertion */
  5344. tabla->hph_status |= jack_type;
  5345. if (jack_type == SND_JACK_HEADPHONE)
  5346. tabla->current_plug = PLUG_TYPE_HEADPHONE;
  5347. else if (jack_type == SND_JACK_UNSUPPORTED)
  5348. tabla->current_plug = PLUG_TYPE_GND_MIC_SWAP;
  5349. else if (jack_type == SND_JACK_HEADSET) {
  5350. tabla->mbhc_polling_active = true;
  5351. tabla->current_plug = PLUG_TYPE_HEADSET;
  5352. tabla_codec_enable_mbhc_micbias(codec, true);
  5353. } else if (jack_type == SND_JACK_LINEOUT)
  5354. tabla->current_plug = PLUG_TYPE_HIGH_HPH;
  5355. if (tabla->mbhc_cfg.headset_jack) {
  5356. pr_debug("%s: Reporting insertion %d(%x)\n", __func__,
  5357. jack_type, tabla->hph_status);
  5358. tabla_snd_soc_jack_report(tabla,
  5359. tabla->mbhc_cfg.headset_jack,
  5360. tabla->hph_status,
  5361. TABLA_JACK_MASK);
  5362. }
  5363. tabla_clr_and_turnon_hph_padac(tabla);
  5364. }
  5365. pr_debug("%s: leave hph_status %x\n", __func__, tabla->hph_status);
  5366. }
  5367. static int tabla_codec_enable_hs_detect(struct snd_soc_codec *codec,
  5368. int insertion, int trigger,
  5369. bool padac_off)
  5370. {
  5371. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  5372. int central_bias_enabled = 0;
  5373. const struct tabla_mbhc_general_cfg *generic =
  5374. TABLA_MBHC_CAL_GENERAL_PTR(tabla->mbhc_cfg.calibration);
  5375. const struct tabla_mbhc_plug_detect_cfg *plug_det =
  5376. TABLA_MBHC_CAL_PLUG_DET_PTR(tabla->mbhc_cfg.calibration);
  5377. pr_debug("%s: enter insertion(%d) trigger(0x%x)\n",
  5378. __func__, insertion, trigger);
  5379. if (!tabla->mbhc_cfg.calibration) {
  5380. pr_err("Error, no tabla calibration\n");
  5381. return -EINVAL;
  5382. }
  5383. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_INT_CTL, 0x1, 0);
  5384. /* Make sure mic bias and Mic line schmitt trigger
  5385. * are turned OFF
  5386. */
  5387. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.ctl_reg, 0x01, 0x01);
  5388. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg, 0x90, 0x00);
  5389. if (insertion) {
  5390. pr_debug("%s: setup for insertion\n", __func__);
  5391. tabla_codec_switch_micbias(codec, 0);
  5392. /* DAPM can manipulate PA/DAC bits concurrently */
  5393. if (padac_off == true) {
  5394. tabla_set_and_turnoff_hph_padac(codec);
  5395. }
  5396. if (trigger & MBHC_USE_HPHL_TRIGGER) {
  5397. /* Enable HPH Schmitt Trigger */
  5398. snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x11,
  5399. 0x11);
  5400. snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x0C,
  5401. plug_det->hph_current << 2);
  5402. snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x02,
  5403. 0x02);
  5404. }
  5405. if (trigger & MBHC_USE_MB_TRIGGER) {
  5406. /* enable the mic line schmitt trigger */
  5407. snd_soc_update_bits(codec,
  5408. tabla->mbhc_bias_regs.mbhc_reg,
  5409. 0x60, plug_det->mic_current << 5);
  5410. snd_soc_update_bits(codec,
  5411. tabla->mbhc_bias_regs.mbhc_reg,
  5412. 0x80, 0x80);
  5413. usleep_range(plug_det->t_mic_pid, plug_det->t_mic_pid);
  5414. snd_soc_update_bits(codec,
  5415. tabla->mbhc_bias_regs.ctl_reg, 0x01,
  5416. 0x00);
  5417. snd_soc_update_bits(codec,
  5418. tabla->mbhc_bias_regs.mbhc_reg,
  5419. 0x10, 0x10);
  5420. }
  5421. /* setup for insetion detection */
  5422. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_INT_CTL, 0x2, 0);
  5423. } else {
  5424. pr_debug("setup for removal detection\n");
  5425. /* Make sure the HPH schmitt trigger is OFF */
  5426. snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x12, 0x00);
  5427. /* enable the mic line schmitt trigger */
  5428. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.ctl_reg,
  5429. 0x01, 0x00);
  5430. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg, 0x60,
  5431. plug_det->mic_current << 5);
  5432. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg,
  5433. 0x80, 0x80);
  5434. usleep_range(plug_det->t_mic_pid, plug_det->t_mic_pid);
  5435. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg,
  5436. 0x10, 0x10);
  5437. /* Setup for low power removal detection */
  5438. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_INT_CTL, 0x2, 0x2);
  5439. }
  5440. if (snd_soc_read(codec, TABLA_A_CDC_MBHC_B1_CTL) & 0x4) {
  5441. /* called called by interrupt */
  5442. if (!(tabla->clock_active)) {
  5443. tabla_codec_enable_config_mode(codec, 1);
  5444. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL,
  5445. 0x06, 0);
  5446. usleep_range(generic->t_shutdown_plug_rem,
  5447. generic->t_shutdown_plug_rem);
  5448. tabla_codec_enable_config_mode(codec, 0);
  5449. } else
  5450. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL,
  5451. 0x06, 0);
  5452. }
  5453. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.int_rbias, 0x80, 0);
  5454. /* If central bandgap disabled */
  5455. if (!(snd_soc_read(codec, TABLA_A_PIN_CTL_OE1) & 1)) {
  5456. snd_soc_update_bits(codec, TABLA_A_PIN_CTL_OE1, 0x3, 0x3);
  5457. usleep_range(generic->t_bg_fast_settle,
  5458. generic->t_bg_fast_settle);
  5459. central_bias_enabled = 1;
  5460. }
  5461. /* If LDO_H disabled */
  5462. if (snd_soc_read(codec, TABLA_A_PIN_CTL_OE0) & 0x80) {
  5463. snd_soc_update_bits(codec, TABLA_A_PIN_CTL_OE0, 0x10, 0);
  5464. snd_soc_update_bits(codec, TABLA_A_PIN_CTL_OE0, 0x80, 0x80);
  5465. usleep_range(generic->t_ldoh, generic->t_ldoh);
  5466. snd_soc_update_bits(codec, TABLA_A_PIN_CTL_OE0, 0x80, 0);
  5467. if (central_bias_enabled)
  5468. snd_soc_update_bits(codec, TABLA_A_PIN_CTL_OE1, 0x1, 0);
  5469. }
  5470. snd_soc_update_bits(codec, tabla->reg_addr.micb_4_mbhc, 0x3,
  5471. tabla->mbhc_cfg.micbias);
  5472. wcd9xxx_enable_irq(codec->control_data, WCD9XXX_IRQ_MBHC_INSERTION);
  5473. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_INT_CTL, 0x1, 0x1);
  5474. pr_debug("%s: leave\n", __func__);
  5475. return 0;
  5476. }
  5477. static u16 tabla_codec_v_sta_dce(struct snd_soc_codec *codec, bool dce,
  5478. s16 vin_mv)
  5479. {
  5480. struct tabla_priv *tabla;
  5481. s16 diff, zero;
  5482. u32 mb_mv, in;
  5483. u16 value;
  5484. tabla = snd_soc_codec_get_drvdata(codec);
  5485. mb_mv = tabla->mbhc_data.micb_mv;
  5486. if (mb_mv == 0) {
  5487. pr_err("%s: Mic Bias voltage is set to zero\n", __func__);
  5488. return -EINVAL;
  5489. }
  5490. if (dce) {
  5491. diff = (tabla->mbhc_data.dce_mb) - (tabla->mbhc_data.dce_z);
  5492. zero = (tabla->mbhc_data.dce_z);
  5493. } else {
  5494. diff = (tabla->mbhc_data.sta_mb) - (tabla->mbhc_data.sta_z);
  5495. zero = (tabla->mbhc_data.sta_z);
  5496. }
  5497. in = (u32) diff * vin_mv;
  5498. value = (u16) (in / mb_mv) + zero;
  5499. return value;
  5500. }
  5501. static s32 tabla_codec_sta_dce_v(struct snd_soc_codec *codec, s8 dce,
  5502. u16 bias_value)
  5503. {
  5504. struct tabla_priv *tabla;
  5505. s16 value, z, mb;
  5506. s32 mv;
  5507. tabla = snd_soc_codec_get_drvdata(codec);
  5508. value = bias_value;
  5509. if (dce) {
  5510. z = (tabla->mbhc_data.dce_z);
  5511. mb = (tabla->mbhc_data.dce_mb);
  5512. mv = (value - z) * (s32)tabla->mbhc_data.micb_mv / (mb - z);
  5513. } else {
  5514. z = (tabla->mbhc_data.sta_z);
  5515. mb = (tabla->mbhc_data.sta_mb);
  5516. mv = (value - z) * (s32)tabla->mbhc_data.micb_mv / (mb - z);
  5517. }
  5518. return mv;
  5519. }
  5520. static void btn_lpress_fn(struct work_struct *work)
  5521. {
  5522. struct delayed_work *delayed_work;
  5523. struct tabla_priv *tabla;
  5524. short bias_value;
  5525. int dce_mv, sta_mv;
  5526. struct wcd9xxx *core;
  5527. struct wcd9xxx_core_resource *core_res;
  5528. pr_debug("%s:\n", __func__);
  5529. delayed_work = to_delayed_work(work);
  5530. tabla = container_of(delayed_work, struct tabla_priv, mbhc_btn_dwork);
  5531. core = dev_get_drvdata(tabla->codec->dev->parent);
  5532. core_res = &core->core_res;
  5533. if (tabla) {
  5534. if (tabla->mbhc_cfg.button_jack) {
  5535. bias_value = tabla_codec_read_sta_result(tabla->codec);
  5536. sta_mv = tabla_codec_sta_dce_v(tabla->codec, 0,
  5537. bias_value);
  5538. bias_value = tabla_codec_read_dce_result(tabla->codec);
  5539. dce_mv = tabla_codec_sta_dce_v(tabla->codec, 1,
  5540. bias_value);
  5541. pr_debug("%s: Reporting long button press event"
  5542. " STA: %d, DCE: %d\n", __func__,
  5543. sta_mv, dce_mv);
  5544. tabla_snd_soc_jack_report(tabla,
  5545. tabla->mbhc_cfg.button_jack,
  5546. tabla->buttons_pressed,
  5547. tabla->buttons_pressed);
  5548. }
  5549. } else {
  5550. pr_err("%s: Bad tabla private data\n", __func__);
  5551. }
  5552. pr_debug("%s: leave\n", __func__);
  5553. wcd9xxx_unlock_sleep(core_res);
  5554. }
  5555. static u16 tabla_get_cfilt_reg(struct snd_soc_codec *codec, u8 cfilt)
  5556. {
  5557. u16 reg;
  5558. switch (cfilt) {
  5559. case TABLA_CFILT1_SEL:
  5560. reg = TABLA_A_MICB_CFILT_1_CTL;
  5561. break;
  5562. case TABLA_CFILT2_SEL:
  5563. reg = TABLA_A_MICB_CFILT_2_CTL;
  5564. break;
  5565. case TABLA_CFILT3_SEL:
  5566. reg = TABLA_A_MICB_CFILT_3_CTL;
  5567. break;
  5568. default:
  5569. BUG();
  5570. }
  5571. return reg;
  5572. }
  5573. void tabla_mbhc_cal(struct snd_soc_codec *codec)
  5574. {
  5575. struct tabla_priv *tabla;
  5576. struct tabla_mbhc_btn_detect_cfg *btn_det;
  5577. u8 cfilt_mode, micbias2_cfilt_mode, bg_mode;
  5578. u8 ncic, nmeas, navg;
  5579. u32 mclk_rate;
  5580. u32 dce_wait, sta_wait;
  5581. u8 *n_cic;
  5582. void *calibration;
  5583. u16 bias2_ctl;
  5584. tabla = snd_soc_codec_get_drvdata(codec);
  5585. calibration = tabla->mbhc_cfg.calibration;
  5586. wcd9xxx_disable_irq(codec->control_data, WCD9XXX_IRQ_MBHC_POTENTIAL);
  5587. tabla_turn_onoff_rel_detection(codec, false);
  5588. /* First compute the DCE / STA wait times
  5589. * depending on tunable parameters.
  5590. * The value is computed in microseconds
  5591. */
  5592. btn_det = TABLA_MBHC_CAL_BTN_DET_PTR(calibration);
  5593. n_cic = tabla_mbhc_cal_btn_det_mp(btn_det, TABLA_BTN_DET_N_CIC);
  5594. ncic = n_cic[tabla_codec_mclk_index(tabla)];
  5595. nmeas = TABLA_MBHC_CAL_BTN_DET_PTR(calibration)->n_meas;
  5596. navg = TABLA_MBHC_CAL_GENERAL_PTR(calibration)->mbhc_navg;
  5597. mclk_rate = tabla->mbhc_cfg.mclk_rate;
  5598. dce_wait = (1000 * 512 * ncic * (nmeas + 1)) / (mclk_rate / 1000);
  5599. sta_wait = (1000 * 128 * (navg + 1)) / (mclk_rate / 1000);
  5600. tabla->mbhc_data.t_dce = dce_wait;
  5601. tabla->mbhc_data.t_sta = sta_wait;
  5602. /* LDOH and CFILT are already configured during pdata handling.
  5603. * Only need to make sure CFILT and bandgap are in Fast mode.
  5604. * Need to restore defaults once calculation is done.
  5605. */
  5606. cfilt_mode = snd_soc_read(codec, tabla->mbhc_bias_regs.cfilt_ctl);
  5607. micbias2_cfilt_mode =
  5608. snd_soc_read(codec, tabla_get_cfilt_reg(codec,
  5609. tabla->pdata->micbias.bias2_cfilt_sel));
  5610. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.cfilt_ctl, 0x40,
  5611. TABLA_CFILT_FAST_MODE);
  5612. snd_soc_update_bits(codec,
  5613. tabla_get_cfilt_reg(codec,
  5614. tabla->pdata->micbias.bias2_cfilt_sel),
  5615. 0x40, TABLA_CFILT_FAST_MODE);
  5616. bg_mode = snd_soc_update_bits(codec, TABLA_A_BIAS_CENTRAL_BG_CTL, 0x02,
  5617. 0x02);
  5618. /* Micbias, CFILT, LDOH, MBHC MUX mode settings
  5619. * to perform ADC calibration
  5620. */
  5621. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.ctl_reg, 0x60,
  5622. tabla->mbhc_cfg.micbias << 5);
  5623. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.ctl_reg, 0x01, 0x00);
  5624. snd_soc_update_bits(codec, TABLA_A_LDO_H_MODE_1, 0x60, 0x60);
  5625. snd_soc_write(codec, TABLA_A_TX_7_MBHC_TEST_CTL, 0x78);
  5626. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x04, 0x04);
  5627. /* MICBIAS2 routing for calibration */
  5628. bias2_ctl = snd_soc_read(codec, TABLA_A_MICB_2_CTL);
  5629. snd_soc_update_bits(codec, TABLA_A_MICB_1_MBHC, 0x03, TABLA_MICBIAS2);
  5630. snd_soc_write(codec, TABLA_A_MICB_2_CTL,
  5631. snd_soc_read(codec, tabla->mbhc_bias_regs.ctl_reg));
  5632. /* DCE measurement for 0 volts */
  5633. snd_soc_write(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x0A);
  5634. snd_soc_write(codec, TABLA_A_CDC_MBHC_EN_CTL, 0x04);
  5635. snd_soc_write(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x02);
  5636. snd_soc_write(codec, TABLA_A_MBHC_SCALING_MUX_1, 0x81);
  5637. usleep_range(100, 100);
  5638. snd_soc_write(codec, TABLA_A_CDC_MBHC_EN_CTL, 0x04);
  5639. usleep_range(tabla->mbhc_data.t_dce, tabla->mbhc_data.t_dce);
  5640. tabla->mbhc_data.dce_z = tabla_codec_read_dce_result(codec);
  5641. /* DCE measurment for MB voltage */
  5642. snd_soc_write(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x0A);
  5643. snd_soc_write(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x02);
  5644. snd_soc_write(codec, TABLA_A_MBHC_SCALING_MUX_1, 0x82);
  5645. usleep_range(100, 100);
  5646. snd_soc_write(codec, TABLA_A_CDC_MBHC_EN_CTL, 0x04);
  5647. usleep_range(tabla->mbhc_data.t_dce, tabla->mbhc_data.t_dce);
  5648. tabla->mbhc_data.dce_mb = tabla_codec_read_dce_result(codec);
  5649. /* Sta measuremnt for 0 volts */
  5650. snd_soc_write(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x0A);
  5651. snd_soc_write(codec, TABLA_A_CDC_MBHC_EN_CTL, 0x02);
  5652. snd_soc_write(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x02);
  5653. snd_soc_write(codec, TABLA_A_MBHC_SCALING_MUX_1, 0x81);
  5654. usleep_range(100, 100);
  5655. snd_soc_write(codec, TABLA_A_CDC_MBHC_EN_CTL, 0x02);
  5656. usleep_range(tabla->mbhc_data.t_sta, tabla->mbhc_data.t_sta);
  5657. tabla->mbhc_data.sta_z = tabla_codec_read_sta_result(codec);
  5658. /* STA Measurement for MB Voltage */
  5659. snd_soc_write(codec, TABLA_A_MBHC_SCALING_MUX_1, 0x82);
  5660. usleep_range(100, 100);
  5661. snd_soc_write(codec, TABLA_A_CDC_MBHC_EN_CTL, 0x02);
  5662. usleep_range(tabla->mbhc_data.t_sta, tabla->mbhc_data.t_sta);
  5663. tabla->mbhc_data.sta_mb = tabla_codec_read_sta_result(codec);
  5664. /* Restore default settings. */
  5665. snd_soc_write(codec, TABLA_A_MICB_2_CTL, bias2_ctl);
  5666. snd_soc_update_bits(codec, TABLA_A_MICB_1_MBHC, 0x03,
  5667. tabla->mbhc_cfg.micbias);
  5668. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x04, 0x00);
  5669. snd_soc_update_bits(codec,
  5670. tabla_get_cfilt_reg(codec,
  5671. tabla->pdata->micbias.bias2_cfilt_sel), 0x40,
  5672. micbias2_cfilt_mode);
  5673. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.cfilt_ctl, 0x40,
  5674. cfilt_mode);
  5675. snd_soc_update_bits(codec, TABLA_A_BIAS_CENTRAL_BG_CTL, 0x02, bg_mode);
  5676. snd_soc_write(codec, TABLA_A_MBHC_SCALING_MUX_1, 0x84);
  5677. usleep_range(100, 100);
  5678. wcd9xxx_enable_irq(codec->control_data, WCD9XXX_IRQ_MBHC_POTENTIAL);
  5679. tabla_turn_onoff_rel_detection(codec, true);
  5680. }
  5681. void *tabla_mbhc_cal_btn_det_mp(const struct tabla_mbhc_btn_detect_cfg* btn_det,
  5682. const enum tabla_mbhc_btn_det_mem mem)
  5683. {
  5684. void *ret = &btn_det->_v_btn_low;
  5685. switch (mem) {
  5686. case TABLA_BTN_DET_GAIN:
  5687. ret += sizeof(btn_det->_n_cic);
  5688. case TABLA_BTN_DET_N_CIC:
  5689. ret += sizeof(btn_det->_n_ready);
  5690. case TABLA_BTN_DET_N_READY:
  5691. ret += sizeof(btn_det->_v_btn_high[0]) * btn_det->num_btn;
  5692. case TABLA_BTN_DET_V_BTN_HIGH:
  5693. ret += sizeof(btn_det->_v_btn_low[0]) * btn_det->num_btn;
  5694. case TABLA_BTN_DET_V_BTN_LOW:
  5695. /* do nothing */
  5696. break;
  5697. default:
  5698. ret = NULL;
  5699. }
  5700. return ret;
  5701. }
  5702. static s16 tabla_scale_v_micb_vddio(struct tabla_priv *tabla, int v,
  5703. bool tovddio)
  5704. {
  5705. int r;
  5706. int vddio_k, mb_k;
  5707. vddio_k = tabla_find_k_value(tabla->pdata->micbias.ldoh_v,
  5708. VDDIO_MICBIAS_MV);
  5709. mb_k = tabla_find_k_value(tabla->pdata->micbias.ldoh_v,
  5710. tabla->mbhc_data.micb_mv);
  5711. if (tovddio)
  5712. r = v * vddio_k / mb_k;
  5713. else
  5714. r = v * mb_k / vddio_k;
  5715. return r;
  5716. }
  5717. static void tabla_mbhc_calc_rel_thres(struct snd_soc_codec *codec, s16 mv)
  5718. {
  5719. s16 deltamv;
  5720. struct tabla_priv *tabla;
  5721. struct tabla_mbhc_btn_detect_cfg *btn_det;
  5722. tabla = snd_soc_codec_get_drvdata(codec);
  5723. btn_det = TABLA_MBHC_CAL_BTN_DET_PTR(tabla->mbhc_cfg.calibration);
  5724. tabla->mbhc_data.v_b1_h =
  5725. tabla_codec_v_sta_dce(codec, DCE,
  5726. mv + btn_det->v_btn_press_delta_cic);
  5727. tabla->mbhc_data.v_brh = tabla->mbhc_data.v_b1_h;
  5728. tabla->mbhc_data.v_brl = TABLA_MBHC_BUTTON_MIN;
  5729. deltamv = mv + btn_det->v_btn_press_delta_sta;
  5730. tabla->mbhc_data.v_b1_hu = tabla_codec_v_sta_dce(codec, STA, deltamv);
  5731. deltamv = mv + btn_det->v_btn_press_delta_cic;
  5732. tabla->mbhc_data.v_b1_huc = tabla_codec_v_sta_dce(codec, DCE, deltamv);
  5733. }
  5734. static void tabla_mbhc_set_rel_thres(struct snd_soc_codec *codec, s16 mv)
  5735. {
  5736. tabla_mbhc_calc_rel_thres(codec, mv);
  5737. tabla_codec_calibrate_rel(codec);
  5738. }
  5739. static s16 tabla_mbhc_highest_btn_mv(struct snd_soc_codec *codec)
  5740. {
  5741. struct tabla_priv *tabla;
  5742. struct tabla_mbhc_btn_detect_cfg *btn_det;
  5743. u16 *btn_high;
  5744. tabla = snd_soc_codec_get_drvdata(codec);
  5745. btn_det = TABLA_MBHC_CAL_BTN_DET_PTR(tabla->mbhc_cfg.calibration);
  5746. btn_high = tabla_mbhc_cal_btn_det_mp(btn_det, TABLA_BTN_DET_V_BTN_HIGH);
  5747. return btn_high[btn_det->num_btn - 1];
  5748. }
  5749. static void tabla_mbhc_calc_thres(struct snd_soc_codec *codec)
  5750. {
  5751. struct tabla_priv *tabla;
  5752. struct tabla_mbhc_btn_detect_cfg *btn_det;
  5753. struct tabla_mbhc_plug_type_cfg *plug_type;
  5754. u8 *n_ready;
  5755. tabla = snd_soc_codec_get_drvdata(codec);
  5756. btn_det = TABLA_MBHC_CAL_BTN_DET_PTR(tabla->mbhc_cfg.calibration);
  5757. plug_type = TABLA_MBHC_CAL_PLUG_TYPE_PTR(tabla->mbhc_cfg.calibration);
  5758. n_ready = tabla_mbhc_cal_btn_det_mp(btn_det, TABLA_BTN_DET_N_READY);
  5759. if (tabla->mbhc_cfg.mclk_rate == TABLA_MCLK_RATE_12288KHZ) {
  5760. tabla->mbhc_data.npoll = 4;
  5761. tabla->mbhc_data.nbounce_wait = 30;
  5762. } else if (tabla->mbhc_cfg.mclk_rate == TABLA_MCLK_RATE_9600KHZ) {
  5763. tabla->mbhc_data.npoll = 7;
  5764. tabla->mbhc_data.nbounce_wait = 23;
  5765. }
  5766. tabla->mbhc_data.t_sta_dce = ((1000 * 256) /
  5767. (tabla->mbhc_cfg.mclk_rate / 1000) *
  5768. n_ready[tabla_codec_mclk_index(tabla)]) +
  5769. 10;
  5770. tabla->mbhc_data.v_ins_hu =
  5771. tabla_codec_v_sta_dce(codec, STA, plug_type->v_hs_max);
  5772. tabla->mbhc_data.v_ins_h =
  5773. tabla_codec_v_sta_dce(codec, DCE, plug_type->v_hs_max);
  5774. tabla->mbhc_data.v_inval_ins_low = TABLA_MBHC_FAKE_INSERT_LOW;
  5775. if (tabla->mbhc_cfg.gpio)
  5776. tabla->mbhc_data.v_inval_ins_high =
  5777. TABLA_MBHC_FAKE_INSERT_HIGH;
  5778. else
  5779. tabla->mbhc_data.v_inval_ins_high =
  5780. TABLA_MBHC_FAKE_INS_HIGH_NO_GPIO;
  5781. if (tabla->mbhc_data.micb_mv != VDDIO_MICBIAS_MV) {
  5782. tabla->mbhc_data.adj_v_hs_max =
  5783. tabla_scale_v_micb_vddio(tabla, plug_type->v_hs_max, true);
  5784. tabla->mbhc_data.adj_v_ins_hu =
  5785. tabla_codec_v_sta_dce(codec, STA,
  5786. tabla->mbhc_data.adj_v_hs_max);
  5787. tabla->mbhc_data.adj_v_ins_h =
  5788. tabla_codec_v_sta_dce(codec, DCE,
  5789. tabla->mbhc_data.adj_v_hs_max);
  5790. tabla->mbhc_data.v_inval_ins_low =
  5791. tabla_scale_v_micb_vddio(tabla,
  5792. tabla->mbhc_data.v_inval_ins_low,
  5793. false);
  5794. tabla->mbhc_data.v_inval_ins_high =
  5795. tabla_scale_v_micb_vddio(tabla,
  5796. tabla->mbhc_data.v_inval_ins_high,
  5797. false);
  5798. }
  5799. tabla_mbhc_calc_rel_thres(codec, tabla_mbhc_highest_btn_mv(codec));
  5800. tabla->mbhc_data.v_no_mic =
  5801. tabla_codec_v_sta_dce(codec, STA, plug_type->v_no_mic);
  5802. }
  5803. void tabla_mbhc_init(struct snd_soc_codec *codec)
  5804. {
  5805. struct tabla_priv *tabla;
  5806. struct tabla_mbhc_general_cfg *generic;
  5807. struct tabla_mbhc_btn_detect_cfg *btn_det;
  5808. int n;
  5809. u8 *n_cic, *gain;
  5810. struct wcd9xxx *tabla_core = dev_get_drvdata(codec->dev->parent);
  5811. tabla = snd_soc_codec_get_drvdata(codec);
  5812. generic = TABLA_MBHC_CAL_GENERAL_PTR(tabla->mbhc_cfg.calibration);
  5813. btn_det = TABLA_MBHC_CAL_BTN_DET_PTR(tabla->mbhc_cfg.calibration);
  5814. for (n = 0; n < 8; n++) {
  5815. if ((!TABLA_IS_1_X(tabla_core->version)) || n != 7) {
  5816. snd_soc_update_bits(codec,
  5817. TABLA_A_CDC_MBHC_FEATURE_B1_CFG,
  5818. 0x07, n);
  5819. snd_soc_write(codec, TABLA_A_CDC_MBHC_FEATURE_B2_CFG,
  5820. btn_det->c[n]);
  5821. }
  5822. }
  5823. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B2_CTL, 0x07,
  5824. btn_det->nc);
  5825. n_cic = tabla_mbhc_cal_btn_det_mp(btn_det, TABLA_BTN_DET_N_CIC);
  5826. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_TIMER_B6_CTL, 0xFF,
  5827. n_cic[tabla_codec_mclk_index(tabla)]);
  5828. gain = tabla_mbhc_cal_btn_det_mp(btn_det, TABLA_BTN_DET_GAIN);
  5829. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B2_CTL, 0x78,
  5830. gain[tabla_codec_mclk_index(tabla)] << 3);
  5831. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_TIMER_B4_CTL, 0x70,
  5832. generic->mbhc_nsa << 4);
  5833. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_TIMER_B4_CTL, 0x0F,
  5834. btn_det->n_meas);
  5835. snd_soc_write(codec, TABLA_A_CDC_MBHC_TIMER_B5_CTL, generic->mbhc_navg);
  5836. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x80, 0x80);
  5837. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x78,
  5838. btn_det->mbhc_nsc << 3);
  5839. snd_soc_update_bits(codec, tabla->reg_addr.micb_4_mbhc, 0x03,
  5840. TABLA_MICBIAS2);
  5841. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x02, 0x02);
  5842. snd_soc_update_bits(codec, TABLA_A_MBHC_SCALING_MUX_2, 0xF0, 0xF0);
  5843. /* override mbhc's micbias */
  5844. snd_soc_update_bits(codec, TABLA_A_MICB_1_MBHC, 0x03,
  5845. tabla->mbhc_cfg.micbias);
  5846. }
  5847. static bool tabla_mbhc_fw_validate(const struct firmware *fw)
  5848. {
  5849. u32 cfg_offset;
  5850. struct tabla_mbhc_imped_detect_cfg *imped_cfg;
  5851. struct tabla_mbhc_btn_detect_cfg *btn_cfg;
  5852. if (fw->size < TABLA_MBHC_CAL_MIN_SIZE)
  5853. return false;
  5854. /* previous check guarantees that there is enough fw data up
  5855. * to num_btn
  5856. */
  5857. btn_cfg = TABLA_MBHC_CAL_BTN_DET_PTR(fw->data);
  5858. cfg_offset = (u32) ((void *) btn_cfg - (void *) fw->data);
  5859. if (fw->size < (cfg_offset + TABLA_MBHC_CAL_BTN_SZ(btn_cfg)))
  5860. return false;
  5861. /* previous check guarantees that there is enough fw data up
  5862. * to start of impedance detection configuration
  5863. */
  5864. imped_cfg = TABLA_MBHC_CAL_IMPED_DET_PTR(fw->data);
  5865. cfg_offset = (u32) ((void *) imped_cfg - (void *) fw->data);
  5866. if (fw->size < (cfg_offset + TABLA_MBHC_CAL_IMPED_MIN_SZ))
  5867. return false;
  5868. if (fw->size < (cfg_offset + TABLA_MBHC_CAL_IMPED_SZ(imped_cfg)))
  5869. return false;
  5870. return true;
  5871. }
  5872. /* called under codec_resource_lock acquisition */
  5873. static int tabla_determine_button(const struct tabla_priv *priv,
  5874. const s32 micmv)
  5875. {
  5876. s16 *v_btn_low, *v_btn_high;
  5877. struct tabla_mbhc_btn_detect_cfg *btn_det;
  5878. int i, btn = -1;
  5879. btn_det = TABLA_MBHC_CAL_BTN_DET_PTR(priv->mbhc_cfg.calibration);
  5880. v_btn_low = tabla_mbhc_cal_btn_det_mp(btn_det, TABLA_BTN_DET_V_BTN_LOW);
  5881. v_btn_high = tabla_mbhc_cal_btn_det_mp(btn_det,
  5882. TABLA_BTN_DET_V_BTN_HIGH);
  5883. for (i = 0; i < btn_det->num_btn; i++) {
  5884. if ((v_btn_low[i] <= micmv) && (v_btn_high[i] >= micmv)) {
  5885. btn = i;
  5886. break;
  5887. }
  5888. }
  5889. if (btn == -1)
  5890. pr_debug("%s: couldn't find button number for mic mv %d\n",
  5891. __func__, micmv);
  5892. return btn;
  5893. }
  5894. static int tabla_get_button_mask(const int btn)
  5895. {
  5896. int mask = 0;
  5897. switch (btn) {
  5898. case 0:
  5899. mask = SND_JACK_BTN_0;
  5900. break;
  5901. case 1:
  5902. mask = SND_JACK_BTN_1;
  5903. break;
  5904. case 2:
  5905. mask = SND_JACK_BTN_2;
  5906. break;
  5907. case 3:
  5908. mask = SND_JACK_BTN_3;
  5909. break;
  5910. case 4:
  5911. mask = SND_JACK_BTN_4;
  5912. break;
  5913. case 5:
  5914. mask = SND_JACK_BTN_5;
  5915. break;
  5916. case 6:
  5917. mask = SND_JACK_BTN_6;
  5918. break;
  5919. case 7:
  5920. mask = SND_JACK_BTN_7;
  5921. break;
  5922. }
  5923. return mask;
  5924. }
  5925. static irqreturn_t tabla_dce_handler(int irq, void *data)
  5926. {
  5927. int i, mask;
  5928. short dce, sta;
  5929. s32 mv, mv_s, stamv, stamv_s;
  5930. bool vddio;
  5931. u16 *btn_high;
  5932. int btn = -1, meas = 0;
  5933. struct tabla_priv *priv = data;
  5934. const struct tabla_mbhc_btn_detect_cfg *d =
  5935. TABLA_MBHC_CAL_BTN_DET_PTR(priv->mbhc_cfg.calibration);
  5936. short btnmeas[d->n_btn_meas + 1];
  5937. struct snd_soc_codec *codec = priv->codec;
  5938. struct wcd9xxx *core = dev_get_drvdata(priv->codec->dev->parent);
  5939. struct wcd9xxx_core_resource *core_res = &core->core_res;
  5940. int n_btn_meas = d->n_btn_meas;
  5941. u8 mbhc_status = snd_soc_read(codec, TABLA_A_CDC_MBHC_B1_STATUS) & 0x3E;
  5942. pr_debug("%s: enter\n", __func__);
  5943. btn_high = tabla_mbhc_cal_btn_det_mp(d, TABLA_BTN_DET_V_BTN_HIGH);
  5944. TABLA_ACQUIRE_LOCK(priv->codec_resource_lock);
  5945. if (priv->mbhc_state == MBHC_STATE_POTENTIAL_RECOVERY) {
  5946. pr_debug("%s: mbhc is being recovered, skip button press\n",
  5947. __func__);
  5948. goto done;
  5949. }
  5950. priv->mbhc_state = MBHC_STATE_POTENTIAL;
  5951. if (!priv->mbhc_polling_active) {
  5952. pr_warn("%s: mbhc polling is not active, skip button press\n",
  5953. __func__);
  5954. goto done;
  5955. }
  5956. dce = tabla_codec_read_dce_result(codec);
  5957. mv = tabla_codec_sta_dce_v(codec, 1, dce);
  5958. /* If GPIO interrupt already kicked in, ignore button press */
  5959. if (priv->in_gpio_handler) {
  5960. pr_debug("%s: GPIO State Changed, ignore button press\n",
  5961. __func__);
  5962. btn = -1;
  5963. goto done;
  5964. }
  5965. vddio = !priv->mbhc_cfg.micbias_always_on &&
  5966. (priv->mbhc_data.micb_mv != VDDIO_MICBIAS_MV &&
  5967. priv->mbhc_micbias_switched);
  5968. mv_s = vddio ? tabla_scale_v_micb_vddio(priv, mv, false) : mv;
  5969. if (mbhc_status != TABLA_MBHC_STATUS_REL_DETECTION) {
  5970. if (priv->mbhc_last_resume &&
  5971. !time_after(jiffies, priv->mbhc_last_resume + HZ)) {
  5972. pr_debug("%s: Button is already released shortly after "
  5973. "resume\n", __func__);
  5974. n_btn_meas = 0;
  5975. }
  5976. }
  5977. /* save hw dce */
  5978. btnmeas[meas++] = tabla_determine_button(priv, mv_s);
  5979. pr_debug("%s: meas HW - DCE %x,%d,%d button %d\n", __func__,
  5980. dce, mv, mv_s, btnmeas[0]);
  5981. if (n_btn_meas == 0) {
  5982. sta = tabla_codec_read_sta_result(codec);
  5983. stamv_s = stamv = tabla_codec_sta_dce_v(codec, 0, sta);
  5984. if (vddio)
  5985. stamv_s = tabla_scale_v_micb_vddio(priv, stamv, false);
  5986. btn = tabla_determine_button(priv, stamv_s);
  5987. pr_debug("%s: meas HW - STA %x,%d,%d button %d\n", __func__,
  5988. sta, stamv, stamv_s, btn);
  5989. BUG_ON(meas != 1);
  5990. if (btnmeas[0] != btn)
  5991. btn = -1;
  5992. }
  5993. /* determine pressed button */
  5994. for (; ((d->n_btn_meas) && (meas < (d->n_btn_meas + 1))); meas++) {
  5995. dce = tabla_codec_sta_dce(codec, 1, false);
  5996. mv = tabla_codec_sta_dce_v(codec, 1, dce);
  5997. mv_s = vddio ? tabla_scale_v_micb_vddio(priv, mv, false) : mv;
  5998. btnmeas[meas] = tabla_determine_button(priv, mv_s);
  5999. pr_debug("%s: meas %d - DCE %x,%d,%d button %d\n",
  6000. __func__, meas, dce, mv, mv_s, btnmeas[meas]);
  6001. /* if large enough measurements are collected,
  6002. * start to check if last all n_btn_con measurements were
  6003. * in same button low/high range */
  6004. if (meas + 1 >= d->n_btn_con) {
  6005. for (i = 0; i < d->n_btn_con; i++)
  6006. if ((btnmeas[meas] < 0) ||
  6007. (btnmeas[meas] != btnmeas[meas - i]))
  6008. break;
  6009. if (i == d->n_btn_con) {
  6010. /* button pressed */
  6011. btn = btnmeas[meas];
  6012. break;
  6013. } else if ((n_btn_meas - meas) < (d->n_btn_con - 1)) {
  6014. /* if left measurements are less than n_btn_con,
  6015. * it's impossible to find button number */
  6016. break;
  6017. }
  6018. }
  6019. }
  6020. if (btn >= 0) {
  6021. if (priv->in_gpio_handler) {
  6022. pr_debug("%s: GPIO already triggered, ignore button "
  6023. "press\n", __func__);
  6024. goto done;
  6025. }
  6026. /* narrow down release threshold */
  6027. tabla_mbhc_set_rel_thres(codec, btn_high[btn]);
  6028. mask = tabla_get_button_mask(btn);
  6029. priv->buttons_pressed |= mask;
  6030. wcd9xxx_lock_sleep(core_res);
  6031. if (schedule_delayed_work(&priv->mbhc_btn_dwork,
  6032. msecs_to_jiffies(400)) == 0) {
  6033. WARN(1, "Button pressed twice without release"
  6034. "event\n");
  6035. wcd9xxx_unlock_sleep(core_res);
  6036. }
  6037. } else {
  6038. pr_debug("%s: bogus button press, too short press?\n",
  6039. __func__);
  6040. }
  6041. done:
  6042. pr_debug("%s: leave\n", __func__);
  6043. TABLA_RELEASE_LOCK(priv->codec_resource_lock);
  6044. return IRQ_HANDLED;
  6045. }
  6046. static int tabla_is_fake_press(struct tabla_priv *priv)
  6047. {
  6048. int i;
  6049. int r = 0;
  6050. struct snd_soc_codec *codec = priv->codec;
  6051. const int dces = MBHC_NUM_DCE_PLUG_DETECT;
  6052. s16 mb_v, v_ins_hu, v_ins_h;
  6053. v_ins_hu = tabla_get_current_v_ins(priv, true);
  6054. v_ins_h = tabla_get_current_v_ins(priv, false);
  6055. for (i = 0; i < dces; i++) {
  6056. usleep_range(10000, 10000);
  6057. if (i == 0) {
  6058. mb_v = tabla_codec_sta_dce(codec, 0, true);
  6059. pr_debug("%s: STA[0]: %d,%d\n", __func__, mb_v,
  6060. tabla_codec_sta_dce_v(codec, 0, mb_v));
  6061. if (mb_v < (s16)priv->mbhc_data.v_b1_hu ||
  6062. mb_v > v_ins_hu) {
  6063. r = 1;
  6064. break;
  6065. }
  6066. } else {
  6067. mb_v = tabla_codec_sta_dce(codec, 1, true);
  6068. pr_debug("%s: DCE[%d]: %d,%d\n", __func__, i, mb_v,
  6069. tabla_codec_sta_dce_v(codec, 1, mb_v));
  6070. if (mb_v < (s16)priv->mbhc_data.v_b1_h ||
  6071. mb_v > v_ins_h) {
  6072. r = 1;
  6073. break;
  6074. }
  6075. }
  6076. }
  6077. return r;
  6078. }
  6079. static irqreturn_t tabla_release_handler(int irq, void *data)
  6080. {
  6081. int ret;
  6082. struct tabla_priv *priv = data;
  6083. struct snd_soc_codec *codec = priv->codec;
  6084. pr_debug("%s: enter\n", __func__);
  6085. TABLA_ACQUIRE_LOCK(priv->codec_resource_lock);
  6086. priv->mbhc_state = MBHC_STATE_RELEASE;
  6087. tabla_codec_drive_v_to_micbias(codec, 10000);
  6088. if (priv->buttons_pressed & TABLA_JACK_BUTTON_MASK) {
  6089. ret = tabla_cancel_btn_work(priv);
  6090. if (ret == 0) {
  6091. pr_debug("%s: Reporting long button release event\n",
  6092. __func__);
  6093. if (priv->mbhc_cfg.button_jack)
  6094. tabla_snd_soc_jack_report(priv,
  6095. priv->mbhc_cfg.button_jack, 0,
  6096. priv->buttons_pressed);
  6097. } else {
  6098. if (tabla_is_fake_press(priv)) {
  6099. pr_debug("%s: Fake button press interrupt\n",
  6100. __func__);
  6101. } else if (priv->mbhc_cfg.button_jack) {
  6102. if (priv->in_gpio_handler) {
  6103. pr_debug("%s: GPIO kicked in, ignore\n",
  6104. __func__);
  6105. } else {
  6106. pr_debug("%s: Reporting short button "
  6107. "press and release\n",
  6108. __func__);
  6109. tabla_snd_soc_jack_report(priv,
  6110. priv->mbhc_cfg.button_jack,
  6111. priv->buttons_pressed,
  6112. priv->buttons_pressed);
  6113. tabla_snd_soc_jack_report(priv,
  6114. priv->mbhc_cfg.button_jack, 0,
  6115. priv->buttons_pressed);
  6116. }
  6117. }
  6118. }
  6119. priv->buttons_pressed &= ~TABLA_JACK_BUTTON_MASK;
  6120. }
  6121. /* revert narrowed release threshold */
  6122. tabla_mbhc_calc_rel_thres(codec, tabla_mbhc_highest_btn_mv(codec));
  6123. tabla_codec_calibrate_hs_polling(codec);
  6124. if (priv->mbhc_cfg.gpio)
  6125. msleep(TABLA_MBHC_GPIO_REL_DEBOUNCE_TIME_MS);
  6126. tabla_codec_start_hs_polling(codec);
  6127. pr_debug("%s: leave\n", __func__);
  6128. TABLA_RELEASE_LOCK(priv->codec_resource_lock);
  6129. return IRQ_HANDLED;
  6130. }
  6131. static void tabla_codec_shutdown_hs_removal_detect(struct snd_soc_codec *codec)
  6132. {
  6133. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  6134. const struct tabla_mbhc_general_cfg *generic =
  6135. TABLA_MBHC_CAL_GENERAL_PTR(tabla->mbhc_cfg.calibration);
  6136. if (!tabla->mclk_enabled && !tabla->mbhc_polling_active)
  6137. tabla_codec_enable_config_mode(codec, 1);
  6138. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0x2, 0x2);
  6139. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x6, 0x0);
  6140. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg, 0x80, 0x00);
  6141. usleep_range(generic->t_shutdown_plug_rem,
  6142. generic->t_shutdown_plug_rem);
  6143. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL, 0xA, 0x8);
  6144. if (!tabla->mclk_enabled && !tabla->mbhc_polling_active)
  6145. tabla_codec_enable_config_mode(codec, 0);
  6146. snd_soc_write(codec, TABLA_A_MBHC_SCALING_MUX_1, 0x00);
  6147. }
  6148. static void tabla_codec_cleanup_hs_polling(struct snd_soc_codec *codec)
  6149. {
  6150. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  6151. tabla_codec_shutdown_hs_removal_detect(codec);
  6152. if (!tabla->mclk_enabled) {
  6153. tabla_codec_disable_clock_block(codec);
  6154. tabla_codec_enable_bandgap(codec, TABLA_BANDGAP_OFF);
  6155. }
  6156. tabla->mbhc_polling_active = false;
  6157. tabla->mbhc_state = MBHC_STATE_NONE;
  6158. }
  6159. static irqreturn_t tabla_hphl_ocp_irq(int irq, void *data)
  6160. {
  6161. struct tabla_priv *tabla = data;
  6162. struct snd_soc_codec *codec;
  6163. pr_info("%s: received HPHL OCP irq\n", __func__);
  6164. if (tabla) {
  6165. codec = tabla->codec;
  6166. if ((tabla->hphlocp_cnt < TABLA_OCP_ATTEMPT) &&
  6167. (!tabla->hphrocp_cnt)) {
  6168. pr_info("%s: retry\n", __func__);
  6169. tabla->hphlocp_cnt++;
  6170. snd_soc_update_bits(codec, TABLA_A_RX_HPH_OCP_CTL, 0x10,
  6171. 0x00);
  6172. snd_soc_update_bits(codec, TABLA_A_RX_HPH_OCP_CTL, 0x10,
  6173. 0x10);
  6174. } else {
  6175. wcd9xxx_disable_irq(codec->control_data,
  6176. WCD9XXX_IRQ_HPH_PA_OCPL_FAULT);
  6177. tabla->hph_status |= SND_JACK_OC_HPHL;
  6178. if (tabla->mbhc_cfg.headset_jack)
  6179. tabla_snd_soc_jack_report(tabla,
  6180. tabla->mbhc_cfg.headset_jack,
  6181. tabla->hph_status,
  6182. TABLA_JACK_MASK);
  6183. }
  6184. } else {
  6185. pr_err("%s: Bad tabla private data\n", __func__);
  6186. }
  6187. return IRQ_HANDLED;
  6188. }
  6189. static irqreturn_t tabla_hphr_ocp_irq(int irq, void *data)
  6190. {
  6191. struct tabla_priv *tabla = data;
  6192. struct snd_soc_codec *codec;
  6193. pr_info("%s: received HPHR OCP irq\n", __func__);
  6194. if (tabla) {
  6195. codec = tabla->codec;
  6196. if ((tabla->hphrocp_cnt < TABLA_OCP_ATTEMPT) &&
  6197. (!tabla->hphlocp_cnt)) {
  6198. pr_info("%s: retry\n", __func__);
  6199. tabla->hphrocp_cnt++;
  6200. snd_soc_update_bits(codec, TABLA_A_RX_HPH_OCP_CTL, 0x10,
  6201. 0x00);
  6202. snd_soc_update_bits(codec, TABLA_A_RX_HPH_OCP_CTL, 0x10,
  6203. 0x10);
  6204. } else {
  6205. wcd9xxx_disable_irq(codec->control_data,
  6206. WCD9XXX_IRQ_HPH_PA_OCPR_FAULT);
  6207. tabla->hph_status |= SND_JACK_OC_HPHR;
  6208. if (tabla->mbhc_cfg.headset_jack)
  6209. tabla_snd_soc_jack_report(tabla,
  6210. tabla->mbhc_cfg.headset_jack,
  6211. tabla->hph_status,
  6212. TABLA_JACK_MASK);
  6213. }
  6214. } else {
  6215. pr_err("%s: Bad tabla private data\n", __func__);
  6216. }
  6217. return IRQ_HANDLED;
  6218. }
  6219. static bool tabla_is_inval_ins_range(struct snd_soc_codec *codec,
  6220. s32 mic_volt, bool highhph, bool *highv)
  6221. {
  6222. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  6223. bool invalid = false;
  6224. s16 v_hs_max;
  6225. /* Perform this check only when the high voltage headphone
  6226. * needs to be considered as invalid
  6227. */
  6228. v_hs_max = tabla_get_current_v_hs_max(tabla);
  6229. *highv = mic_volt > v_hs_max;
  6230. if (!highhph && *highv)
  6231. invalid = true;
  6232. else if (mic_volt < tabla->mbhc_data.v_inval_ins_high &&
  6233. (mic_volt > tabla->mbhc_data.v_inval_ins_low))
  6234. invalid = true;
  6235. return invalid;
  6236. }
  6237. static bool tabla_is_inval_ins_delta(struct snd_soc_codec *codec,
  6238. int mic_volt, int mic_volt_prev,
  6239. int threshold)
  6240. {
  6241. return abs(mic_volt - mic_volt_prev) > threshold;
  6242. }
  6243. /* called under codec_resource_lock acquisition */
  6244. void tabla_find_plug_and_report(struct snd_soc_codec *codec,
  6245. enum tabla_mbhc_plug_type plug_type)
  6246. {
  6247. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  6248. pr_debug("%s: enter current_plug(%d) new_plug(%d)\n",
  6249. __func__, tabla->current_plug, plug_type);
  6250. if (plug_type == PLUG_TYPE_HEADPHONE &&
  6251. tabla->current_plug == PLUG_TYPE_NONE) {
  6252. /* Nothing was reported previously
  6253. * report a headphone or unsupported
  6254. */
  6255. tabla_codec_report_plug(codec, 1, SND_JACK_HEADPHONE);
  6256. tabla_codec_cleanup_hs_polling(codec);
  6257. } else if (plug_type == PLUG_TYPE_GND_MIC_SWAP) {
  6258. if (!tabla->mbhc_cfg.detect_extn_cable) {
  6259. if (tabla->current_plug == PLUG_TYPE_HEADSET)
  6260. tabla_codec_report_plug(codec, 0,
  6261. SND_JACK_HEADSET);
  6262. else if (tabla->current_plug == PLUG_TYPE_HEADPHONE)
  6263. tabla_codec_report_plug(codec, 0,
  6264. SND_JACK_HEADPHONE);
  6265. }
  6266. tabla_codec_report_plug(codec, 1, SND_JACK_UNSUPPORTED);
  6267. tabla_codec_cleanup_hs_polling(codec);
  6268. } else if (plug_type == PLUG_TYPE_HEADSET) {
  6269. /* If Headphone was reported previously, this will
  6270. * only report the mic line
  6271. */
  6272. tabla_codec_report_plug(codec, 1, SND_JACK_HEADSET);
  6273. if (!tabla->mbhc_micbias_switched &&
  6274. tabla_is_hph_pa_on(codec)) {
  6275. /*If the headphone path is on, switch the micbias
  6276. to VDDIO to avoid noise due to button polling */
  6277. tabla_codec_switch_micbias(codec, 1);
  6278. pr_debug("%s: HPH path is still up\n", __func__);
  6279. }
  6280. msleep(100);
  6281. tabla_codec_start_hs_polling(codec);
  6282. } else if (plug_type == PLUG_TYPE_HIGH_HPH) {
  6283. if (tabla->mbhc_cfg.detect_extn_cable) {
  6284. /* High impedance device found. Report as LINEOUT*/
  6285. tabla_codec_report_plug(codec, 1, SND_JACK_LINEOUT);
  6286. tabla_codec_cleanup_hs_polling(codec);
  6287. pr_debug("%s: setup mic trigger for further detection\n",
  6288. __func__);
  6289. tabla->lpi_enabled = true;
  6290. /*
  6291. * Do not enable HPHL trigger. If playback is active,
  6292. * it might lead to continuous false HPHL triggers
  6293. */
  6294. tabla_codec_enable_hs_detect(codec, 1,
  6295. MBHC_USE_MB_TRIGGER,
  6296. false);
  6297. } else {
  6298. if (tabla->current_plug == PLUG_TYPE_NONE)
  6299. tabla_codec_report_plug(codec, 1,
  6300. SND_JACK_HEADPHONE);
  6301. tabla_codec_cleanup_hs_polling(codec);
  6302. pr_debug("setup mic trigger for further detection\n");
  6303. tabla->lpi_enabled = true;
  6304. tabla_codec_enable_hs_detect(codec, 1,
  6305. MBHC_USE_MB_TRIGGER |
  6306. MBHC_USE_HPHL_TRIGGER,
  6307. false);
  6308. }
  6309. } else {
  6310. WARN(1, "Unexpected current plug_type %d, plug_type %d\n",
  6311. tabla->current_plug, plug_type);
  6312. }
  6313. pr_debug("%s: leave\n", __func__);
  6314. }
  6315. /* should be called under interrupt context that hold suspend */
  6316. static void tabla_schedule_hs_detect_plug(struct tabla_priv *tabla,
  6317. struct work_struct *correct_plug_work)
  6318. {
  6319. struct wcd9xxx *core = tabla->codec->control_data;
  6320. struct wcd9xxx_core_resource *core_res = &core->core_res;
  6321. pr_debug("%s: scheduling tabla_hs_correct_gpio_plug\n", __func__);
  6322. tabla->hs_detect_work_stop = false;
  6323. wcd9xxx_lock_sleep(core_res);
  6324. schedule_work(correct_plug_work);
  6325. }
  6326. /* called under codec_resource_lock acquisition */
  6327. static void tabla_cancel_hs_detect_plug(struct tabla_priv *tabla,
  6328. struct work_struct *correct_plug_work)
  6329. {
  6330. struct wcd9xxx *core = tabla->codec->control_data;
  6331. struct wcd9xxx_core_resource *core_res = &core->core_res;
  6332. pr_debug("%s: canceling hs_correct_plug_work\n", __func__);
  6333. tabla->hs_detect_work_stop = true;
  6334. wmb();
  6335. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  6336. if (cancel_work_sync(correct_plug_work)) {
  6337. pr_debug("%s: hs_correct_plug_work is canceled\n", __func__);
  6338. wcd9xxx_unlock_sleep(core_res);
  6339. }
  6340. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  6341. }
  6342. static bool tabla_hs_gpio_level_remove(struct tabla_priv *tabla)
  6343. {
  6344. return (gpio_get_value_cansleep(tabla->mbhc_cfg.gpio) !=
  6345. tabla->mbhc_cfg.gpio_level_insert);
  6346. }
  6347. /* called under codec_resource_lock acquisition */
  6348. static void tabla_codec_hphr_gnd_switch(struct snd_soc_codec *codec, bool on)
  6349. {
  6350. snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x01, on);
  6351. if (on)
  6352. usleep_range(5000, 5000);
  6353. }
  6354. static void tabla_codec_onoff_vddio_switch(struct snd_soc_codec *codec, bool on)
  6355. {
  6356. bool override;
  6357. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  6358. pr_debug("%s: enter\n", __func__);
  6359. if (on) {
  6360. override = snd_soc_read(codec, TABLA_A_CDC_MBHC_B1_CTL) & 0x04;
  6361. if (!override)
  6362. tabla_turn_onoff_override(codec, true);
  6363. /* enable the vddio switch */
  6364. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg,
  6365. 0x91, 0x81);
  6366. /* deroute the override from MicBias2 to MicBias4 */
  6367. snd_soc_update_bits(codec, TABLA_A_MICB_1_MBHC,
  6368. 0x03, 0x03);
  6369. usleep_range(MBHC_VDDIO_SWITCH_WAIT_MS * 1000,
  6370. MBHC_VDDIO_SWITCH_WAIT_MS * 1000);
  6371. if (!override)
  6372. tabla_turn_onoff_override(codec, false);
  6373. tabla->mbhc_micbias_switched = true;
  6374. pr_debug("%s: VDDIO switch enabled\n", __func__);
  6375. } else {
  6376. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg,
  6377. 0x91, 0x00);
  6378. /* reroute the override to MicBias2 */
  6379. snd_soc_update_bits(codec, TABLA_A_MICB_1_MBHC,
  6380. 0x03, 0x01);
  6381. tabla->mbhc_micbias_switched = false;
  6382. pr_debug("%s: VDDIO switch disabled\n", __func__);
  6383. }
  6384. }
  6385. /* called under codec_resource_lock acquisition and mbhc override = 1 */
  6386. static enum tabla_mbhc_plug_type
  6387. tabla_codec_get_plug_type(struct snd_soc_codec *codec, bool highhph)
  6388. {
  6389. int i;
  6390. bool gndswitch, vddioswitch;
  6391. int scaled;
  6392. struct tabla_mbhc_plug_type_cfg *plug_type_ptr;
  6393. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  6394. const bool vddio = !tabla->mbhc_cfg.micbias_always_on &&
  6395. (tabla->mbhc_data.micb_mv != VDDIO_MICBIAS_MV);
  6396. int num_det = (MBHC_NUM_DCE_PLUG_DETECT + vddio);
  6397. enum tabla_mbhc_plug_type plug_type[num_det];
  6398. s16 mb_v[num_det];
  6399. s32 mic_mv[num_det];
  6400. bool inval;
  6401. bool highdelta = false;
  6402. bool ahighv = false, highv;
  6403. bool gndmicswapped = false;
  6404. pr_debug("%s: enter\n", __func__);
  6405. /* make sure override is on */
  6406. WARN_ON(!(snd_soc_read(codec, TABLA_A_CDC_MBHC_B1_CTL) & 0x04));
  6407. /* GND and MIC swap detection requires at least 2 rounds of DCE */
  6408. BUG_ON(num_det < 2);
  6409. plug_type_ptr =
  6410. TABLA_MBHC_CAL_PLUG_TYPE_PTR(tabla->mbhc_cfg.calibration);
  6411. plug_type[0] = PLUG_TYPE_INVALID;
  6412. /* performs DCEs for N times
  6413. * 1st: check if voltage is in invalid range
  6414. * 2nd - N-2nd: check voltage range and delta
  6415. * N-1st: check voltage range, delta with HPHR GND switch
  6416. * Nth: check voltage range with VDDIO switch */
  6417. for (i = 0; i < num_det; i++) {
  6418. gndswitch = (i == (num_det - 2));
  6419. vddioswitch = (i == (num_det - 1));
  6420. if (i == 0) {
  6421. mb_v[i] = tabla_codec_setup_hs_polling(codec);
  6422. mic_mv[i] = tabla_codec_sta_dce_v(codec, 1 , mb_v[i]);
  6423. inval = tabla_is_inval_ins_range(codec, mic_mv[i],
  6424. highhph, &highv);
  6425. ahighv |= highv;
  6426. scaled = mic_mv[i];
  6427. } else {
  6428. if (vddioswitch)
  6429. tabla_codec_onoff_vddio_switch(codec, true);
  6430. if (gndswitch)
  6431. tabla_codec_hphr_gnd_switch(codec, true);
  6432. mb_v[i] = __tabla_codec_sta_dce(codec, 1, true, true);
  6433. mic_mv[i] = tabla_codec_sta_dce_v(codec, 1 , mb_v[i]);
  6434. if (vddioswitch)
  6435. scaled = tabla_scale_v_micb_vddio(tabla,
  6436. mic_mv[i],
  6437. false);
  6438. else
  6439. scaled = mic_mv[i];
  6440. /* !gndswitch & vddioswitch means the previous DCE
  6441. * was done with gndswitch, don't compare with DCE
  6442. * with gndswitch */
  6443. highdelta = tabla_is_inval_ins_delta(codec, scaled,
  6444. mic_mv[i - 1],
  6445. TABLA_MBHC_FAKE_INS_DELTA_SCALED_MV);
  6446. inval = (tabla_is_inval_ins_range(codec, mic_mv[i],
  6447. highhph, &highv) ||
  6448. highdelta);
  6449. ahighv |= highv;
  6450. if (gndswitch)
  6451. tabla_codec_hphr_gnd_switch(codec, false);
  6452. if (vddioswitch)
  6453. tabla_codec_onoff_vddio_switch(codec, false);
  6454. }
  6455. pr_debug("%s: DCE #%d, %04x, V %d, scaled V %d, GND %d, "
  6456. "VDDIO %d, inval %d\n", __func__,
  6457. i + 1, mb_v[i] & 0xffff, mic_mv[i], scaled, gndswitch,
  6458. vddioswitch, inval);
  6459. /* don't need to run further DCEs */
  6460. if ((ahighv || !vddioswitch) && inval)
  6461. break;
  6462. mic_mv[i] = scaled;
  6463. /*
  6464. * claim UNSUPPORTED plug insertion when
  6465. * good headset is detected but HPHR GND switch makes
  6466. * delta difference
  6467. */
  6468. if (i == (num_det - 2) && highdelta && !ahighv)
  6469. gndmicswapped = true;
  6470. else if (i == (num_det - 1) && inval) {
  6471. if (gndmicswapped)
  6472. plug_type[0] = PLUG_TYPE_GND_MIC_SWAP;
  6473. else
  6474. plug_type[0] = PLUG_TYPE_INVALID;
  6475. }
  6476. }
  6477. for (i = 0; (plug_type[0] != PLUG_TYPE_GND_MIC_SWAP && !inval) &&
  6478. i < num_det; i++) {
  6479. /*
  6480. * If we are here, means none of the all
  6481. * measurements are fake, continue plug type detection.
  6482. * If all three measurements do not produce same
  6483. * plug type, restart insertion detection
  6484. */
  6485. if (mic_mv[i] < plug_type_ptr->v_no_mic) {
  6486. plug_type[i] = PLUG_TYPE_HEADPHONE;
  6487. pr_debug("%s: Detect attempt %d, detected Headphone\n",
  6488. __func__, i);
  6489. } else if (highhph && (mic_mv[i] > plug_type_ptr->v_hs_max)) {
  6490. plug_type[i] = PLUG_TYPE_HIGH_HPH;
  6491. pr_debug("%s: Detect attempt %d, detected High "
  6492. "Headphone\n", __func__, i);
  6493. } else {
  6494. plug_type[i] = PLUG_TYPE_HEADSET;
  6495. pr_debug("%s: Detect attempt %d, detected Headset\n",
  6496. __func__, i);
  6497. }
  6498. if (i > 0 && (plug_type[i - 1] != plug_type[i])) {
  6499. pr_err("%s: Detect attempt %d and %d are not same",
  6500. __func__, i - 1, i);
  6501. plug_type[0] = PLUG_TYPE_INVALID;
  6502. inval = true;
  6503. break;
  6504. }
  6505. }
  6506. pr_debug("%s: Detected plug type %d\n", __func__, plug_type[0]);
  6507. pr_debug("%s: leave\n", __func__);
  6508. return plug_type[0];
  6509. }
  6510. static void tabla_hs_correct_gpio_plug(struct work_struct *work)
  6511. {
  6512. struct tabla_priv *tabla;
  6513. struct snd_soc_codec *codec;
  6514. int retry = 0, pt_gnd_mic_swap_cnt = 0;
  6515. bool correction = false;
  6516. enum tabla_mbhc_plug_type plug_type = PLUG_TYPE_INVALID;
  6517. unsigned long timeout;
  6518. struct wcd9xxx *core;
  6519. struct wcd9xxx_core_resource *core_res;
  6520. tabla = container_of(work, struct tabla_priv, hs_correct_plug_work);
  6521. codec = tabla->codec;
  6522. core = tabla->codec->control_data;
  6523. core_res = &core->core_res;
  6524. pr_debug("%s: enter\n", __func__);
  6525. tabla->mbhc_cfg.mclk_cb_fn(codec, 1, false);
  6526. /* Keep override on during entire plug type correction work.
  6527. *
  6528. * This is okay under the assumption that any GPIO irqs which use
  6529. * MBHC block cancel and sync this work so override is off again
  6530. * prior to GPIO interrupt handler's MBHC block usage.
  6531. * Also while this correction work is running, we can guarantee
  6532. * DAPM doesn't use any MBHC block as this work only runs with
  6533. * headphone detection.
  6534. */
  6535. tabla_turn_onoff_override(codec, true);
  6536. timeout = jiffies + msecs_to_jiffies(TABLA_HS_DETECT_PLUG_TIME_MS);
  6537. while (!time_after(jiffies, timeout)) {
  6538. ++retry;
  6539. rmb();
  6540. if (tabla->hs_detect_work_stop) {
  6541. pr_debug("%s: stop requested\n", __func__);
  6542. break;
  6543. }
  6544. msleep(TABLA_HS_DETECT_PLUG_INERVAL_MS);
  6545. if (tabla_hs_gpio_level_remove(tabla)) {
  6546. pr_debug("%s: GPIO value is low\n", __func__);
  6547. break;
  6548. }
  6549. /* can race with removal interrupt */
  6550. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  6551. plug_type = tabla_codec_get_plug_type(codec, true);
  6552. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  6553. pr_debug("%s: attempt(%d) current_plug(%d) new_plug(%d)\n",
  6554. __func__, retry, tabla->current_plug, plug_type);
  6555. if (plug_type == PLUG_TYPE_INVALID) {
  6556. pr_debug("Invalid plug in attempt # %d\n", retry);
  6557. if (!tabla->mbhc_cfg.detect_extn_cable &&
  6558. retry == NUM_ATTEMPTS_TO_REPORT &&
  6559. tabla->current_plug == PLUG_TYPE_NONE) {
  6560. tabla_codec_report_plug(codec, 1,
  6561. SND_JACK_HEADPHONE);
  6562. }
  6563. } else if (plug_type == PLUG_TYPE_HEADPHONE) {
  6564. pr_debug("Good headphone detected, continue polling mic\n");
  6565. if (tabla->mbhc_cfg.detect_extn_cable) {
  6566. if (tabla->current_plug != plug_type)
  6567. tabla_codec_report_plug(codec, 1,
  6568. SND_JACK_HEADPHONE);
  6569. } else if (tabla->current_plug == PLUG_TYPE_NONE)
  6570. tabla_codec_report_plug(codec, 1,
  6571. SND_JACK_HEADPHONE);
  6572. } else {
  6573. if (plug_type == PLUG_TYPE_GND_MIC_SWAP) {
  6574. pt_gnd_mic_swap_cnt++;
  6575. if (pt_gnd_mic_swap_cnt <
  6576. TABLA_MBHC_GND_MIC_SWAP_THRESHOLD)
  6577. continue;
  6578. else if (pt_gnd_mic_swap_cnt >
  6579. TABLA_MBHC_GND_MIC_SWAP_THRESHOLD) {
  6580. /* This is due to GND/MIC switch didn't
  6581. * work, Report unsupported plug */
  6582. } else if (tabla->mbhc_cfg.swap_gnd_mic) {
  6583. /* if switch is toggled, check again,
  6584. * otherwise report unsupported plug */
  6585. if (tabla->mbhc_cfg.swap_gnd_mic(codec))
  6586. continue;
  6587. }
  6588. } else
  6589. pt_gnd_mic_swap_cnt = 0;
  6590. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  6591. /* Turn off override */
  6592. tabla_turn_onoff_override(codec, false);
  6593. /* The valid plug also includes PLUG_TYPE_GND_MIC_SWAP
  6594. */
  6595. tabla_find_plug_and_report(codec, plug_type);
  6596. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  6597. pr_debug("Attempt %d found correct plug %d\n", retry,
  6598. plug_type);
  6599. correction = true;
  6600. break;
  6601. }
  6602. }
  6603. /* Turn off override */
  6604. if (!correction)
  6605. tabla_turn_onoff_override(codec, false);
  6606. tabla->mbhc_cfg.mclk_cb_fn(codec, 0, false);
  6607. if (tabla->mbhc_cfg.detect_extn_cable) {
  6608. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  6609. if (tabla->current_plug == PLUG_TYPE_HEADPHONE ||
  6610. tabla->current_plug == PLUG_TYPE_GND_MIC_SWAP ||
  6611. tabla->current_plug == PLUG_TYPE_INVALID ||
  6612. plug_type == PLUG_TYPE_INVALID) {
  6613. /* Enable removal detection */
  6614. tabla_codec_cleanup_hs_polling(codec);
  6615. tabla_codec_enable_hs_detect(codec, 0, 0, false);
  6616. }
  6617. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  6618. }
  6619. pr_debug("%s: leave current_plug(%d)\n",
  6620. __func__, tabla->current_plug);
  6621. /* unlock sleep */
  6622. wcd9xxx_unlock_sleep(core_res);
  6623. }
  6624. /* called under codec_resource_lock acquisition */
  6625. static void tabla_codec_decide_gpio_plug(struct snd_soc_codec *codec)
  6626. {
  6627. enum tabla_mbhc_plug_type plug_type;
  6628. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  6629. pr_debug("%s: enter\n", __func__);
  6630. tabla_turn_onoff_override(codec, true);
  6631. plug_type = tabla_codec_get_plug_type(codec, true);
  6632. tabla_turn_onoff_override(codec, false);
  6633. if (tabla_hs_gpio_level_remove(tabla)) {
  6634. pr_debug("%s: GPIO value is low when determining plug\n",
  6635. __func__);
  6636. return;
  6637. }
  6638. if (plug_type == PLUG_TYPE_INVALID ||
  6639. plug_type == PLUG_TYPE_GND_MIC_SWAP) {
  6640. tabla_schedule_hs_detect_plug(tabla,
  6641. &tabla->hs_correct_plug_work);
  6642. } else if (plug_type == PLUG_TYPE_HEADPHONE) {
  6643. tabla_codec_report_plug(codec, 1, SND_JACK_HEADPHONE);
  6644. tabla_schedule_hs_detect_plug(tabla,
  6645. &tabla->hs_correct_plug_work);
  6646. } else {
  6647. pr_debug("%s: Valid plug found, determine plug type %d\n",
  6648. __func__, plug_type);
  6649. tabla_find_plug_and_report(codec, plug_type);
  6650. }
  6651. pr_debug("%s: leave\n", __func__);
  6652. }
  6653. /* called under codec_resource_lock acquisition */
  6654. static void tabla_codec_detect_plug_type(struct snd_soc_codec *codec)
  6655. {
  6656. enum tabla_mbhc_plug_type plug_type;
  6657. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  6658. const struct tabla_mbhc_plug_detect_cfg *plug_det =
  6659. TABLA_MBHC_CAL_PLUG_DET_PTR(tabla->mbhc_cfg.calibration);
  6660. pr_debug("%s: enter\n", __func__);
  6661. /* Turn on the override,
  6662. * tabla_codec_setup_hs_polling requires override on */
  6663. tabla_turn_onoff_override(codec, true);
  6664. if (plug_det->t_ins_complete > 20)
  6665. msleep(plug_det->t_ins_complete);
  6666. else
  6667. usleep_range(plug_det->t_ins_complete * 1000,
  6668. plug_det->t_ins_complete * 1000);
  6669. if (tabla->mbhc_cfg.gpio) {
  6670. /* Turn off the override */
  6671. tabla_turn_onoff_override(codec, false);
  6672. if (tabla_hs_gpio_level_remove(tabla))
  6673. pr_debug("%s: GPIO value is low when determining "
  6674. "plug\n", __func__);
  6675. else
  6676. tabla_codec_decide_gpio_plug(codec);
  6677. pr_debug("%s: leave\n", __func__);
  6678. return;
  6679. }
  6680. plug_type = tabla_codec_get_plug_type(codec, false);
  6681. tabla_turn_onoff_override(codec, false);
  6682. if (plug_type == PLUG_TYPE_INVALID) {
  6683. pr_debug("%s: Invalid plug type detected\n", __func__);
  6684. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_B1_CTL, 0x02, 0x02);
  6685. tabla_codec_cleanup_hs_polling(codec);
  6686. tabla_codec_enable_hs_detect(codec, 1,
  6687. MBHC_USE_MB_TRIGGER |
  6688. MBHC_USE_HPHL_TRIGGER, false);
  6689. } else if (plug_type == PLUG_TYPE_GND_MIC_SWAP) {
  6690. pr_debug("%s: GND-MIC swapped plug type detected\n", __func__);
  6691. tabla_codec_report_plug(codec, 1, SND_JACK_UNSUPPORTED);
  6692. tabla_codec_cleanup_hs_polling(codec);
  6693. tabla_codec_enable_hs_detect(codec, 0, 0, false);
  6694. } else if (plug_type == PLUG_TYPE_HEADPHONE) {
  6695. pr_debug("%s: Headphone Detected\n", __func__);
  6696. tabla_codec_report_plug(codec, 1, SND_JACK_HEADPHONE);
  6697. tabla_codec_cleanup_hs_polling(codec);
  6698. tabla_schedule_hs_detect_plug(tabla,
  6699. &tabla->hs_correct_plug_work_nogpio);
  6700. } else if (plug_type == PLUG_TYPE_HEADSET) {
  6701. pr_debug("%s: Headset detected\n", __func__);
  6702. tabla_codec_report_plug(codec, 1, SND_JACK_HEADSET);
  6703. /* avoid false button press detect */
  6704. msleep(50);
  6705. tabla_codec_start_hs_polling(codec);
  6706. } else if (tabla->mbhc_cfg.detect_extn_cable &&
  6707. plug_type == PLUG_TYPE_HIGH_HPH) {
  6708. pr_debug("%s: High impedance plug type detected\n", __func__);
  6709. tabla_codec_report_plug(codec, 1, SND_JACK_LINEOUT);
  6710. /* Enable insertion detection on the other end of cable */
  6711. tabla_codec_cleanup_hs_polling(codec);
  6712. tabla_codec_enable_hs_detect(codec, 1,
  6713. MBHC_USE_MB_TRIGGER, false);
  6714. }
  6715. pr_debug("%s: leave\n", __func__);
  6716. }
  6717. /* called only from interrupt which is under codec_resource_lock acquisition */
  6718. static void tabla_hs_insert_irq_gpio(struct tabla_priv *priv, bool is_removal)
  6719. {
  6720. struct snd_soc_codec *codec = priv->codec;
  6721. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  6722. if (!is_removal) {
  6723. pr_debug("%s: MIC trigger insertion interrupt\n", __func__);
  6724. rmb();
  6725. if (priv->lpi_enabled)
  6726. msleep(100);
  6727. rmb();
  6728. if (!priv->lpi_enabled) {
  6729. pr_debug("%s: lpi is disabled\n", __func__);
  6730. } else if (gpio_get_value_cansleep(priv->mbhc_cfg.gpio) ==
  6731. priv->mbhc_cfg.gpio_level_insert) {
  6732. pr_debug("%s: Valid insertion, "
  6733. "detect plug type\n", __func__);
  6734. tabla_codec_decide_gpio_plug(codec);
  6735. } else {
  6736. pr_debug("%s: Invalid insertion, "
  6737. "stop plug detection\n", __func__);
  6738. }
  6739. } else if (tabla->mbhc_cfg.detect_extn_cable) {
  6740. pr_debug("%s: Removal\n", __func__);
  6741. if (!tabla_hs_gpio_level_remove(tabla)) {
  6742. /*
  6743. * gpio says, something is still inserted, could be
  6744. * extension cable i.e. headset is removed from
  6745. * extension cable
  6746. */
  6747. /* cancel detect plug */
  6748. tabla_cancel_hs_detect_plug(tabla,
  6749. &tabla->hs_correct_plug_work);
  6750. tabla_codec_decide_gpio_plug(codec);
  6751. }
  6752. } else {
  6753. pr_err("%s: GPIO used, invalid MBHC Removal\n", __func__);
  6754. }
  6755. }
  6756. /* called only from interrupt which is under codec_resource_lock acquisition */
  6757. static void tabla_hs_insert_irq_nogpio(struct tabla_priv *priv, bool is_removal,
  6758. bool is_mb_trigger)
  6759. {
  6760. int ret;
  6761. struct snd_soc_codec *codec = priv->codec;
  6762. struct wcd9xxx *core = dev_get_drvdata(priv->codec->dev->parent);
  6763. struct wcd9xxx_core_resource *core_res = &core->core_res;
  6764. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  6765. /* Cancel possibly running hs_detect_work */
  6766. tabla_cancel_hs_detect_plug(tabla,
  6767. &tabla->hs_correct_plug_work_nogpio);
  6768. if (is_removal) {
  6769. /*
  6770. * If headphone is removed while playback is in progress,
  6771. * it is possible that micbias will be switched to VDDIO.
  6772. */
  6773. tabla_codec_switch_micbias(codec, 0);
  6774. if (priv->current_plug == PLUG_TYPE_HEADPHONE)
  6775. tabla_codec_report_plug(codec, 0, SND_JACK_HEADPHONE);
  6776. else if (priv->current_plug == PLUG_TYPE_GND_MIC_SWAP)
  6777. tabla_codec_report_plug(codec, 0, SND_JACK_UNSUPPORTED);
  6778. else
  6779. WARN(1, "%s: Unexpected current plug type %d\n",
  6780. __func__, priv->current_plug);
  6781. tabla_codec_shutdown_hs_removal_detect(codec);
  6782. tabla_codec_enable_hs_detect(codec, 1,
  6783. MBHC_USE_MB_TRIGGER |
  6784. MBHC_USE_HPHL_TRIGGER,
  6785. true);
  6786. } else if (is_mb_trigger && !is_removal) {
  6787. pr_debug("%s: Waiting for Headphone left trigger\n",
  6788. __func__);
  6789. wcd9xxx_lock_sleep(core_res);
  6790. if (schedule_delayed_work(&priv->mbhc_insert_dwork,
  6791. usecs_to_jiffies(1000000)) == 0) {
  6792. pr_err("%s: mbhc_insert_dwork is already scheduled\n",
  6793. __func__);
  6794. wcd9xxx_unlock_sleep(core_res);
  6795. }
  6796. tabla_codec_enable_hs_detect(codec, 1, MBHC_USE_HPHL_TRIGGER,
  6797. false);
  6798. } else {
  6799. ret = cancel_delayed_work(&priv->mbhc_insert_dwork);
  6800. if (ret != 0) {
  6801. pr_debug("%s: Complete plug insertion, Detecting plug "
  6802. "type\n", __func__);
  6803. tabla_codec_detect_plug_type(codec);
  6804. wcd9xxx_unlock_sleep(core_res);
  6805. } else {
  6806. wcd9xxx_enable_irq(codec->control_data,
  6807. WCD9XXX_IRQ_MBHC_INSERTION);
  6808. pr_err("%s: Error detecting plug insertion\n",
  6809. __func__);
  6810. }
  6811. }
  6812. }
  6813. /* called only from interrupt which is under codec_resource_lock acquisition */
  6814. static void tabla_hs_insert_irq_extn(struct tabla_priv *priv,
  6815. bool is_mb_trigger)
  6816. {
  6817. struct snd_soc_codec *codec = priv->codec;
  6818. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  6819. /* Cancel possibly running hs_detect_work */
  6820. tabla_cancel_hs_detect_plug(tabla,
  6821. &tabla->hs_correct_plug_work);
  6822. if (is_mb_trigger) {
  6823. pr_debug("%s: Waiting for Headphone left trigger\n",
  6824. __func__);
  6825. tabla_codec_enable_hs_detect(codec, 1, MBHC_USE_HPHL_TRIGGER,
  6826. false);
  6827. } else {
  6828. pr_debug("%s: HPHL trigger received, detecting plug type\n",
  6829. __func__);
  6830. tabla_codec_detect_plug_type(codec);
  6831. }
  6832. }
  6833. static irqreturn_t tabla_hs_insert_irq(int irq, void *data)
  6834. {
  6835. bool is_mb_trigger, is_removal;
  6836. struct tabla_priv *priv = data;
  6837. struct snd_soc_codec *codec = priv->codec;
  6838. pr_debug("%s: enter\n", __func__);
  6839. TABLA_ACQUIRE_LOCK(priv->codec_resource_lock);
  6840. wcd9xxx_disable_irq(codec->control_data, WCD9XXX_IRQ_MBHC_INSERTION);
  6841. is_mb_trigger = !!(snd_soc_read(codec, priv->mbhc_bias_regs.mbhc_reg) &
  6842. 0x10);
  6843. is_removal = !!(snd_soc_read(codec, TABLA_A_CDC_MBHC_INT_CTL) & 0x02);
  6844. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_INT_CTL, 0x03, 0x00);
  6845. /* Turn off both HPH and MIC line schmitt triggers */
  6846. snd_soc_update_bits(codec, priv->mbhc_bias_regs.mbhc_reg, 0x90, 0x00);
  6847. snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x13, 0x00);
  6848. snd_soc_update_bits(codec, priv->mbhc_bias_regs.ctl_reg, 0x01, 0x00);
  6849. if (priv->mbhc_cfg.detect_extn_cable &&
  6850. priv->current_plug == PLUG_TYPE_HIGH_HPH)
  6851. tabla_hs_insert_irq_extn(priv, is_mb_trigger);
  6852. else if (priv->mbhc_cfg.gpio)
  6853. tabla_hs_insert_irq_gpio(priv, is_removal);
  6854. else
  6855. tabla_hs_insert_irq_nogpio(priv, is_removal, is_mb_trigger);
  6856. TABLA_RELEASE_LOCK(priv->codec_resource_lock);
  6857. return IRQ_HANDLED;
  6858. }
  6859. static bool is_valid_mic_voltage(struct snd_soc_codec *codec, s32 mic_mv)
  6860. {
  6861. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  6862. const struct tabla_mbhc_plug_type_cfg *plug_type =
  6863. TABLA_MBHC_CAL_PLUG_TYPE_PTR(tabla->mbhc_cfg.calibration);
  6864. const s16 v_hs_max = tabla_get_current_v_hs_max(tabla);
  6865. return (!(mic_mv > 10 && mic_mv < 80) && (mic_mv > plug_type->v_no_mic)
  6866. && (mic_mv < v_hs_max)) ? true : false;
  6867. }
  6868. /* called under codec_resource_lock acquisition
  6869. * returns true if mic voltage range is back to normal insertion
  6870. * returns false either if timedout or removed */
  6871. static bool tabla_hs_remove_settle(struct snd_soc_codec *codec)
  6872. {
  6873. int i;
  6874. bool timedout, settled = false;
  6875. s32 mic_mv[MBHC_NUM_DCE_PLUG_DETECT];
  6876. short mb_v[MBHC_NUM_DCE_PLUG_DETECT];
  6877. unsigned long retry = 0, timeout;
  6878. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  6879. const s16 v_hs_max = tabla_get_current_v_hs_max(tabla);
  6880. timeout = jiffies + msecs_to_jiffies(TABLA_HS_DETECT_PLUG_TIME_MS);
  6881. while (!(timedout = time_after(jiffies, timeout))) {
  6882. retry++;
  6883. if (tabla->mbhc_cfg.gpio && tabla_hs_gpio_level_remove(tabla)) {
  6884. pr_debug("%s: GPIO indicates removal\n", __func__);
  6885. break;
  6886. }
  6887. if (tabla->mbhc_cfg.gpio) {
  6888. if (retry > 1)
  6889. msleep(250);
  6890. else
  6891. msleep(50);
  6892. }
  6893. if (tabla->mbhc_cfg.gpio && tabla_hs_gpio_level_remove(tabla)) {
  6894. pr_debug("%s: GPIO indicates removal\n", __func__);
  6895. break;
  6896. }
  6897. for (i = 0; i < MBHC_NUM_DCE_PLUG_DETECT; i++) {
  6898. mb_v[i] = tabla_codec_sta_dce(codec, 1, true);
  6899. mic_mv[i] = tabla_codec_sta_dce_v(codec, 1 , mb_v[i]);
  6900. pr_debug("%s : DCE run %lu, mic_mv = %d(%x)\n",
  6901. __func__, retry, mic_mv[i], mb_v[i]);
  6902. }
  6903. if (tabla->mbhc_cfg.gpio && tabla_hs_gpio_level_remove(tabla)) {
  6904. pr_debug("%s: GPIO indicates removal\n", __func__);
  6905. break;
  6906. }
  6907. if (tabla->current_plug == PLUG_TYPE_NONE) {
  6908. pr_debug("%s : headset/headphone is removed\n",
  6909. __func__);
  6910. break;
  6911. }
  6912. for (i = 0; i < MBHC_NUM_DCE_PLUG_DETECT; i++)
  6913. if (!is_valid_mic_voltage(codec, mic_mv[i]))
  6914. break;
  6915. if (i == MBHC_NUM_DCE_PLUG_DETECT) {
  6916. pr_debug("%s: MIC voltage settled\n", __func__);
  6917. settled = true;
  6918. msleep(200);
  6919. break;
  6920. }
  6921. /* only for non-GPIO remove irq */
  6922. if (!tabla->mbhc_cfg.gpio) {
  6923. for (i = 0; i < MBHC_NUM_DCE_PLUG_DETECT; i++)
  6924. if (mic_mv[i] < v_hs_max)
  6925. break;
  6926. if (i == MBHC_NUM_DCE_PLUG_DETECT) {
  6927. pr_debug("%s: Headset is removed\n", __func__);
  6928. break;
  6929. }
  6930. }
  6931. }
  6932. if (timedout)
  6933. pr_debug("%s: Microphone did not settle in %d seconds\n",
  6934. __func__, TABLA_HS_DETECT_PLUG_TIME_MS);
  6935. return settled;
  6936. }
  6937. /* called only from interrupt which is under codec_resource_lock acquisition */
  6938. static void tabla_hs_remove_irq_gpio(struct tabla_priv *priv)
  6939. {
  6940. struct snd_soc_codec *codec = priv->codec;
  6941. pr_debug("%s: enter\n", __func__);
  6942. if (tabla_hs_remove_settle(codec))
  6943. tabla_codec_start_hs_polling(codec);
  6944. pr_debug("%s: leave\n", __func__);
  6945. }
  6946. /* called only from interrupt which is under codec_resource_lock acquisition */
  6947. static void tabla_hs_remove_irq_nogpio(struct tabla_priv *priv)
  6948. {
  6949. short bias_value;
  6950. bool removed = true;
  6951. struct snd_soc_codec *codec = priv->codec;
  6952. const struct tabla_mbhc_general_cfg *generic =
  6953. TABLA_MBHC_CAL_GENERAL_PTR(priv->mbhc_cfg.calibration);
  6954. int min_us = TABLA_FAKE_REMOVAL_MIN_PERIOD_MS * 1000;
  6955. pr_debug("%s: enter\n", __func__);
  6956. if (priv->current_plug != PLUG_TYPE_HEADSET) {
  6957. pr_debug("%s(): Headset is not inserted, ignore removal\n",
  6958. __func__);
  6959. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL,
  6960. 0x08, 0x08);
  6961. return;
  6962. }
  6963. usleep_range(generic->t_shutdown_plug_rem,
  6964. generic->t_shutdown_plug_rem);
  6965. do {
  6966. bias_value = tabla_codec_sta_dce(codec, 1, true);
  6967. pr_debug("%s: DCE %d,%d, %d us left\n", __func__, bias_value,
  6968. tabla_codec_sta_dce_v(codec, 1, bias_value), min_us);
  6969. if (bias_value < tabla_get_current_v_ins(priv, false)) {
  6970. pr_debug("%s: checking false removal\n", __func__);
  6971. msleep(500);
  6972. removed = !tabla_hs_remove_settle(codec);
  6973. pr_debug("%s: headset %sactually removed\n", __func__,
  6974. removed ? "" : "not ");
  6975. break;
  6976. }
  6977. min_us -= priv->mbhc_data.t_dce;
  6978. } while (min_us > 0);
  6979. if (removed) {
  6980. if (priv->mbhc_cfg.detect_extn_cable) {
  6981. if (!tabla_hs_gpio_level_remove(priv)) {
  6982. /*
  6983. * extension cable is still plugged in
  6984. * report it as LINEOUT device
  6985. */
  6986. tabla_codec_report_plug(codec, 1,
  6987. SND_JACK_LINEOUT);
  6988. tabla_codec_cleanup_hs_polling(codec);
  6989. tabla_codec_enable_hs_detect(codec, 1,
  6990. MBHC_USE_MB_TRIGGER,
  6991. false);
  6992. }
  6993. } else {
  6994. /* Cancel possibly running hs_detect_work */
  6995. tabla_cancel_hs_detect_plug(priv,
  6996. &priv->hs_correct_plug_work_nogpio);
  6997. /*
  6998. * If this removal is not false, first check the micbias
  6999. * switch status and switch it to LDOH if it is already
  7000. * switched to VDDIO.
  7001. */
  7002. tabla_codec_switch_micbias(codec, 0);
  7003. tabla_codec_report_plug(codec, 0, SND_JACK_HEADSET);
  7004. tabla_codec_cleanup_hs_polling(codec);
  7005. tabla_codec_enable_hs_detect(codec, 1,
  7006. MBHC_USE_MB_TRIGGER |
  7007. MBHC_USE_HPHL_TRIGGER,
  7008. true);
  7009. }
  7010. } else {
  7011. tabla_codec_start_hs_polling(codec);
  7012. }
  7013. pr_debug("%s: leave\n", __func__);
  7014. }
  7015. static irqreturn_t tabla_hs_remove_irq(int irq, void *data)
  7016. {
  7017. struct tabla_priv *priv = data;
  7018. bool vddio;
  7019. pr_debug("%s: enter, removal interrupt\n", __func__);
  7020. TABLA_ACQUIRE_LOCK(priv->codec_resource_lock);
  7021. vddio = !priv->mbhc_cfg.micbias_always_on &&
  7022. (priv->mbhc_data.micb_mv != VDDIO_MICBIAS_MV &&
  7023. priv->mbhc_micbias_switched);
  7024. if (vddio)
  7025. __tabla_codec_switch_micbias(priv->codec, 0, false, true);
  7026. if ((priv->mbhc_cfg.detect_extn_cable &&
  7027. !tabla_hs_gpio_level_remove(priv)) ||
  7028. !priv->mbhc_cfg.gpio) {
  7029. tabla_hs_remove_irq_nogpio(priv);
  7030. } else
  7031. tabla_hs_remove_irq_gpio(priv);
  7032. /* if driver turned off vddio switch and headset is not removed,
  7033. * turn on the vddio switch back, if headset is removed then vddio
  7034. * switch is off by time now and shouldn't be turn on again from here */
  7035. if (vddio && priv->current_plug == PLUG_TYPE_HEADSET)
  7036. __tabla_codec_switch_micbias(priv->codec, 1, true, true);
  7037. TABLA_RELEASE_LOCK(priv->codec_resource_lock);
  7038. return IRQ_HANDLED;
  7039. }
  7040. void mbhc_insert_work(struct work_struct *work)
  7041. {
  7042. struct delayed_work *dwork;
  7043. struct tabla_priv *tabla;
  7044. struct snd_soc_codec *codec;
  7045. struct wcd9xxx *tabla_core;
  7046. struct wcd9xxx_core_resource *core_res;
  7047. dwork = to_delayed_work(work);
  7048. tabla = container_of(dwork, struct tabla_priv, mbhc_insert_dwork);
  7049. codec = tabla->codec;
  7050. tabla_core = dev_get_drvdata(codec->dev->parent);
  7051. core_res = &tabla_core->core_res;
  7052. pr_debug("%s:\n", __func__);
  7053. /* Turn off both HPH and MIC line schmitt triggers */
  7054. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.mbhc_reg, 0x90, 0x00);
  7055. snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x13, 0x00);
  7056. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.ctl_reg, 0x01, 0x00);
  7057. wcd9xxx_disable_irq_sync(codec->control_data,
  7058. WCD9XXX_IRQ_MBHC_INSERTION);
  7059. tabla_codec_detect_plug_type(codec);
  7060. wcd9xxx_unlock_sleep(core_res);
  7061. }
  7062. static void tabla_hs_gpio_handler(struct snd_soc_codec *codec)
  7063. {
  7064. bool insert;
  7065. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  7066. struct wcd9xxx *core = dev_get_drvdata(codec->dev->parent);
  7067. bool is_removed = false;
  7068. pr_debug("%s: enter\n", __func__);
  7069. tabla->in_gpio_handler = true;
  7070. /* Wait here for debounce time */
  7071. usleep_range(TABLA_GPIO_IRQ_DEBOUNCE_TIME_US,
  7072. TABLA_GPIO_IRQ_DEBOUNCE_TIME_US);
  7073. wcd9xxx_nested_irq_lock(&core->core_res);
  7074. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  7075. /* cancel pending button press */
  7076. if (tabla_cancel_btn_work(tabla))
  7077. pr_debug("%s: button press is canceled\n", __func__);
  7078. insert = (gpio_get_value_cansleep(tabla->mbhc_cfg.gpio) ==
  7079. tabla->mbhc_cfg.gpio_level_insert);
  7080. if ((tabla->current_plug == PLUG_TYPE_NONE) && insert) {
  7081. tabla->lpi_enabled = false;
  7082. wmb();
  7083. /* cancel detect plug */
  7084. tabla_cancel_hs_detect_plug(tabla,
  7085. &tabla->hs_correct_plug_work);
  7086. /* Disable Mic Bias pull down and HPH Switch to GND */
  7087. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.ctl_reg, 0x01,
  7088. 0x00);
  7089. snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x01, 0x00);
  7090. tabla_codec_detect_plug_type(codec);
  7091. } else if ((tabla->current_plug != PLUG_TYPE_NONE) && !insert) {
  7092. tabla->lpi_enabled = false;
  7093. wmb();
  7094. /* cancel detect plug */
  7095. tabla_cancel_hs_detect_plug(tabla,
  7096. &tabla->hs_correct_plug_work);
  7097. if (tabla->current_plug == PLUG_TYPE_HEADPHONE) {
  7098. tabla_codec_report_plug(codec, 0, SND_JACK_HEADPHONE);
  7099. is_removed = true;
  7100. } else if (tabla->current_plug == PLUG_TYPE_GND_MIC_SWAP) {
  7101. tabla_codec_report_plug(codec, 0, SND_JACK_UNSUPPORTED);
  7102. is_removed = true;
  7103. } else if (tabla->current_plug == PLUG_TYPE_HEADSET) {
  7104. tabla_codec_pause_hs_polling(codec);
  7105. tabla_codec_cleanup_hs_polling(codec);
  7106. tabla_codec_report_plug(codec, 0, SND_JACK_HEADSET);
  7107. is_removed = true;
  7108. } else if (tabla->current_plug == PLUG_TYPE_HIGH_HPH) {
  7109. tabla_codec_report_plug(codec, 0, SND_JACK_LINEOUT);
  7110. is_removed = true;
  7111. }
  7112. if (is_removed) {
  7113. /* Enable Mic Bias pull down and HPH Switch to GND */
  7114. snd_soc_update_bits(codec,
  7115. tabla->mbhc_bias_regs.ctl_reg, 0x01,
  7116. 0x01);
  7117. snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x01,
  7118. 0x01);
  7119. /* Make sure mic trigger is turned off */
  7120. snd_soc_update_bits(codec,
  7121. tabla->mbhc_bias_regs.ctl_reg,
  7122. 0x01, 0x01);
  7123. snd_soc_update_bits(codec,
  7124. tabla->mbhc_bias_regs.mbhc_reg,
  7125. 0x90, 0x00);
  7126. /* Reset MBHC State Machine */
  7127. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL,
  7128. 0x08, 0x08);
  7129. snd_soc_update_bits(codec, TABLA_A_CDC_MBHC_CLK_CTL,
  7130. 0x08, 0x00);
  7131. /* Turn off override */
  7132. tabla_turn_onoff_override(codec, false);
  7133. tabla_codec_switch_micbias(codec, 0);
  7134. }
  7135. }
  7136. tabla->in_gpio_handler = false;
  7137. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  7138. wcd9xxx_nested_irq_unlock(&core->core_res);
  7139. pr_debug("%s: leave\n", __func__);
  7140. }
  7141. static irqreturn_t tabla_mechanical_plug_detect_irq(int irq, void *data)
  7142. {
  7143. int r = IRQ_HANDLED;
  7144. struct snd_soc_codec *codec = data;
  7145. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  7146. struct wcd9xxx *core = codec->control_data;
  7147. struct wcd9xxx_core_resource *core_res = &core->core_res;
  7148. if (unlikely(wcd9xxx_lock_sleep(core_res) == false)) {
  7149. pr_warn("%s: failed to hold suspend\n", __func__);
  7150. /*
  7151. * Give up this IRQ for now and resend this IRQ so IRQ can be
  7152. * handled after system resume
  7153. */
  7154. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  7155. tabla->gpio_irq_resend = true;
  7156. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  7157. wake_lock_timeout(&tabla->irq_resend_wlock, HZ);
  7158. r = IRQ_NONE;
  7159. } else {
  7160. tabla_hs_gpio_handler(codec);
  7161. wcd9xxx_unlock_sleep(core_res);
  7162. }
  7163. return r;
  7164. }
  7165. static void tabla_hs_correct_plug_nogpio(struct work_struct *work)
  7166. {
  7167. struct tabla_priv *tabla;
  7168. struct snd_soc_codec *codec;
  7169. unsigned long timeout;
  7170. int retry = 0;
  7171. enum tabla_mbhc_plug_type plug_type;
  7172. bool is_headset = false;
  7173. struct wcd9xxx *core;
  7174. struct wcd9xxx_core_resource *core_res;
  7175. pr_debug("%s(): Poll Microphone voltage for %d seconds\n",
  7176. __func__, TABLA_HS_DETECT_PLUG_TIME_MS / 1000);
  7177. tabla = container_of(work, struct tabla_priv,
  7178. hs_correct_plug_work_nogpio);
  7179. codec = tabla->codec;
  7180. core = codec->control_data;
  7181. core_res = &core->core_res;
  7182. /* Make sure the MBHC mux is connected to MIC Path */
  7183. snd_soc_write(codec, TABLA_A_MBHC_SCALING_MUX_1, 0x84);
  7184. /* setup for microphone polling */
  7185. tabla_turn_onoff_override(codec, true);
  7186. tabla->mbhc_cfg.mclk_cb_fn(codec, 1, false);
  7187. timeout = jiffies + msecs_to_jiffies(TABLA_HS_DETECT_PLUG_TIME_MS);
  7188. while (!time_after(jiffies, timeout)) {
  7189. ++retry;
  7190. msleep(TABLA_HS_DETECT_PLUG_INERVAL_MS);
  7191. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  7192. plug_type = tabla_codec_get_plug_type(codec, false);
  7193. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  7194. if (plug_type == PLUG_TYPE_HIGH_HPH
  7195. || plug_type == PLUG_TYPE_INVALID) {
  7196. /* this means the plug is removed
  7197. * End microphone polling and setup
  7198. * for low power removal detection.
  7199. */
  7200. pr_debug("%s(): Plug may be removed, setup removal\n",
  7201. __func__);
  7202. break;
  7203. } else if (plug_type == PLUG_TYPE_HEADSET) {
  7204. /* Plug is corrected from headphone to headset,
  7205. * report headset and end the polling
  7206. */
  7207. is_headset = true;
  7208. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  7209. tabla_turn_onoff_override(codec, false);
  7210. tabla_codec_report_plug(codec, 1, SND_JACK_HEADSET);
  7211. tabla_codec_start_hs_polling(codec);
  7212. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  7213. pr_debug("%s(): corrected from headphone to headset\n",
  7214. __func__);
  7215. break;
  7216. }
  7217. }
  7218. /* Undo setup for microphone polling depending
  7219. * result from polling
  7220. */
  7221. tabla->mbhc_cfg.mclk_cb_fn(codec, 0, false);
  7222. if (!is_headset) {
  7223. pr_debug("%s: Inserted headphone is not a headset\n",
  7224. __func__);
  7225. tabla_turn_onoff_override(codec, false);
  7226. tabla_codec_cleanup_hs_polling(codec);
  7227. tabla_codec_enable_hs_detect(codec, 0, 0, false);
  7228. }
  7229. wcd9xxx_unlock_sleep(core_res);
  7230. }
  7231. static int tabla_mbhc_init_and_calibrate(struct tabla_priv *tabla)
  7232. {
  7233. int ret = 0;
  7234. struct snd_soc_codec *codec = tabla->codec;
  7235. tabla->mbhc_cfg.mclk_cb_fn(codec, 1, false);
  7236. tabla_mbhc_init(codec);
  7237. tabla_mbhc_cal(codec);
  7238. tabla_mbhc_calc_thres(codec);
  7239. tabla->mbhc_cfg.mclk_cb_fn(codec, 0, false);
  7240. tabla_codec_calibrate_hs_polling(codec);
  7241. if (!tabla->mbhc_cfg.gpio) {
  7242. INIT_WORK(&tabla->hs_correct_plug_work_nogpio,
  7243. tabla_hs_correct_plug_nogpio);
  7244. ret = tabla_codec_enable_hs_detect(codec, 1,
  7245. MBHC_USE_MB_TRIGGER |
  7246. MBHC_USE_HPHL_TRIGGER,
  7247. false);
  7248. if (IS_ERR_VALUE(ret))
  7249. pr_err("%s: Failed to setup MBHC detection\n",
  7250. __func__);
  7251. } else {
  7252. /* Enable Mic Bias pull down and HPH Switch to GND */
  7253. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.ctl_reg,
  7254. 0x01, 0x01);
  7255. snd_soc_update_bits(codec, TABLA_A_MBHC_HPH, 0x01, 0x01);
  7256. INIT_WORK(&tabla->hs_correct_plug_work,
  7257. tabla_hs_correct_gpio_plug);
  7258. }
  7259. if (!IS_ERR_VALUE(ret)) {
  7260. snd_soc_update_bits(codec, TABLA_A_RX_HPH_OCP_CTL, 0x10, 0x10);
  7261. wcd9xxx_enable_irq(codec->control_data,
  7262. WCD9XXX_IRQ_HPH_PA_OCPL_FAULT);
  7263. wcd9xxx_enable_irq(codec->control_data,
  7264. WCD9XXX_IRQ_HPH_PA_OCPR_FAULT);
  7265. if (tabla->mbhc_cfg.gpio) {
  7266. ret = request_threaded_irq(tabla->mbhc_cfg.gpio_irq,
  7267. NULL,
  7268. tabla_mechanical_plug_detect_irq,
  7269. (IRQF_TRIGGER_RISING |
  7270. IRQF_TRIGGER_FALLING),
  7271. "tabla-gpio", codec);
  7272. if (!IS_ERR_VALUE(ret)) {
  7273. ret = enable_irq_wake(tabla->mbhc_cfg.gpio_irq);
  7274. /* Bootup time detection */
  7275. tabla_hs_gpio_handler(codec);
  7276. }
  7277. }
  7278. }
  7279. return ret;
  7280. }
  7281. static void mbhc_fw_read(struct work_struct *work)
  7282. {
  7283. struct delayed_work *dwork;
  7284. struct tabla_priv *tabla;
  7285. struct snd_soc_codec *codec;
  7286. const struct firmware *fw;
  7287. int ret = -1, retry = 0;
  7288. dwork = to_delayed_work(work);
  7289. tabla = container_of(dwork, struct tabla_priv, mbhc_firmware_dwork);
  7290. codec = tabla->codec;
  7291. while (retry < MBHC_FW_READ_ATTEMPTS) {
  7292. retry++;
  7293. pr_info("%s:Attempt %d to request MBHC firmware\n",
  7294. __func__, retry);
  7295. ret = request_firmware(&fw, "wcd9310/wcd9310_mbhc.bin",
  7296. codec->dev);
  7297. if (ret != 0) {
  7298. usleep_range(MBHC_FW_READ_TIMEOUT,
  7299. MBHC_FW_READ_TIMEOUT);
  7300. } else {
  7301. pr_info("%s: MBHC Firmware read succesful\n", __func__);
  7302. break;
  7303. }
  7304. }
  7305. if (ret != 0) {
  7306. pr_err("%s: Cannot load MBHC firmware use default cal\n",
  7307. __func__);
  7308. } else if (tabla_mbhc_fw_validate(fw) == false) {
  7309. pr_err("%s: Invalid MBHC cal data size use default cal\n",
  7310. __func__);
  7311. release_firmware(fw);
  7312. } else {
  7313. tabla->mbhc_cfg.calibration = (void *)fw->data;
  7314. tabla->mbhc_fw = fw;
  7315. }
  7316. (void) tabla_mbhc_init_and_calibrate(tabla);
  7317. }
  7318. int tabla_hs_detect(struct snd_soc_codec *codec,
  7319. const struct tabla_mbhc_config *cfg)
  7320. {
  7321. struct tabla_priv *tabla;
  7322. int rc = 0;
  7323. if (!codec || !cfg->calibration) {
  7324. pr_err("Error: no codec or calibration\n");
  7325. return -EINVAL;
  7326. }
  7327. if (cfg->mclk_rate != TABLA_MCLK_RATE_12288KHZ) {
  7328. if (cfg->mclk_rate == TABLA_MCLK_RATE_9600KHZ)
  7329. pr_err("Error: clock rate %dHz is not yet supported\n",
  7330. cfg->mclk_rate);
  7331. else
  7332. pr_err("Error: unsupported clock rate %d\n",
  7333. cfg->mclk_rate);
  7334. return -EINVAL;
  7335. }
  7336. tabla = snd_soc_codec_get_drvdata(codec);
  7337. tabla->mbhc_cfg = *cfg;
  7338. tabla->in_gpio_handler = false;
  7339. tabla->current_plug = PLUG_TYPE_NONE;
  7340. tabla->lpi_enabled = false;
  7341. tabla_get_mbhc_micbias_regs(codec, &tabla->mbhc_bias_regs);
  7342. /* Put CFILT in fast mode by default */
  7343. if (!tabla->mbhc_cfg.micbias_always_on)
  7344. snd_soc_update_bits(codec, tabla->mbhc_bias_regs.cfilt_ctl,
  7345. 0x40, TABLA_CFILT_FAST_MODE);
  7346. INIT_DELAYED_WORK(&tabla->mbhc_firmware_dwork, mbhc_fw_read);
  7347. INIT_DELAYED_WORK(&tabla->mbhc_btn_dwork, btn_lpress_fn);
  7348. INIT_WORK(&tabla->hphlocp_work, hphlocp_off_report);
  7349. INIT_WORK(&tabla->hphrocp_work, hphrocp_off_report);
  7350. INIT_DELAYED_WORK(&tabla->mbhc_insert_dwork, mbhc_insert_work);
  7351. if (!tabla->mbhc_cfg.read_fw_bin)
  7352. rc = tabla_mbhc_init_and_calibrate(tabla);
  7353. else
  7354. schedule_delayed_work(&tabla->mbhc_firmware_dwork,
  7355. usecs_to_jiffies(MBHC_FW_READ_TIMEOUT));
  7356. return rc;
  7357. }
  7358. EXPORT_SYMBOL_GPL(tabla_hs_detect);
  7359. static irqreturn_t tabla_slimbus_irq(int irq, void *data)
  7360. {
  7361. struct tabla_priv *priv = data;
  7362. struct snd_soc_codec *codec = priv->codec;
  7363. struct tabla_priv *tabla_p = snd_soc_codec_get_drvdata(codec);
  7364. int i, j, port_id, k, ch_mask_temp;
  7365. unsigned long slimbus_value;
  7366. u8 val;
  7367. for (i = 0; i < WCD9XXX_SLIM_NUM_PORT_REG; i++) {
  7368. slimbus_value = wcd9xxx_interface_reg_read(codec->control_data,
  7369. TABLA_SLIM_PGD_PORT_INT_STATUS0 + i);
  7370. for_each_set_bit(j, &slimbus_value, BITS_PER_BYTE) {
  7371. val = wcd9xxx_interface_reg_read(codec->control_data,
  7372. TABLA_SLIM_PGD_PORT_INT_SOURCE0 + i*8 + j);
  7373. if (val & 0x1)
  7374. pr_err_ratelimited("overflow error on port %x,"
  7375. " value %x\n", i*8 + j, val);
  7376. if (val & 0x2)
  7377. pr_err_ratelimited("underflow error on port %x,"
  7378. " value %x\n", i*8 + j, val);
  7379. if (val & 0x4) {
  7380. port_id = i*8 + j;
  7381. for (k = 0; k < ARRAY_SIZE(tabla_dai); k++) {
  7382. ch_mask_temp = 1 << port_id;
  7383. pr_debug("%s: tabla_p->dai[%d].ch_mask = 0x%lx\n",
  7384. __func__, k,
  7385. tabla_p->dai[k].ch_mask);
  7386. if (ch_mask_temp &
  7387. tabla_p->dai[k].ch_mask) {
  7388. tabla_p->dai[k].ch_mask &=
  7389. ~ch_mask_temp;
  7390. if (!tabla_p->dai[k].ch_mask)
  7391. wake_up(
  7392. &tabla_p->dai[k].dai_wait);
  7393. }
  7394. }
  7395. }
  7396. }
  7397. wcd9xxx_interface_reg_write(codec->control_data,
  7398. TABLA_SLIM_PGD_PORT_INT_CLR0 + i, slimbus_value);
  7399. val = 0x0;
  7400. }
  7401. return IRQ_HANDLED;
  7402. }
  7403. static int tabla_handle_pdata(struct tabla_priv *tabla)
  7404. {
  7405. struct snd_soc_codec *codec = tabla->codec;
  7406. struct wcd9xxx_pdata *pdata = tabla->pdata;
  7407. int k1, k2, k3, rc = 0;
  7408. u8 leg_mode = pdata->amic_settings.legacy_mode;
  7409. u8 txfe_bypass = pdata->amic_settings.txfe_enable;
  7410. u8 txfe_buff = pdata->amic_settings.txfe_buff;
  7411. u8 flag = pdata->amic_settings.use_pdata;
  7412. u8 i = 0, j = 0;
  7413. u8 val_txfe = 0, value = 0;
  7414. if (!pdata) {
  7415. rc = -ENODEV;
  7416. goto done;
  7417. }
  7418. /* Make sure settings are correct */
  7419. if ((pdata->micbias.ldoh_v > TABLA_LDOH_2P85_V) ||
  7420. (pdata->micbias.bias1_cfilt_sel > TABLA_CFILT3_SEL) ||
  7421. (pdata->micbias.bias2_cfilt_sel > TABLA_CFILT3_SEL) ||
  7422. (pdata->micbias.bias3_cfilt_sel > TABLA_CFILT3_SEL) ||
  7423. (pdata->micbias.bias4_cfilt_sel > TABLA_CFILT3_SEL)) {
  7424. rc = -EINVAL;
  7425. goto done;
  7426. }
  7427. /* figure out k value */
  7428. k1 = tabla_find_k_value(pdata->micbias.ldoh_v,
  7429. pdata->micbias.cfilt1_mv);
  7430. k2 = tabla_find_k_value(pdata->micbias.ldoh_v,
  7431. pdata->micbias.cfilt2_mv);
  7432. k3 = tabla_find_k_value(pdata->micbias.ldoh_v,
  7433. pdata->micbias.cfilt3_mv);
  7434. if (IS_ERR_VALUE(k1) || IS_ERR_VALUE(k2) || IS_ERR_VALUE(k3)) {
  7435. rc = -EINVAL;
  7436. goto done;
  7437. }
  7438. /* Set voltage level and always use LDO */
  7439. snd_soc_update_bits(codec, TABLA_A_LDO_H_MODE_1, 0x0C,
  7440. (pdata->micbias.ldoh_v << 2));
  7441. snd_soc_update_bits(codec, TABLA_A_MICB_CFILT_1_VAL, 0xFC,
  7442. (k1 << 2));
  7443. snd_soc_update_bits(codec, TABLA_A_MICB_CFILT_2_VAL, 0xFC,
  7444. (k2 << 2));
  7445. snd_soc_update_bits(codec, TABLA_A_MICB_CFILT_3_VAL, 0xFC,
  7446. (k3 << 2));
  7447. snd_soc_update_bits(codec, TABLA_A_MICB_1_CTL, 0x60,
  7448. (pdata->micbias.bias1_cfilt_sel << 5));
  7449. snd_soc_update_bits(codec, TABLA_A_MICB_2_CTL, 0x60,
  7450. (pdata->micbias.bias2_cfilt_sel << 5));
  7451. snd_soc_update_bits(codec, TABLA_A_MICB_3_CTL, 0x60,
  7452. (pdata->micbias.bias3_cfilt_sel << 5));
  7453. snd_soc_update_bits(codec, tabla->reg_addr.micb_4_ctl, 0x60,
  7454. (pdata->micbias.bias4_cfilt_sel << 5));
  7455. for (i = 0; i < 6; j++, i += 2) {
  7456. if (flag & (0x01 << i)) {
  7457. value = (leg_mode & (0x01 << i)) ? 0x10 : 0x00;
  7458. val_txfe = (txfe_bypass & (0x01 << i)) ? 0x20 : 0x00;
  7459. val_txfe = val_txfe |
  7460. ((txfe_buff & (0x01 << i)) ? 0x10 : 0x00);
  7461. snd_soc_update_bits(codec, TABLA_A_TX_1_2_EN + j * 10,
  7462. 0x10, value);
  7463. snd_soc_update_bits(codec,
  7464. TABLA_A_TX_1_2_TEST_EN + j * 10,
  7465. 0x30, val_txfe);
  7466. }
  7467. if (flag & (0x01 << (i + 1))) {
  7468. value = (leg_mode & (0x01 << (i + 1))) ? 0x01 : 0x00;
  7469. val_txfe = (txfe_bypass &
  7470. (0x01 << (i + 1))) ? 0x02 : 0x00;
  7471. val_txfe |= (txfe_buff &
  7472. (0x01 << (i + 1))) ? 0x01 : 0x00;
  7473. snd_soc_update_bits(codec, TABLA_A_TX_1_2_EN + j * 10,
  7474. 0x01, value);
  7475. snd_soc_update_bits(codec,
  7476. TABLA_A_TX_1_2_TEST_EN + j * 10,
  7477. 0x03, val_txfe);
  7478. }
  7479. }
  7480. if (flag & 0x40) {
  7481. value = (leg_mode & 0x40) ? 0x10 : 0x00;
  7482. value = value | ((txfe_bypass & 0x40) ? 0x02 : 0x00);
  7483. value = value | ((txfe_buff & 0x40) ? 0x01 : 0x00);
  7484. snd_soc_update_bits(codec, TABLA_A_TX_7_MBHC_EN,
  7485. 0x13, value);
  7486. }
  7487. if (pdata->ocp.use_pdata) {
  7488. /* not defined in CODEC specification */
  7489. if (pdata->ocp.hph_ocp_limit == 1 ||
  7490. pdata->ocp.hph_ocp_limit == 5) {
  7491. rc = -EINVAL;
  7492. goto done;
  7493. }
  7494. snd_soc_update_bits(codec, TABLA_A_RX_COM_OCP_CTL,
  7495. 0x0F, pdata->ocp.num_attempts);
  7496. snd_soc_write(codec, TABLA_A_RX_COM_OCP_COUNT,
  7497. ((pdata->ocp.run_time << 4) | pdata->ocp.wait_time));
  7498. snd_soc_update_bits(codec, TABLA_A_RX_HPH_OCP_CTL,
  7499. 0xE0, (pdata->ocp.hph_ocp_limit << 5));
  7500. }
  7501. for (i = 0; i < ARRAY_SIZE(pdata->regulator); i++) {
  7502. if (!strncmp(pdata->regulator[i].name, "CDC_VDDA_RX", 11)) {
  7503. if (pdata->regulator[i].min_uV == 1800000 &&
  7504. pdata->regulator[i].max_uV == 1800000) {
  7505. snd_soc_write(codec, TABLA_A_BIAS_REF_CTL,
  7506. 0x1C);
  7507. } else if (pdata->regulator[i].min_uV == 2200000 &&
  7508. pdata->regulator[i].max_uV == 2200000) {
  7509. snd_soc_write(codec, TABLA_A_BIAS_REF_CTL,
  7510. 0x1E);
  7511. } else {
  7512. pr_err("%s: unsupported CDC_VDDA_RX voltage "
  7513. "min %d, max %d\n", __func__,
  7514. pdata->regulator[i].min_uV,
  7515. pdata->regulator[i].max_uV);
  7516. rc = -EINVAL;
  7517. }
  7518. break;
  7519. }
  7520. }
  7521. done:
  7522. return rc;
  7523. }
  7524. static const struct tabla_reg_mask_val tabla_1_1_reg_defaults[] = {
  7525. /* Tabla 1.1 MICBIAS changes */
  7526. TABLA_REG_VAL(TABLA_A_MICB_1_INT_RBIAS, 0x24),
  7527. TABLA_REG_VAL(TABLA_A_MICB_2_INT_RBIAS, 0x24),
  7528. TABLA_REG_VAL(TABLA_A_MICB_3_INT_RBIAS, 0x24),
  7529. /* Tabla 1.1 HPH changes */
  7530. TABLA_REG_VAL(TABLA_A_RX_HPH_BIAS_PA, 0x57),
  7531. TABLA_REG_VAL(TABLA_A_RX_HPH_BIAS_LDO, 0x56),
  7532. /* Tabla 1.1 EAR PA changes */
  7533. TABLA_REG_VAL(TABLA_A_RX_EAR_BIAS_PA, 0xA6),
  7534. TABLA_REG_VAL(TABLA_A_RX_EAR_GAIN, 0x02),
  7535. TABLA_REG_VAL(TABLA_A_RX_EAR_VCM, 0x03),
  7536. /* Tabla 1.1 Lineout_5 Changes */
  7537. TABLA_REG_VAL(TABLA_A_RX_LINE_5_GAIN, 0x10),
  7538. /* Tabla 1.1 RX Changes */
  7539. TABLA_REG_VAL(TABLA_A_CDC_RX1_B5_CTL, 0x78),
  7540. TABLA_REG_VAL(TABLA_A_CDC_RX2_B5_CTL, 0x78),
  7541. TABLA_REG_VAL(TABLA_A_CDC_RX3_B5_CTL, 0x78),
  7542. TABLA_REG_VAL(TABLA_A_CDC_RX4_B5_CTL, 0x78),
  7543. TABLA_REG_VAL(TABLA_A_CDC_RX5_B5_CTL, 0x78),
  7544. TABLA_REG_VAL(TABLA_A_CDC_RX6_B5_CTL, 0x78),
  7545. TABLA_REG_VAL(TABLA_A_CDC_RX7_B5_CTL, 0x78),
  7546. /* Tabla 1.1 RX1 and RX2 Changes */
  7547. TABLA_REG_VAL(TABLA_A_CDC_RX1_B6_CTL, 0xA0),
  7548. TABLA_REG_VAL(TABLA_A_CDC_RX2_B6_CTL, 0xA0),
  7549. /* Tabla 1.1 RX3 to RX7 Changes */
  7550. TABLA_REG_VAL(TABLA_A_CDC_RX3_B6_CTL, 0x80),
  7551. TABLA_REG_VAL(TABLA_A_CDC_RX4_B6_CTL, 0x80),
  7552. TABLA_REG_VAL(TABLA_A_CDC_RX5_B6_CTL, 0x80),
  7553. TABLA_REG_VAL(TABLA_A_CDC_RX6_B6_CTL, 0x80),
  7554. TABLA_REG_VAL(TABLA_A_CDC_RX7_B6_CTL, 0x80),
  7555. /* Tabla 1.1 CLASSG Changes */
  7556. TABLA_REG_VAL(TABLA_A_CDC_CLSG_FREQ_THRESH_B3_CTL, 0x1B),
  7557. };
  7558. static const struct tabla_reg_mask_val tabla_2_0_reg_defaults[] = {
  7559. /* Tabla 2.0 MICBIAS changes */
  7560. TABLA_REG_VAL(TABLA_A_MICB_2_MBHC, 0x02),
  7561. };
  7562. static const struct tabla_reg_mask_val tabla_1_x_only_reg_2_0_defaults[] = {
  7563. TABLA_REG_VAL(TABLA_1_A_MICB_4_INT_RBIAS, 0x24),
  7564. };
  7565. static const struct tabla_reg_mask_val tabla_2_only_reg_2_0_defaults[] = {
  7566. TABLA_REG_VAL(TABLA_2_A_MICB_4_INT_RBIAS, 0x24),
  7567. };
  7568. static void tabla_update_reg_defaults(struct snd_soc_codec *codec)
  7569. {
  7570. u32 i;
  7571. struct wcd9xxx *tabla_core = dev_get_drvdata(codec->dev->parent);
  7572. for (i = 0; i < ARRAY_SIZE(tabla_1_1_reg_defaults); i++)
  7573. snd_soc_write(codec, tabla_1_1_reg_defaults[i].reg,
  7574. tabla_1_1_reg_defaults[i].val);
  7575. for (i = 0; i < ARRAY_SIZE(tabla_2_0_reg_defaults); i++)
  7576. snd_soc_write(codec, tabla_2_0_reg_defaults[i].reg,
  7577. tabla_2_0_reg_defaults[i].val);
  7578. if (TABLA_IS_1_X(tabla_core->version)) {
  7579. for (i = 0; i < ARRAY_SIZE(tabla_1_x_only_reg_2_0_defaults);
  7580. i++)
  7581. snd_soc_write(codec,
  7582. tabla_1_x_only_reg_2_0_defaults[i].reg,
  7583. tabla_1_x_only_reg_2_0_defaults[i].val);
  7584. } else {
  7585. for (i = 0; i < ARRAY_SIZE(tabla_2_only_reg_2_0_defaults); i++)
  7586. snd_soc_write(codec,
  7587. tabla_2_only_reg_2_0_defaults[i].reg,
  7588. tabla_2_only_reg_2_0_defaults[i].val);
  7589. }
  7590. }
  7591. static const struct tabla_reg_mask_val tabla_codec_reg_init_val[] = {
  7592. /* Initialize current threshold to 350MA
  7593. * number of wait and run cycles to 4096
  7594. */
  7595. {TABLA_A_RX_HPH_OCP_CTL, 0xE0, 0x60},
  7596. {TABLA_A_RX_COM_OCP_COUNT, 0xFF, 0xFF},
  7597. {TABLA_A_QFUSE_CTL, 0xFF, 0x03},
  7598. /* Initialize gain registers to use register gain */
  7599. {TABLA_A_RX_HPH_L_GAIN, 0x10, 0x10},
  7600. {TABLA_A_RX_HPH_R_GAIN, 0x10, 0x10},
  7601. {TABLA_A_RX_LINE_1_GAIN, 0x10, 0x10},
  7602. {TABLA_A_RX_LINE_2_GAIN, 0x10, 0x10},
  7603. {TABLA_A_RX_LINE_3_GAIN, 0x10, 0x10},
  7604. {TABLA_A_RX_LINE_4_GAIN, 0x10, 0x10},
  7605. /* Set the MICBIAS default output as pull down*/
  7606. {TABLA_A_MICB_1_CTL, 0x01, 0x01},
  7607. {TABLA_A_MICB_2_CTL, 0x01, 0x01},
  7608. {TABLA_A_MICB_3_CTL, 0x01, 0x01},
  7609. /* Initialize mic biases to differential mode */
  7610. {TABLA_A_MICB_1_INT_RBIAS, 0x24, 0x24},
  7611. {TABLA_A_MICB_2_INT_RBIAS, 0x24, 0x24},
  7612. {TABLA_A_MICB_3_INT_RBIAS, 0x24, 0x24},
  7613. {TABLA_A_CDC_CONN_CLSG_CTL, 0x3C, 0x14},
  7614. /* Use 16 bit sample size for TX1 to TX6 */
  7615. {TABLA_A_CDC_CONN_TX_SB_B1_CTL, 0x30, 0x20},
  7616. {TABLA_A_CDC_CONN_TX_SB_B2_CTL, 0x30, 0x20},
  7617. {TABLA_A_CDC_CONN_TX_SB_B3_CTL, 0x30, 0x20},
  7618. {TABLA_A_CDC_CONN_TX_SB_B4_CTL, 0x30, 0x20},
  7619. {TABLA_A_CDC_CONN_TX_SB_B5_CTL, 0x30, 0x20},
  7620. {TABLA_A_CDC_CONN_TX_SB_B6_CTL, 0x30, 0x20},
  7621. /* Use 16 bit sample size for TX7 to TX10 */
  7622. {TABLA_A_CDC_CONN_TX_SB_B7_CTL, 0x60, 0x40},
  7623. {TABLA_A_CDC_CONN_TX_SB_B8_CTL, 0x60, 0x40},
  7624. {TABLA_A_CDC_CONN_TX_SB_B9_CTL, 0x60, 0x40},
  7625. {TABLA_A_CDC_CONN_TX_SB_B10_CTL, 0x60, 0x40},
  7626. /* Use 16 bit sample size for RX */
  7627. {TABLA_A_CDC_CONN_RX_SB_B1_CTL, 0xFF, 0xAA},
  7628. {TABLA_A_CDC_CONN_RX_SB_B2_CTL, 0xFF, 0xAA},
  7629. /*enable HPF filter for TX paths */
  7630. {TABLA_A_CDC_TX1_MUX_CTL, 0x8, 0x0},
  7631. {TABLA_A_CDC_TX2_MUX_CTL, 0x8, 0x0},
  7632. {TABLA_A_CDC_TX3_MUX_CTL, 0x8, 0x0},
  7633. {TABLA_A_CDC_TX4_MUX_CTL, 0x8, 0x0},
  7634. {TABLA_A_CDC_TX5_MUX_CTL, 0x8, 0x0},
  7635. {TABLA_A_CDC_TX6_MUX_CTL, 0x8, 0x0},
  7636. {TABLA_A_CDC_TX7_MUX_CTL, 0x8, 0x0},
  7637. {TABLA_A_CDC_TX8_MUX_CTL, 0x8, 0x0},
  7638. {TABLA_A_CDC_TX9_MUX_CTL, 0x8, 0x0},
  7639. {TABLA_A_CDC_TX10_MUX_CTL, 0x8, 0x0},
  7640. /* config Decimator for DMIC CLK_MODE_1(3.072Mhz@12.88Mhz mclk) */
  7641. {TABLA_A_CDC_TX1_DMIC_CTL, 0x1, 0x1},
  7642. {TABLA_A_CDC_TX2_DMIC_CTL, 0x1, 0x1},
  7643. {TABLA_A_CDC_TX3_DMIC_CTL, 0x1, 0x1},
  7644. {TABLA_A_CDC_TX4_DMIC_CTL, 0x1, 0x1},
  7645. {TABLA_A_CDC_TX5_DMIC_CTL, 0x1, 0x1},
  7646. {TABLA_A_CDC_TX6_DMIC_CTL, 0x1, 0x1},
  7647. {TABLA_A_CDC_TX7_DMIC_CTL, 0x1, 0x1},
  7648. {TABLA_A_CDC_TX8_DMIC_CTL, 0x1, 0x1},
  7649. {TABLA_A_CDC_TX9_DMIC_CTL, 0x1, 0x1},
  7650. {TABLA_A_CDC_TX10_DMIC_CTL, 0x1, 0x1},
  7651. /* config DMIC clk to CLK_MODE_1 (3.072Mhz@12.88Mhz mclk) */
  7652. {TABLA_A_CDC_CLK_DMIC_CTL, 0x2A, 0x2A},
  7653. };
  7654. static const struct tabla_reg_mask_val tabla_1_x_codec_reg_init_val[] = {
  7655. /* Set the MICBIAS default output as pull down*/
  7656. {TABLA_1_A_MICB_4_CTL, 0x01, 0x01},
  7657. /* Initialize mic biases to differential mode */
  7658. {TABLA_1_A_MICB_4_INT_RBIAS, 0x24, 0x24},
  7659. };
  7660. static const struct tabla_reg_mask_val tabla_2_higher_codec_reg_init_val[] = {
  7661. /* Set the MICBIAS default output as pull down*/
  7662. {TABLA_2_A_MICB_4_CTL, 0x01, 0x01},
  7663. /* Initialize mic biases to differential mode */
  7664. {TABLA_2_A_MICB_4_INT_RBIAS, 0x24, 0x24},
  7665. };
  7666. static void tabla_codec_init_reg(struct snd_soc_codec *codec)
  7667. {
  7668. u32 i;
  7669. struct wcd9xxx *tabla_core = dev_get_drvdata(codec->dev->parent);
  7670. for (i = 0; i < ARRAY_SIZE(tabla_codec_reg_init_val); i++)
  7671. snd_soc_update_bits(codec, tabla_codec_reg_init_val[i].reg,
  7672. tabla_codec_reg_init_val[i].mask,
  7673. tabla_codec_reg_init_val[i].val);
  7674. if (TABLA_IS_1_X(tabla_core->version)) {
  7675. for (i = 0; i < ARRAY_SIZE(tabla_1_x_codec_reg_init_val); i++)
  7676. snd_soc_update_bits(codec,
  7677. tabla_1_x_codec_reg_init_val[i].reg,
  7678. tabla_1_x_codec_reg_init_val[i].mask,
  7679. tabla_1_x_codec_reg_init_val[i].val);
  7680. } else {
  7681. for (i = 0; i < ARRAY_SIZE(tabla_2_higher_codec_reg_init_val);
  7682. i++)
  7683. snd_soc_update_bits(codec,
  7684. tabla_2_higher_codec_reg_init_val[i].reg,
  7685. tabla_2_higher_codec_reg_init_val[i].mask,
  7686. tabla_2_higher_codec_reg_init_val[i].val);
  7687. }
  7688. snd_soc_update_bits(codec, TABLA_A_CDC_DMIC_CLK0_MODE, 0x7, 0x4);
  7689. snd_soc_update_bits(codec, TABLA_A_CDC_DMIC_CLK1_MODE, 0x7, 0x4);
  7690. snd_soc_update_bits(codec, TABLA_A_CDC_DMIC_CLK2_MODE, 0x7, 0x4);
  7691. snd_soc_update_bits(codec, TABLA_A_PIN_CTL_OE0, 0x90, 0x90);
  7692. snd_soc_update_bits(codec, TABLA_A_PIN_CTL_OE1, 0x8, 0x8);
  7693. snd_soc_update_bits(codec, TABLA_A_PIN_CTL_DATA0, 0x90, 0x0);
  7694. snd_soc_update_bits(codec, TABLA_A_PIN_CTL_DATA1, 0x8, 0x0);
  7695. }
  7696. static void tabla_update_reg_address(struct tabla_priv *priv)
  7697. {
  7698. struct wcd9xxx *tabla_core = dev_get_drvdata(priv->codec->dev->parent);
  7699. struct tabla_reg_address *reg_addr = &priv->reg_addr;
  7700. if (TABLA_IS_1_X(tabla_core->version)) {
  7701. reg_addr->micb_4_mbhc = TABLA_1_A_MICB_4_MBHC;
  7702. reg_addr->micb_4_int_rbias = TABLA_1_A_MICB_4_INT_RBIAS;
  7703. reg_addr->micb_4_ctl = TABLA_1_A_MICB_4_CTL;
  7704. } else if (TABLA_IS_2_0(tabla_core->version)) {
  7705. reg_addr->micb_4_mbhc = TABLA_2_A_MICB_4_MBHC;
  7706. reg_addr->micb_4_int_rbias = TABLA_2_A_MICB_4_INT_RBIAS;
  7707. reg_addr->micb_4_ctl = TABLA_2_A_MICB_4_CTL;
  7708. }
  7709. }
  7710. #ifdef CONFIG_DEBUG_FS
  7711. static int codec_debug_open(struct inode *inode, struct file *file)
  7712. {
  7713. file->private_data = inode->i_private;
  7714. return 0;
  7715. }
  7716. static ssize_t codec_debug_write(struct file *filp,
  7717. const char __user *ubuf, size_t cnt, loff_t *ppos)
  7718. {
  7719. char lbuf[32];
  7720. char *buf;
  7721. int rc;
  7722. struct tabla_priv *tabla = filp->private_data;
  7723. if (cnt > sizeof(lbuf) - 1)
  7724. return -EINVAL;
  7725. rc = copy_from_user(lbuf, ubuf, cnt);
  7726. if (rc)
  7727. return -EFAULT;
  7728. lbuf[cnt] = '\0';
  7729. buf = (char *)lbuf;
  7730. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  7731. tabla->no_mic_headset_override =
  7732. (*strsep(&buf, " ") == '0') ? false : true;
  7733. if (tabla->no_mic_headset_override && tabla->mbhc_polling_active) {
  7734. tabla_codec_pause_hs_polling(tabla->codec);
  7735. tabla_codec_start_hs_polling(tabla->codec);
  7736. }
  7737. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  7738. return cnt;
  7739. }
  7740. static ssize_t codec_mbhc_debug_read(struct file *file, char __user *buf,
  7741. size_t count, loff_t *pos)
  7742. {
  7743. const int size = 768;
  7744. char buffer[size];
  7745. int n = 0;
  7746. struct tabla_priv *tabla = file->private_data;
  7747. struct snd_soc_codec *codec = tabla->codec;
  7748. const struct mbhc_internal_cal_data *p = &tabla->mbhc_data;
  7749. const s16 v_ins_hu_cur = tabla_get_current_v_ins(tabla, true);
  7750. const s16 v_ins_h_cur = tabla_get_current_v_ins(tabla, false);
  7751. n = scnprintf(buffer, size - n, "dce_z = %x(%dmv)\n", p->dce_z,
  7752. tabla_codec_sta_dce_v(codec, 1, p->dce_z));
  7753. n += scnprintf(buffer + n, size - n, "dce_mb = %x(%dmv)\n",
  7754. p->dce_mb, tabla_codec_sta_dce_v(codec, 1, p->dce_mb));
  7755. n += scnprintf(buffer + n, size - n, "sta_z = %x(%dmv)\n",
  7756. p->sta_z, tabla_codec_sta_dce_v(codec, 0, p->sta_z));
  7757. n += scnprintf(buffer + n, size - n, "sta_mb = %x(%dmv)\n",
  7758. p->sta_mb, tabla_codec_sta_dce_v(codec, 0, p->sta_mb));
  7759. n += scnprintf(buffer + n, size - n, "t_dce = %x\n", p->t_dce);
  7760. n += scnprintf(buffer + n, size - n, "t_sta = %x\n", p->t_sta);
  7761. n += scnprintf(buffer + n, size - n, "micb_mv = %dmv\n",
  7762. p->micb_mv);
  7763. n += scnprintf(buffer + n, size - n, "v_ins_hu = %x(%dmv)%s\n",
  7764. p->v_ins_hu,
  7765. tabla_codec_sta_dce_v(codec, 0, p->v_ins_hu),
  7766. p->v_ins_hu == v_ins_hu_cur ? "*" : "");
  7767. n += scnprintf(buffer + n, size - n, "v_ins_h = %x(%dmv)%s\n",
  7768. p->v_ins_h, tabla_codec_sta_dce_v(codec, 1, p->v_ins_h),
  7769. p->v_ins_h == v_ins_h_cur ? "*" : "");
  7770. n += scnprintf(buffer + n, size - n, "adj_v_ins_hu = %x(%dmv)%s\n",
  7771. p->adj_v_ins_hu,
  7772. tabla_codec_sta_dce_v(codec, 0, p->adj_v_ins_hu),
  7773. p->adj_v_ins_hu == v_ins_hu_cur ? "*" : "");
  7774. n += scnprintf(buffer + n, size - n, "adj_v_ins_h = %x(%dmv)%s\n",
  7775. p->adj_v_ins_h,
  7776. tabla_codec_sta_dce_v(codec, 1, p->adj_v_ins_h),
  7777. p->adj_v_ins_h == v_ins_h_cur ? "*" : "");
  7778. n += scnprintf(buffer + n, size - n, "v_b1_hu = %x(%dmv)\n",
  7779. p->v_b1_hu, tabla_codec_sta_dce_v(codec, 0, p->v_b1_hu));
  7780. n += scnprintf(buffer + n, size - n, "v_b1_h = %x(%dmv)\n",
  7781. p->v_b1_h, tabla_codec_sta_dce_v(codec, 1, p->v_b1_h));
  7782. n += scnprintf(buffer + n, size - n, "v_b1_huc = %x(%dmv)\n",
  7783. p->v_b1_huc,
  7784. tabla_codec_sta_dce_v(codec, 1, p->v_b1_huc));
  7785. n += scnprintf(buffer + n, size - n, "v_brh = %x(%dmv)\n",
  7786. p->v_brh, tabla_codec_sta_dce_v(codec, 1, p->v_brh));
  7787. n += scnprintf(buffer + n, size - n, "v_brl = %x(%dmv)\n", p->v_brl,
  7788. tabla_codec_sta_dce_v(codec, 0, p->v_brl));
  7789. n += scnprintf(buffer + n, size - n, "v_no_mic = %x(%dmv)\n",
  7790. p->v_no_mic,
  7791. tabla_codec_sta_dce_v(codec, 0, p->v_no_mic));
  7792. n += scnprintf(buffer + n, size - n, "npoll = %d\n", p->npoll);
  7793. n += scnprintf(buffer + n, size - n, "nbounce_wait = %d\n",
  7794. p->nbounce_wait);
  7795. n += scnprintf(buffer + n, size - n, "v_inval_ins_low = %d\n",
  7796. p->v_inval_ins_low);
  7797. n += scnprintf(buffer + n, size - n, "v_inval_ins_high = %d\n",
  7798. p->v_inval_ins_high);
  7799. if (tabla->mbhc_cfg.gpio)
  7800. n += scnprintf(buffer + n, size - n, "GPIO insert = %d\n",
  7801. tabla_hs_gpio_level_remove(tabla));
  7802. buffer[n] = 0;
  7803. return simple_read_from_buffer(buf, count, pos, buffer, n);
  7804. }
  7805. static const struct file_operations codec_debug_ops = {
  7806. .open = codec_debug_open,
  7807. .write = codec_debug_write,
  7808. };
  7809. static const struct file_operations codec_mbhc_debug_ops = {
  7810. .open = codec_debug_open,
  7811. .read = codec_mbhc_debug_read,
  7812. };
  7813. #endif
  7814. static int tabla_codec_probe(struct snd_soc_codec *codec)
  7815. {
  7816. struct wcd9xxx *control;
  7817. struct tabla_priv *tabla;
  7818. struct snd_soc_dapm_context *dapm = &codec->dapm;
  7819. int ret = 0;
  7820. int i;
  7821. void *ptr = NULL;
  7822. struct wcd9xxx_core_resource *core_res;
  7823. codec->control_data = dev_get_drvdata(codec->dev->parent);
  7824. control = codec->control_data;
  7825. core_res = &control->core_res;
  7826. tabla = kzalloc(sizeof(struct tabla_priv), GFP_KERNEL);
  7827. if (!tabla) {
  7828. dev_err(codec->dev, "Failed to allocate private data\n");
  7829. return -ENOMEM;
  7830. }
  7831. for (i = 0 ; i < NUM_DECIMATORS; i++) {
  7832. tx_mute_work[i].tabla = tx_hpf_work[i].tabla = tabla;
  7833. tx_mute_work[i].decimator = tx_hpf_work[i].decimator = i + 1;
  7834. INIT_DELAYED_WORK(&tx_hpf_work[i].dwork,
  7835. tx_hpf_corner_freq_callback);
  7836. INIT_DELAYED_WORK(&tx_mute_work[i].dwork,
  7837. tx_digital_unmute_callback);
  7838. }
  7839. /* Make sure mbhc micbias register addresses are zeroed out */
  7840. memset(&tabla->mbhc_bias_regs, 0,
  7841. sizeof(struct mbhc_micbias_regs));
  7842. tabla->mbhc_micbias_switched = false;
  7843. /* Make sure mbhc intenal calibration data is zeroed out */
  7844. memset(&tabla->mbhc_data, 0,
  7845. sizeof(struct mbhc_internal_cal_data));
  7846. tabla->mbhc_data.t_sta_dce = DEFAULT_DCE_STA_WAIT;
  7847. tabla->mbhc_data.t_dce = DEFAULT_DCE_WAIT;
  7848. tabla->mbhc_data.t_sta = DEFAULT_STA_WAIT;
  7849. snd_soc_codec_set_drvdata(codec, tabla);
  7850. tabla->mclk_enabled = false;
  7851. tabla->bandgap_type = TABLA_BANDGAP_OFF;
  7852. tabla->clock_active = false;
  7853. tabla->config_mode_active = false;
  7854. tabla->mbhc_polling_active = false;
  7855. tabla->mbhc_fake_ins_start = 0;
  7856. tabla->no_mic_headset_override = false;
  7857. tabla->hs_polling_irq_prepared = false;
  7858. mutex_init(&tabla->codec_resource_lock);
  7859. tabla->codec = codec;
  7860. tabla->mbhc_state = MBHC_STATE_NONE;
  7861. tabla->mbhc_last_resume = 0;
  7862. for (i = 0; i < COMPANDER_MAX; i++) {
  7863. tabla->comp_enabled[i] = 0;
  7864. tabla->comp_fs[i] = COMPANDER_FS_48KHZ;
  7865. }
  7866. tabla->pdata = dev_get_platdata(codec->dev->parent);
  7867. tabla->intf_type = wcd9xxx_get_intf_type();
  7868. tabla->aux_pga_cnt = 0;
  7869. tabla->aux_l_gain = 0x1F;
  7870. tabla->aux_r_gain = 0x1F;
  7871. tabla_update_reg_address(tabla);
  7872. tabla_update_reg_defaults(codec);
  7873. tabla_codec_init_reg(codec);
  7874. ret = tabla_handle_pdata(tabla);
  7875. if (IS_ERR_VALUE(ret)) {
  7876. pr_err("%s: bad pdata\n", __func__);
  7877. goto err_pdata;
  7878. }
  7879. if (TABLA_IS_1_X(control->version))
  7880. snd_soc_add_codec_controls(codec, tabla_1_x_snd_controls,
  7881. ARRAY_SIZE(tabla_1_x_snd_controls));
  7882. else
  7883. snd_soc_add_codec_controls(codec, tabla_2_higher_snd_controls,
  7884. ARRAY_SIZE(tabla_2_higher_snd_controls));
  7885. if (TABLA_IS_1_X(control->version))
  7886. snd_soc_dapm_new_controls(dapm, tabla_1_x_dapm_widgets,
  7887. ARRAY_SIZE(tabla_1_x_dapm_widgets));
  7888. else
  7889. snd_soc_dapm_new_controls(dapm, tabla_2_higher_dapm_widgets,
  7890. ARRAY_SIZE(tabla_2_higher_dapm_widgets));
  7891. ptr = kmalloc((sizeof(tabla_rx_chs) +
  7892. sizeof(tabla_tx_chs)), GFP_KERNEL);
  7893. if (!ptr) {
  7894. pr_err("%s: no mem for slim chan ctl data\n", __func__);
  7895. ret = -ENOMEM;
  7896. goto err_nomem_slimch;
  7897. }
  7898. if (tabla->intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
  7899. snd_soc_dapm_new_controls(dapm, tabla_dapm_i2s_widgets,
  7900. ARRAY_SIZE(tabla_dapm_i2s_widgets));
  7901. snd_soc_dapm_add_routes(dapm, audio_i2s_map,
  7902. ARRAY_SIZE(audio_i2s_map));
  7903. for (i = 0; i < ARRAY_SIZE(tabla_i2s_dai); i++)
  7904. INIT_LIST_HEAD(&tabla->dai[i].wcd9xxx_ch_list);
  7905. } else if (tabla->intf_type == WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
  7906. for (i = 0; i < NUM_CODEC_DAIS; i++) {
  7907. INIT_LIST_HEAD(&tabla->dai[i].wcd9xxx_ch_list);
  7908. init_waitqueue_head(&tabla->dai[i].dai_wait);
  7909. }
  7910. }
  7911. control->num_rx_port = TABLA_RX_MAX;
  7912. control->rx_chs = ptr;
  7913. memcpy(control->rx_chs, tabla_rx_chs, sizeof(tabla_rx_chs));
  7914. control->num_tx_port = TABLA_TX_MAX;
  7915. control->tx_chs = ptr + sizeof(tabla_rx_chs);
  7916. memcpy(control->tx_chs, tabla_tx_chs, sizeof(tabla_tx_chs));
  7917. if (TABLA_IS_1_X(control->version)) {
  7918. snd_soc_dapm_add_routes(dapm, tabla_1_x_lineout_2_to_4_map,
  7919. ARRAY_SIZE(tabla_1_x_lineout_2_to_4_map));
  7920. } else if (TABLA_IS_2_0(control->version)) {
  7921. snd_soc_dapm_add_routes(dapm, tabla_2_x_lineout_2_to_4_map,
  7922. ARRAY_SIZE(tabla_2_x_lineout_2_to_4_map));
  7923. } else {
  7924. pr_err("%s : ERROR. Unsupported Tabla version 0x%2x\n",
  7925. __func__, control->version);
  7926. goto err_pdata;
  7927. }
  7928. snd_soc_dapm_sync(dapm);
  7929. ret = wcd9xxx_request_irq(core_res,
  7930. WCD9XXX_IRQ_MBHC_INSERTION,
  7931. tabla_hs_insert_irq, "Headset insert detect", tabla);
  7932. if (ret) {
  7933. pr_err("%s: Failed to request irq %d\n", __func__,
  7934. WCD9XXX_IRQ_MBHC_INSERTION);
  7935. goto err_insert_irq;
  7936. }
  7937. wcd9xxx_disable_irq(core_res, WCD9XXX_IRQ_MBHC_INSERTION);
  7938. ret = wcd9xxx_request_irq(core_res,
  7939. WCD9XXX_IRQ_MBHC_REMOVAL,
  7940. tabla_hs_remove_irq,
  7941. "Headset remove detect", tabla);
  7942. if (ret) {
  7943. pr_err("%s: Failed to request irq %d\n", __func__,
  7944. WCD9XXX_IRQ_MBHC_REMOVAL);
  7945. goto err_remove_irq;
  7946. }
  7947. ret = wcd9xxx_request_irq(core_res,
  7948. WCD9XXX_IRQ_MBHC_POTENTIAL,
  7949. tabla_dce_handler, "DC Estimation detect",
  7950. tabla);
  7951. if (ret) {
  7952. pr_err("%s: Failed to request irq %d\n", __func__,
  7953. WCD9XXX_IRQ_MBHC_POTENTIAL);
  7954. goto err_potential_irq;
  7955. }
  7956. ret = wcd9xxx_request_irq(core_res, WCD9XXX_IRQ_MBHC_RELEASE,
  7957. tabla_release_handler,
  7958. "Button Release detect", tabla);
  7959. if (ret) {
  7960. pr_err("%s: Failed to request irq %d\n", __func__,
  7961. WCD9XXX_IRQ_MBHC_RELEASE);
  7962. goto err_release_irq;
  7963. }
  7964. ret = wcd9xxx_request_irq(core_res, WCD9XXX_IRQ_SLIMBUS,
  7965. tabla_slimbus_irq, "SLIMBUS Slave", tabla);
  7966. if (ret) {
  7967. pr_err("%s: Failed to request irq %d\n", __func__,
  7968. WCD9XXX_IRQ_SLIMBUS);
  7969. goto err_slimbus_irq;
  7970. }
  7971. for (i = 0; i < WCD9XXX_SLIM_NUM_PORT_REG; i++)
  7972. wcd9xxx_interface_reg_write(control,
  7973. TABLA_SLIM_PGD_PORT_INT_EN0 + i, 0xFF);
  7974. ret = wcd9xxx_request_irq(core_res,
  7975. WCD9XXX_IRQ_HPH_PA_OCPL_FAULT,
  7976. tabla_hphl_ocp_irq,
  7977. "HPH_L OCP detect", tabla);
  7978. if (ret) {
  7979. pr_err("%s: Failed to request irq %d\n", __func__,
  7980. WCD9XXX_IRQ_HPH_PA_OCPL_FAULT);
  7981. goto err_hphl_ocp_irq;
  7982. }
  7983. wcd9xxx_disable_irq(core_res, WCD9XXX_IRQ_HPH_PA_OCPL_FAULT);
  7984. ret = wcd9xxx_request_irq(core_res,
  7985. WCD9XXX_IRQ_HPH_PA_OCPR_FAULT,
  7986. tabla_hphr_ocp_irq,
  7987. "HPH_R OCP detect", tabla);
  7988. if (ret) {
  7989. pr_err("%s: Failed to request irq %d\n", __func__,
  7990. WCD9XXX_IRQ_HPH_PA_OCPR_FAULT);
  7991. goto err_hphr_ocp_irq;
  7992. }
  7993. wcd9xxx_disable_irq(core_res, WCD9XXX_IRQ_HPH_PA_OCPR_FAULT);
  7994. /*
  7995. * Register suspend lock and notifier to resend edge triggered
  7996. * gpio IRQs
  7997. */
  7998. wake_lock_init(&tabla->irq_resend_wlock, WAKE_LOCK_SUSPEND,
  7999. "tabla_gpio_irq_resend");
  8000. tabla->gpio_irq_resend = false;
  8001. mutex_lock(&dapm->codec->mutex);
  8002. snd_soc_dapm_disable_pin(dapm, "ANC HPHL");
  8003. snd_soc_dapm_disable_pin(dapm, "ANC HPHR");
  8004. snd_soc_dapm_disable_pin(dapm, "ANC HEADPHONE");
  8005. snd_soc_dapm_sync(dapm);
  8006. mutex_unlock(&dapm->codec->mutex);
  8007. #ifdef CONFIG_DEBUG_FS
  8008. if (ret == 0) {
  8009. tabla->debugfs_poke =
  8010. debugfs_create_file("TRRS", S_IFREG | S_IRUGO, NULL, tabla,
  8011. &codec_debug_ops);
  8012. tabla->debugfs_mbhc =
  8013. debugfs_create_file("tabla_mbhc", S_IFREG | S_IRUGO,
  8014. NULL, tabla, &codec_mbhc_debug_ops);
  8015. }
  8016. #endif
  8017. codec->ignore_pmdown_time = 1;
  8018. return ret;
  8019. err_hphr_ocp_irq:
  8020. wcd9xxx_free_irq(core_res,
  8021. WCD9XXX_IRQ_HPH_PA_OCPL_FAULT, tabla);
  8022. err_hphl_ocp_irq:
  8023. wcd9xxx_free_irq(core_res, WCD9XXX_IRQ_SLIMBUS, tabla);
  8024. err_slimbus_irq:
  8025. wcd9xxx_free_irq(core_res, WCD9XXX_IRQ_MBHC_RELEASE, tabla);
  8026. err_release_irq:
  8027. wcd9xxx_free_irq(core_res, WCD9XXX_IRQ_MBHC_POTENTIAL,
  8028. tabla);
  8029. err_potential_irq:
  8030. wcd9xxx_free_irq(core_res, WCD9XXX_IRQ_MBHC_REMOVAL, tabla);
  8031. err_remove_irq:
  8032. wcd9xxx_free_irq(core_res, WCD9XXX_IRQ_MBHC_INSERTION,
  8033. tabla);
  8034. err_insert_irq:
  8035. err_pdata:
  8036. kfree(ptr);
  8037. err_nomem_slimch:
  8038. mutex_destroy(&tabla->codec_resource_lock);
  8039. kfree(tabla);
  8040. return ret;
  8041. }
  8042. static int tabla_codec_remove(struct snd_soc_codec *codec)
  8043. {
  8044. struct tabla_priv *tabla = snd_soc_codec_get_drvdata(codec);
  8045. wake_lock_destroy(&tabla->irq_resend_wlock);
  8046. wcd9xxx_free_irq(codec->control_data, WCD9XXX_IRQ_SLIMBUS, tabla);
  8047. wcd9xxx_free_irq(codec->control_data, WCD9XXX_IRQ_MBHC_RELEASE, tabla);
  8048. wcd9xxx_free_irq(codec->control_data, WCD9XXX_IRQ_MBHC_POTENTIAL,
  8049. tabla);
  8050. wcd9xxx_free_irq(codec->control_data, WCD9XXX_IRQ_MBHC_REMOVAL, tabla);
  8051. wcd9xxx_free_irq(codec->control_data, WCD9XXX_IRQ_MBHC_INSERTION,
  8052. tabla);
  8053. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  8054. tabla_codec_disable_clock_block(codec);
  8055. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  8056. tabla_codec_enable_bandgap(codec, TABLA_BANDGAP_OFF);
  8057. if (tabla->mbhc_fw)
  8058. release_firmware(tabla->mbhc_fw);
  8059. mutex_destroy(&tabla->codec_resource_lock);
  8060. #ifdef CONFIG_DEBUG_FS
  8061. debugfs_remove(tabla->debugfs_poke);
  8062. debugfs_remove(tabla->debugfs_mbhc);
  8063. #endif
  8064. kfree(tabla);
  8065. return 0;
  8066. }
  8067. static struct snd_soc_codec_driver soc_codec_dev_tabla = {
  8068. .probe = tabla_codec_probe,
  8069. .remove = tabla_codec_remove,
  8070. .read = tabla_read,
  8071. .write = tabla_write,
  8072. .readable_register = tabla_readable,
  8073. .volatile_register = tabla_volatile,
  8074. .reg_cache_size = TABLA_CACHE_SIZE,
  8075. .reg_cache_default = tabla_reg_defaults,
  8076. .reg_word_size = 1,
  8077. .controls = tabla_snd_controls,
  8078. .num_controls = ARRAY_SIZE(tabla_snd_controls),
  8079. .dapm_widgets = tabla_dapm_widgets,
  8080. .num_dapm_widgets = ARRAY_SIZE(tabla_dapm_widgets),
  8081. .dapm_routes = audio_map,
  8082. .num_dapm_routes = ARRAY_SIZE(audio_map),
  8083. };
  8084. #ifdef CONFIG_PM
  8085. static int tabla_suspend(struct device *dev)
  8086. {
  8087. dev_dbg(dev, "%s: system suspend\n", __func__);
  8088. return 0;
  8089. }
  8090. static int tabla_resume(struct device *dev)
  8091. {
  8092. int irq;
  8093. struct platform_device *pdev = to_platform_device(dev);
  8094. struct tabla_priv *tabla = platform_get_drvdata(pdev);
  8095. dev_dbg(dev, "%s: system resume tabla %p\n", __func__, tabla);
  8096. if (tabla) {
  8097. TABLA_ACQUIRE_LOCK(tabla->codec_resource_lock);
  8098. tabla->mbhc_last_resume = jiffies;
  8099. if (tabla->gpio_irq_resend) {
  8100. WARN_ON(!tabla->mbhc_cfg.gpio_irq);
  8101. tabla->gpio_irq_resend = false;
  8102. irq = tabla->mbhc_cfg.gpio_irq;
  8103. pr_debug("%s: Resending GPIO IRQ %d\n", __func__, irq);
  8104. irq_set_pending(irq);
  8105. check_irq_resend(irq_to_desc(irq), irq);
  8106. /* release suspend lock */
  8107. wake_unlock(&tabla->irq_resend_wlock);
  8108. }
  8109. TABLA_RELEASE_LOCK(tabla->codec_resource_lock);
  8110. }
  8111. return 0;
  8112. }
  8113. static const struct dev_pm_ops tabla_pm_ops = {
  8114. .suspend = tabla_suspend,
  8115. .resume = tabla_resume,
  8116. };
  8117. #endif
  8118. static int __devinit tabla_probe(struct platform_device *pdev)
  8119. {
  8120. int ret = 0;
  8121. pr_err("tabla_probe\n");
  8122. if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_SLIMBUS)
  8123. ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_tabla,
  8124. tabla_dai, ARRAY_SIZE(tabla_dai));
  8125. else if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_I2C)
  8126. ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_tabla,
  8127. tabla_i2s_dai, ARRAY_SIZE(tabla_i2s_dai));
  8128. return ret;
  8129. }
  8130. static int __devexit tabla_remove(struct platform_device *pdev)
  8131. {
  8132. snd_soc_unregister_codec(&pdev->dev);
  8133. return 0;
  8134. }
  8135. static struct platform_driver tabla_codec_driver = {
  8136. .probe = tabla_probe,
  8137. .remove = tabla_remove,
  8138. .driver = {
  8139. .name = "tabla_codec",
  8140. .owner = THIS_MODULE,
  8141. #ifdef CONFIG_PM
  8142. .pm = &tabla_pm_ops,
  8143. #endif
  8144. },
  8145. };
  8146. static struct platform_driver tabla1x_codec_driver = {
  8147. .probe = tabla_probe,
  8148. .remove = tabla_remove,
  8149. .driver = {
  8150. .name = "tabla1x_codec",
  8151. .owner = THIS_MODULE,
  8152. #ifdef CONFIG_PM
  8153. .pm = &tabla_pm_ops,
  8154. #endif
  8155. },
  8156. };
  8157. static int __init tabla_codec_init(void)
  8158. {
  8159. int rtn = platform_driver_register(&tabla_codec_driver);
  8160. if (rtn == 0) {
  8161. rtn = platform_driver_register(&tabla1x_codec_driver);
  8162. if (rtn != 0)
  8163. platform_driver_unregister(&tabla_codec_driver);
  8164. }
  8165. return rtn;
  8166. }
  8167. static void __exit tabla_codec_exit(void)
  8168. {
  8169. platform_driver_unregister(&tabla1x_codec_driver);
  8170. platform_driver_unregister(&tabla_codec_driver);
  8171. }
  8172. module_init(tabla_codec_init);
  8173. module_exit(tabla_codec_exit);
  8174. MODULE_DESCRIPTION("Tabla codec driver");
  8175. MODULE_VERSION("1.0");
  8176. MODULE_LICENSE("GPL v2");