max98504a.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553
  1. /*
  2. * max98504.c -- MAX98504 SoC Audio driver
  3. *
  4. * Copyright 2013-2014 Maxim Integrated Products
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/init.h>
  12. #include <linux/i2c.h>
  13. #include <sound/soc.h>
  14. #include <linux/slab.h>
  15. #include <linux/gpio.h>
  16. #include <sound/tlv.h>
  17. #include <sound/tlv.h>
  18. #include <sound/max98504a.h>
  19. #include <linux/delay.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <linux/of_gpio.h>
  22. #include "max98504a.h"
  23. #ifdef DEBUG_MAX98504
  24. #define msg_maxim(format, args...) \
  25. printk(KERN_INFO "[MAX98504_DEBUG] %s " format, __func__, ## args)
  26. #else
  27. #define msg_maxim(format, args...)
  28. #endif
  29. static struct regmap *regmap;
  30. static DEFINE_MUTEX(max98504_lock);
  31. static struct reg_default max98504_reg[] = {
  32. { MAX98504_REG_01_INTERRUPT_STATUS, 0x00 },
  33. { MAX98504_REG_02_INTERRUPT_FLAGS, 0x00 },
  34. { MAX98504_REG_03_INTERRUPT_ENABLES, 0x00 },
  35. { MAX98504_REG_04_INTERRUPT_FLAG_CLEARS, 0x00 },
  36. { MAX98504_REG_10_GPIO_ENABLE, 0x00 },
  37. { MAX98504_REG_11_GPIO_CONFIG, 0x00 },
  38. { MAX98504_REG_12_WATCHDOG_ENABLE, 0x00 },
  39. { MAX98504_REG_13_WATCHDOG_CONFIG, 0x00 },
  40. { MAX98504_REG_14_WATCHDOG_CLEAR, 0x00 },
  41. { MAX98504_REG_15_CLOCK_MONITOR_ENABLE, 0x00 },
  42. { MAX98504_REG_16_PVDD_BROWNOUT_ENABLE, 0x00 },
  43. { MAX98504_REG_17_PVDD_BROWNOUT_CONFIG_1, 0x00 },
  44. { MAX98504_REG_18_PVDD_BROWNOUT_CONFIG_2, 0x00 },
  45. { MAX98504_REG_19_PVDD_BROWNOUT_CONFIG_3, 0x00 },
  46. { MAX98504_REG_1A_PVDD_BROWNOUT_CONFIG_4, 0x00 },
  47. { MAX98504_REG_20_PCM_RX_ENABLES, 0x00 },
  48. { MAX98504_REG_21_PCM_TX_ENABLES, 0x00 },
  49. { MAX98504_REG_22_PCM_TX_HIZ_CONTROL, 0x00 },
  50. { MAX98504_REG_23_PCM_TX_CHANNEL_SOURCES, 0x00 },
  51. { MAX98504_REG_24_PCM_MODE_CONFIG, 0x00 },
  52. { MAX98504_REG_25_PCM_DSP_CONFIG, 0x00 },
  53. { MAX98504_REG_26_PCM_CLOCK_SETUP, 0x00 },
  54. { MAX98504_REG_27_PCM_SAMPLE_RATE_SETUP, 0x00 },
  55. { MAX98504_REG_28_PCM_TO_SPEAKER_MONOMIX, 0x00 },
  56. { MAX98504_REG_30_PDM_TX_ENABLES, 0x00 },
  57. { MAX98504_REG_31_PDM_TX_HIZ_CONTROL, 0x00 },
  58. { MAX98504_REG_32_PDM_TX_CONTROL, 0x00 },
  59. { MAX98504_REG_33_PDM_RX_ENABLE, 0x00 },
  60. { MAX98504_REG_34_SPEAKER_ENABLE, 0x00 },
  61. { MAX98504_REG_35_SPEAKER_SOURCE_SELECT, 0x00 },
  62. { MAX98504_REG_36_MEASUREMENT_ENABLES, 0x00 },
  63. { MAX98504_REG_37_ANALOGUE_INPUT_GAIN, 0x00 },
  64. { MAX98504_REG_38_TEMPERATURE_LIMIT_CONFIG, 0x00 },
  65. { MAX98504_REG_39_ANALOGUE_SPARE, 0x00 },
  66. { MAX98504_REG_40_GLOBAL_ENABLE, 0x00 },
  67. { MAX98504_REG_41_SOFTWARE_RESET, 0x00 },
  68. };
  69. static struct {
  70. u8 read;
  71. u8 write;
  72. u8 vol;
  73. } max98504_reg_access[MAX98504_REG_CNT] = {
  74. [MAX98504_REG_01_INTERRUPT_STATUS] = { 0xFF, 0x00, 0xFF },
  75. [MAX98504_REG_02_INTERRUPT_FLAGS] = { 0xFF, 0x00, 0xFF },
  76. [MAX98504_REG_03_INTERRUPT_ENABLES] = { 0xFF, 0xFF, 0x00 },
  77. [MAX98504_REG_04_INTERRUPT_FLAG_CLEARS] = { 0x00, 0xFF, 0xFF },
  78. [MAX98504_REG_10_GPIO_ENABLE] = { 0xFF, 0xFF, 0x00 },
  79. [MAX98504_REG_11_GPIO_CONFIG] = { 0xFF, 0xFF, 0x00 },
  80. [MAX98504_REG_12_WATCHDOG_ENABLE] = { 0xFF, 0xFF, 0x00 },
  81. [MAX98504_REG_13_WATCHDOG_CONFIG] = { 0xFF, 0xFF, 0x00 },
  82. [MAX98504_REG_14_WATCHDOG_CLEAR] = { 0x00, 0xFF, 0xFF },
  83. [MAX98504_REG_15_CLOCK_MONITOR_ENABLE] = { 0xFF, 0xFF, 0x00 },
  84. [MAX98504_REG_16_PVDD_BROWNOUT_ENABLE] = { 0xFF, 0xFF, 0x00 },
  85. [MAX98504_REG_17_PVDD_BROWNOUT_CONFIG_1] = { 0xFF, 0xFF, 0x00 },
  86. [MAX98504_REG_18_PVDD_BROWNOUT_CONFIG_2] = { 0xFF, 0xFF, 0x00 },
  87. [MAX98504_REG_19_PVDD_BROWNOUT_CONFIG_3] = { 0xFF, 0xFF, 0x00 },
  88. [MAX98504_REG_1A_PVDD_BROWNOUT_CONFIG_4] = { 0xFF, 0xFF, 0x00 },
  89. [MAX98504_REG_20_PCM_RX_ENABLES] = { 0xFF, 0xFF, 0x00 },
  90. [MAX98504_REG_21_PCM_TX_ENABLES] = { 0xFF, 0xFF, 0x00 },
  91. [MAX98504_REG_22_PCM_TX_HIZ_CONTROL] = { 0xFF, 0xFF, 0x00 },
  92. [MAX98504_REG_23_PCM_TX_CHANNEL_SOURCES] = { 0xFF, 0xFF, 0x00 },
  93. [MAX98504_REG_24_PCM_MODE_CONFIG] = { 0xFF, 0xFF, 0x00 },
  94. [MAX98504_REG_25_PCM_DSP_CONFIG] = { 0xFF, 0xFF, 0x00 },
  95. [MAX98504_REG_26_PCM_CLOCK_SETUP] = { 0xFF, 0xFF, 0x00 },
  96. [MAX98504_REG_27_PCM_SAMPLE_RATE_SETUP] = { 0xFF, 0xFF, 0x00 },
  97. [MAX98504_REG_28_PCM_TO_SPEAKER_MONOMIX] = { 0xFF, 0xFF, 0x00 },
  98. [MAX98504_REG_30_PDM_TX_ENABLES] = { 0xFF, 0xFF, 0x00 },
  99. [MAX98504_REG_31_PDM_TX_HIZ_CONTROL] = { 0xFF, 0xFF, 0x00 },
  100. [MAX98504_REG_32_PDM_TX_CONTROL] = { 0xFF, 0xFF, 0x00 },
  101. [MAX98504_REG_33_PDM_RX_ENABLE] = { 0xFF, 0xFF, 0x00 },
  102. [MAX98504_REG_34_SPEAKER_ENABLE] = { 0xFF, 0xFF, 0x00 },
  103. [MAX98504_REG_35_SPEAKER_SOURCE_SELECT] = { 0xFF, 0xFF, 0x00 },
  104. [MAX98504_REG_36_MEASUREMENT_ENABLES] = { 0xFF, 0xFF, 0x00 },
  105. [MAX98504_REG_37_ANALOGUE_INPUT_GAIN] = { 0xFF, 0xFF, 0x00 },
  106. [MAX98504_REG_38_TEMPERATURE_LIMIT_CONFIG] = { 0xFF, 0xFF, 0x00 },
  107. [MAX98504_REG_39_ANALOGUE_SPARE] = { 0xFF, 0xFF, 0x00 },
  108. [MAX98504_REG_40_GLOBAL_ENABLE] = { 0xFF, 0xFF, 0xFF },
  109. [MAX98504_REG_41_SOFTWARE_RESET] = { 0x00, 0xFF, 0xFF },
  110. };
  111. static bool max98504_volatile_register(struct device *dev, unsigned int reg)
  112. {
  113. if (max98504_reg_access[reg].vol)
  114. return 1;
  115. else
  116. return 0;
  117. }
  118. static bool max98504_readable_register(struct device *dev, unsigned int reg)
  119. {
  120. if (reg >= MAX98504_REG_CNT)
  121. return 0;
  122. return max98504_reg_access[reg].read != 0;
  123. }
  124. static int max98504_reset(struct max98504_priv *max98504)
  125. {
  126. int ret;
  127. ret = regmap_write(max98504->regmap, MAX98504_REG_41_SOFTWARE_RESET, M98504_SOFTWARE_RESET_MASK);
  128. msleep(10);
  129. return ret;
  130. }
  131. static int max98504_probe(struct max98504_priv *max98504)
  132. {
  133. struct max98504_pdata *pdata = max98504->pdata;
  134. struct max98504_cfg_data *cfg_data = &pdata->cfg_data;
  135. u8 regval;
  136. int ret;
  137. unsigned int value;
  138. msg_maxim("\n");
  139. max98504_reset(max98504);
  140. ret = regmap_read(max98504->regmap, MAX98504_REG_7FFF_REV_ID, &value);
  141. if (ret < 0) {
  142. pr_err("Failed to read device revision: %d\n",
  143. ret);
  144. goto err_access;
  145. }
  146. msg_maxim("REV ID=0x%x\n", value);
  147. if (!pdata) {
  148. pr_err("No platform data\n");
  149. return ret;
  150. }
  151. /* Configure Rx Mode */
  152. if(pdata->rx_mode == MODE_RX_PCM) {
  153. regval = 0;
  154. if(cfg_data->rx_dither_en) regval |= M98504_PCM_DSP_CFG_RX_DITH_EN_MASK;
  155. if(cfg_data->rx_flt_mode) regval |= M98504_PCM_DSP_CFG_RX_FLT_MODE_MASK;
  156. regmap_update_bits(max98504->regmap, MAX98504_REG_25_PCM_DSP_CONFIG, M98504_PCM_DSP_CFG_RX_DITH_EN_MASK|M98504_PCM_DSP_CFG_RX_FLT_MODE_MASK, regval);
  157. regmap_write(max98504->regmap, MAX98504_REG_20_PCM_RX_ENABLES, (u8)cfg_data->rx_ch_en);
  158. }
  159. else if(pdata->rx_mode==MODE_RX_PDM0 || pdata->rx_mode==MODE_RX_PDM1) {
  160. regmap_write(max98504->regmap, MAX98504_REG_33_PDM_RX_ENABLE, M98504_PDM_RX_EN_MASK);
  161. }
  162. regmap_write(max98504->regmap, MAX98504_REG_35_SPEAKER_SOURCE_SELECT, (u8) (M98504_SPK_SRC_SEL_MASK & pdata->rx_mode));
  163. /* Configure Tx Mode */
  164. if(pdata->tx_mode == MODE_TX_PCM) {
  165. regval = 0;
  166. if(cfg_data->tx_dither_en) regval |= M98504_PCM_DSP_CFG_TX_DITH_EN_MASK;
  167. if(cfg_data->meas_dc_block_en) regval |= M98504_PCM_DSP_CFG_MEAS_DCBLK_EN_MASK;
  168. regmap_update_bits(max98504->regmap, MAX98504_REG_25_PCM_DSP_CONFIG, M98504_PCM_DSP_CFG_TX_DITH_EN_MASK|M98504_PCM_DSP_CFG_MEAS_DCBLK_EN_MASK, regval);
  169. regmap_write(max98504->regmap, MAX98504_REG_21_PCM_TX_ENABLES, (u8)cfg_data->tx_ch_en);
  170. regmap_write(max98504->regmap, MAX98504_REG_22_PCM_TX_HIZ_CONTROL, (u8)cfg_data->tx_hiz_ch_en);
  171. regmap_write(max98504->regmap, MAX98504_REG_23_PCM_TX_CHANNEL_SOURCES, (u8)cfg_data->tx_ch_src);
  172. }
  173. else {
  174. regmap_write(max98504->regmap, MAX98504_REG_30_PDM_TX_ENABLES, (u8)cfg_data->tx_ch_en);
  175. regmap_write(max98504->regmap, MAX98504_REG_31_PDM_TX_HIZ_CONTROL, (u8)cfg_data->tx_hiz_ch_en);
  176. regmap_write(max98504->regmap, MAX98504_REG_32_PDM_TX_CONTROL, (u8)cfg_data->tx_ch_src);
  177. }
  178. regmap_write(max98504->regmap, MAX98504_REG_36_MEASUREMENT_ENABLES, M98504_MEAS_I_EN_MASK | M98504_MEAS_V_EN_MASK);
  179. /* Brownout Protection */
  180. regmap_write(max98504->regmap, MAX98504_REG_16_PVDD_BROWNOUT_ENABLE, 0x1);
  181. regmap_write(max98504->regmap, MAX98504_REG_17_PVDD_BROWNOUT_CONFIG_1, 0x3);
  182. regmap_write(max98504->regmap, MAX98504_REG_18_PVDD_BROWNOUT_CONFIG_2, 0x64);
  183. regmap_write(max98504->regmap, MAX98504_REG_19_PVDD_BROWNOUT_CONFIG_3, 0xff);
  184. regmap_write(max98504->regmap, MAX98504_REG_1A_PVDD_BROWNOUT_CONFIG_4, 0xff);
  185. #if defined(CONFIG_SEC_S_PROJECT) //bypass temp code
  186. max98504_set_speaker_status(1);
  187. #endif
  188. return ret;
  189. err_access:
  190. return ret;
  191. }
  192. int max98504_set_speaker_status(int OnOff)
  193. {
  194. mutex_lock(&max98504_lock);
  195. if(regmap==NULL) {
  196. pr_err("Speaker control is not allowed.\n");
  197. return -1;
  198. }
  199. if(OnOff) {
  200. regmap_update_bits(regmap, MAX98504_REG_34_SPEAKER_ENABLE,
  201. M98504_SPK_EN_MASK, M98504_SPK_EN_MASK);
  202. regmap_update_bits(regmap, MAX98504_REG_40_GLOBAL_ENABLE,
  203. M98504_GLOBAL_EN_MASK, M98504_GLOBAL_EN_MASK);
  204. }
  205. else {
  206. regmap_update_bits(regmap, MAX98504_REG_40_GLOBAL_ENABLE,
  207. M98504_GLOBAL_EN_MASK, 0);
  208. regmap_update_bits(regmap, MAX98504_REG_34_SPEAKER_ENABLE,
  209. M98504_SPK_EN_MASK, 0);
  210. }
  211. mutex_unlock(&max98504_lock);
  212. return 0;
  213. }
  214. bool max98504_get_speaker_status(void)
  215. {
  216. unsigned int ret;
  217. mutex_lock(&max98504_lock);
  218. if(regmap==NULL) {
  219. pr_err("Speaker control is not allowed.\n");
  220. return 0;
  221. }
  222. regmap_read(regmap, MAX98504_REG_34_SPEAKER_ENABLE, &ret);
  223. mutex_unlock(&max98504_lock);
  224. return ret>0?true:false;
  225. }
  226. EXPORT_SYMBOL_GPL(max98504_set_speaker_status);
  227. EXPORT_SYMBOL_GPL(max98504_get_speaker_status);
  228. static const struct regmap_config max98504_regmap = {
  229. .reg_bits = 16,
  230. .val_bits = 8,
  231. .max_register = MAX98504_REG_CNT,
  232. .reg_defaults = max98504_reg,
  233. .num_reg_defaults = ARRAY_SIZE(max98504_reg),
  234. .volatile_reg = max98504_volatile_register,
  235. .readable_reg = max98504_readable_register,
  236. .cache_type = REGCACHE_RBTREE,
  237. };
  238. static int reg_set_optimum_mode_check(struct regulator *reg, int load_uA)
  239. {
  240. return (regulator_count_voltages(reg) > 0) ?
  241. regulator_set_optimum_mode(reg, load_uA) : 0;
  242. }
  243. static int max98504_regulator_config(struct i2c_client *i2c, bool pullup, bool on)
  244. {
  245. struct regulator *max98504_vcc_i2c;
  246. int rc;
  247. #define VCC_I2C_MIN_UV 1800000
  248. #define VCC_I2C_MAX_UV 1800000
  249. #define I2C_LOAD_UA 300000
  250. if (pullup) {
  251. max98504_vcc_i2c = regulator_get(&i2c->dev, "vcc_i2c");
  252. if (IS_ERR(max98504_vcc_i2c)) {
  253. rc = PTR_ERR(max98504_vcc_i2c);
  254. pr_info("Regulator get failed rc=%d\n", rc);
  255. goto error_get_vtg_i2c;
  256. }
  257. if (regulator_count_voltages(max98504_vcc_i2c) > 0) {
  258. rc = regulator_set_voltage(max98504_vcc_i2c, VCC_I2C_MIN_UV, VCC_I2C_MAX_UV);
  259. if (rc) {
  260. pr_info("regulator set_vtg failed rc=%d\n", rc);
  261. goto error_set_vtg_i2c;
  262. }
  263. }
  264. rc = reg_set_optimum_mode_check(max98504_vcc_i2c, I2C_LOAD_UA);
  265. if (rc < 0) {
  266. pr_info("Regulator vcc_i2c set_opt failed rc=%d\n", rc);
  267. goto error_reg_opt_i2c;
  268. }
  269. rc = regulator_enable(max98504_vcc_i2c);
  270. if (rc) {
  271. pr_info("Regulator vcc_i2c enable failed rc=%d\n", rc);
  272. goto error_reg_en_vcc_i2c;
  273. }
  274. }
  275. return 0;
  276. error_set_vtg_i2c:
  277. regulator_put(max98504_vcc_i2c);
  278. error_get_vtg_i2c:
  279. if (regulator_count_voltages(max98504_vcc_i2c) > 0)
  280. regulator_set_voltage(max98504_vcc_i2c, 0, VCC_I2C_MAX_UV);
  281. error_reg_en_vcc_i2c:
  282. if(pullup) reg_set_optimum_mode_check(max98504_vcc_i2c, 0);
  283. error_reg_opt_i2c:
  284. regulator_disable(max98504_vcc_i2c);
  285. return rc;
  286. }
  287. #ifdef USE_MAX98504_IRQ
  288. static irqreturn_t max98504_interrupt(int irq, void *data)
  289. {
  290. struct max98504_priv *max98504 = (struct max98504_priv * )data;
  291. unsigned int mask;
  292. unsigned int flag;
  293. regmap_read(max98504->regmap, MAX98504_REG_03_INTERRUPT_ENABLES, &mask);
  294. regmap_read(max98504->regmap, MAX98504_REG_02_INTERRUPT_FLAGS, &flag);
  295. msg_maxim("flag=0x%02x mask=0x%02x -> flag=0x%02x\n",
  296. flag, mask, flag & mask);
  297. flag &= mask;
  298. if (!flag)
  299. return IRQ_NONE;
  300. /* Send work to be scheduled */
  301. if (flag & M98504_INT_GENFAIL_EN_MASK) {
  302. msg_maxim("M98504_INT_GENFAIL_EN_MASK active!");
  303. }
  304. if (flag & M98504_INT_AUTHDONE_EN_MASK) {
  305. msg_maxim("M98504_INT_AUTHDONE_EN_MASK active!");
  306. }
  307. if (flag & M98504_INT_VBATBROWN_EN_MASK) {
  308. msg_maxim("M98504_INT_VBATBROWN_EN_MASK active!");
  309. }
  310. if (flag & M98504_INT_WATCHFAIL_EN_MASK) {
  311. msg_maxim("M98504_INT_WATCHFAIL_EN_MASK active!");
  312. }
  313. if (flag & M98504_INT_THERMWARN_END_EN_MASK) {
  314. msg_maxim("M98504_INT_THERMWARN_END_EN_MASK active!");
  315. }
  316. if (flag & M98504_INT_THERMWARN_BGN_EN_MASK) {
  317. msg_maxim("M98504_INT_THERMWARN_BGN_EN_MASK active!\n");
  318. }
  319. if (flag & M98504_INT_THERMSHDN_END_EN_MASK) {
  320. msg_maxim("M98504_INT_THERMSHDN_END_EN_MASK active!\n");
  321. }
  322. if (flag & M98504_INT_THERMSHDN_BGN_FLAG_MASK) {
  323. msg_maxim("M98504_INT_THERMSHDN_BGN_FLAG_MASK active!\n");
  324. }
  325. regmap_write(max98504->regmap, MAX98504_REG_04_INTERRUPT_FLAG_CLEARS, flag&0xff);
  326. return IRQ_HANDLED;
  327. }
  328. #endif
  329. static int __devinit max98504_i2c_probe(struct i2c_client *i2c,
  330. const struct i2c_device_id *id)
  331. {
  332. struct max98504_priv *max98504;
  333. struct max98504_pdata *pdata;
  334. int ret;
  335. msg_maxim("\n");
  336. max98504 = kzalloc(sizeof(struct max98504_priv), GFP_KERNEL);
  337. if (max98504 == NULL)
  338. return -ENOMEM;
  339. max98504->devtype = id->driver_data;
  340. i2c_set_clientdata(i2c, max98504);
  341. max98504->control_data = i2c;
  342. if (i2c->dev.of_node) {
  343. max98504->pdata = devm_kzalloc(&i2c->dev,
  344. sizeof(struct max98504_pdata), GFP_KERNEL);
  345. if (!max98504->pdata) {
  346. dev_err(&i2c->dev, "Failed to allocate memory\n");
  347. return -ENOMEM;
  348. }
  349. else pdata = max98504->pdata;
  350. #ifdef USE_MAX98504_IRQ
  351. pdata->irq = of_get_named_gpio_flags(i2c->dev.of_node, "max98504,irq-gpio",
  352. 0, NULL);
  353. #endif
  354. ret = of_property_read_u32(i2c->dev.of_node, "max98504,rx_mode", &pdata->rx_mode);
  355. if (ret) {
  356. dev_err(&i2c->dev, "Failed to read rx_mode.\n");
  357. return -EINVAL;
  358. }
  359. ret = of_property_read_u32(i2c->dev.of_node, "max98504,tx_mode", &pdata->tx_mode);
  360. if (ret) {
  361. dev_err(&i2c->dev, "Failed to read tx_mode.\n");
  362. return -EINVAL;
  363. }
  364. ret = of_property_read_u32_array(i2c->dev.of_node, "max98504,cfg_data",
  365. (u32*)&pdata->cfg_data, sizeof(struct max98504_cfg_data)/sizeof(u32));
  366. if (ret) {
  367. dev_err(&i2c->dev, "Failed to read cfg_data.\n");
  368. return -EINVAL;
  369. }
  370. msg_maxim("rx_mode:%d, tx_mode:%d, tx_dither_en:%d, rx_dither_en:%d, meas_dc_block_en:%d, rx_flt_mode:%d, rx_ch_en:%d\n",
  371. pdata->rx_mode,
  372. pdata->tx_mode,
  373. pdata->cfg_data.tx_dither_en,
  374. pdata->cfg_data.rx_dither_en,
  375. pdata->cfg_data.meas_dc_block_en,
  376. pdata->cfg_data.rx_flt_mode,
  377. pdata->cfg_data.rx_ch_en);
  378. msg_maxim("tx_ch_en:%d, tx_hiz_ch_en:%d, tx_ch_src:%d, auth_en:%d, wdog_time_out:%d\n",
  379. pdata->cfg_data.tx_ch_en,
  380. pdata->cfg_data.tx_hiz_ch_en,
  381. pdata->cfg_data.tx_ch_src,
  382. pdata->cfg_data.auth_en,
  383. pdata->cfg_data.wdog_time_out);
  384. } else max98504->pdata = i2c->dev.platform_data;
  385. max98504_regulator_config(i2c, of_property_read_bool(i2c->dev.of_node, "max98504,i2c-pull-up"), 1);
  386. max98504->regmap = regmap = regmap_init_i2c(i2c, &max98504_regmap);
  387. if (IS_ERR(max98504->regmap)) {
  388. ret = PTR_ERR(max98504->regmap);
  389. dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
  390. goto err_out;
  391. }
  392. max98504_probe(max98504);
  393. #ifdef USE_MAX98504_IRQ
  394. if (gpio_is_valid(pdata->irq)) {
  395. /* configure touchscreen irq gpio */
  396. ret = gpio_request(pdata->irq, "max98504_irq_gpio");
  397. if (ret) {
  398. dev_err(&i2c->dev, "unable to request gpio [%d]\n",
  399. pdata->irq);
  400. goto err_irq_gpio_req;
  401. }
  402. ret = gpio_direction_input(pdata->irq);
  403. if (ret) {
  404. dev_err(&i2c->dev,
  405. "unable to set direction for gpio [%d]\n",
  406. pdata->irq);
  407. goto err_irq_gpio_req;
  408. }
  409. i2c->irq = gpio_to_irq(pdata->irq);
  410. } else {
  411. dev_err(&i2c->dev, "irq gpio not provided\n");
  412. }
  413. ret = request_threaded_irq(i2c->irq, NULL, max98504_interrupt,
  414. IRQF_TRIGGER_FALLING, "max98504_interrupt", max98504);
  415. if (ret) {
  416. dev_err(&i2c->dev, "Failed to register interrupt\n");
  417. }
  418. err_irq_gpio_req:
  419. if (gpio_is_valid(pdata->irq))
  420. gpio_free(pdata->irq);
  421. #endif
  422. err_out:
  423. if (ret < 0) {
  424. if (max98504->regmap)
  425. regmap_exit(max98504->regmap);
  426. kfree(max98504);
  427. }
  428. return 0;
  429. }
  430. static __devexit int max98504_i2c_remove(struct i2c_client *client)
  431. {
  432. struct max98504_priv *max98504 = dev_get_drvdata(&client->dev);
  433. if (max98504->regmap)
  434. regmap_exit(max98504->regmap);
  435. kfree(i2c_get_clientdata(client));
  436. return 0;
  437. }
  438. static const struct i2c_device_id max98504_i2c_id[] = {
  439. { "max98504", MAX98504 },
  440. { }
  441. };
  442. MODULE_DEVICE_TABLE(i2c, max98504_i2c_id);
  443. static struct i2c_driver max98504_i2c_driver = {
  444. .driver = {
  445. .name = "max98504",
  446. .owner = THIS_MODULE,
  447. },
  448. .probe = max98504_i2c_probe,
  449. .remove = __devexit_p(max98504_i2c_remove),
  450. .id_table = max98504_i2c_id,
  451. };
  452. static int __init max98504_init(void)
  453. {
  454. return i2c_add_driver(&max98504_i2c_driver);
  455. }
  456. module_init(max98504_init);
  457. static void __exit max98504_exit(void)
  458. {
  459. i2c_del_driver(&max98504_i2c_driver);
  460. }
  461. module_exit(max98504_exit);
  462. MODULE_DESCRIPTION("SoC MAX98504 driver");
  463. MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
  464. MODULE_LICENSE("GPL");