jz4740.c 12 KB

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  1. /*
  2. * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * You should have received a copy of the GNU General Public License along
  9. * with this program; if not, write to the Free Software Foundation, Inc.,
  10. * 675 Mass Ave, Cambridge, MA 02139, USA.
  11. *
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/slab.h>
  17. #include <linux/io.h>
  18. #include <linux/delay.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/initval.h>
  23. #include <sound/soc.h>
  24. #define JZ4740_REG_CODEC_1 0x0
  25. #define JZ4740_REG_CODEC_2 0x1
  26. #define JZ4740_CODEC_1_LINE_ENABLE BIT(29)
  27. #define JZ4740_CODEC_1_MIC_ENABLE BIT(28)
  28. #define JZ4740_CODEC_1_SW1_ENABLE BIT(27)
  29. #define JZ4740_CODEC_1_ADC_ENABLE BIT(26)
  30. #define JZ4740_CODEC_1_SW2_ENABLE BIT(25)
  31. #define JZ4740_CODEC_1_DAC_ENABLE BIT(24)
  32. #define JZ4740_CODEC_1_VREF_DISABLE BIT(20)
  33. #define JZ4740_CODEC_1_VREF_AMP_DISABLE BIT(19)
  34. #define JZ4740_CODEC_1_VREF_PULLDOWN BIT(18)
  35. #define JZ4740_CODEC_1_VREF_LOW_CURRENT BIT(17)
  36. #define JZ4740_CODEC_1_VREF_HIGH_CURRENT BIT(16)
  37. #define JZ4740_CODEC_1_HEADPHONE_DISABLE BIT(14)
  38. #define JZ4740_CODEC_1_HEADPHONE_AMP_CHANGE_ANY BIT(13)
  39. #define JZ4740_CODEC_1_HEADPHONE_CHARGE BIT(12)
  40. #define JZ4740_CODEC_1_HEADPHONE_PULLDOWN (BIT(11) | BIT(10))
  41. #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M BIT(9)
  42. #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN BIT(8)
  43. #define JZ4740_CODEC_1_SUSPEND BIT(1)
  44. #define JZ4740_CODEC_1_RESET BIT(0)
  45. #define JZ4740_CODEC_1_LINE_ENABLE_OFFSET 29
  46. #define JZ4740_CODEC_1_MIC_ENABLE_OFFSET 28
  47. #define JZ4740_CODEC_1_SW1_ENABLE_OFFSET 27
  48. #define JZ4740_CODEC_1_ADC_ENABLE_OFFSET 26
  49. #define JZ4740_CODEC_1_SW2_ENABLE_OFFSET 25
  50. #define JZ4740_CODEC_1_DAC_ENABLE_OFFSET 24
  51. #define JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET 14
  52. #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET 8
  53. #define JZ4740_CODEC_2_INPUT_VOLUME_MASK 0x1f0000
  54. #define JZ4740_CODEC_2_SAMPLE_RATE_MASK 0x000f00
  55. #define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK 0x000030
  56. #define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK 0x000003
  57. #define JZ4740_CODEC_2_INPUT_VOLUME_OFFSET 16
  58. #define JZ4740_CODEC_2_SAMPLE_RATE_OFFSET 8
  59. #define JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET 4
  60. #define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET 0
  61. static const uint32_t jz4740_codec_regs[] = {
  62. 0x021b2302, 0x00170803,
  63. };
  64. struct jz4740_codec {
  65. void __iomem *base;
  66. struct resource *mem;
  67. };
  68. static unsigned int jz4740_codec_read(struct snd_soc_codec *codec,
  69. unsigned int reg)
  70. {
  71. struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec);
  72. return readl(jz4740_codec->base + (reg << 2));
  73. }
  74. static int jz4740_codec_write(struct snd_soc_codec *codec, unsigned int reg,
  75. unsigned int val)
  76. {
  77. struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec);
  78. u32 *cache = codec->reg_cache;
  79. cache[reg] = val;
  80. writel(val, jz4740_codec->base + (reg << 2));
  81. return 0;
  82. }
  83. static const struct snd_kcontrol_new jz4740_codec_controls[] = {
  84. SOC_SINGLE("Master Playback Volume", JZ4740_REG_CODEC_2,
  85. JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET, 3, 0),
  86. SOC_SINGLE("Master Capture Volume", JZ4740_REG_CODEC_2,
  87. JZ4740_CODEC_2_INPUT_VOLUME_OFFSET, 31, 0),
  88. SOC_SINGLE("Master Playback Switch", JZ4740_REG_CODEC_1,
  89. JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET, 1, 1),
  90. SOC_SINGLE("Mic Capture Volume", JZ4740_REG_CODEC_2,
  91. JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET, 3, 0),
  92. };
  93. static const struct snd_kcontrol_new jz4740_codec_output_controls[] = {
  94. SOC_DAPM_SINGLE("Bypass Switch", JZ4740_REG_CODEC_1,
  95. JZ4740_CODEC_1_SW1_ENABLE_OFFSET, 1, 0),
  96. SOC_DAPM_SINGLE("DAC Switch", JZ4740_REG_CODEC_1,
  97. JZ4740_CODEC_1_SW2_ENABLE_OFFSET, 1, 0),
  98. };
  99. static const struct snd_kcontrol_new jz4740_codec_input_controls[] = {
  100. SOC_DAPM_SINGLE("Line Capture Switch", JZ4740_REG_CODEC_1,
  101. JZ4740_CODEC_1_LINE_ENABLE_OFFSET, 1, 0),
  102. SOC_DAPM_SINGLE("Mic Capture Switch", JZ4740_REG_CODEC_1,
  103. JZ4740_CODEC_1_MIC_ENABLE_OFFSET, 1, 0),
  104. };
  105. static const struct snd_soc_dapm_widget jz4740_codec_dapm_widgets[] = {
  106. SND_SOC_DAPM_ADC("ADC", "Capture", JZ4740_REG_CODEC_1,
  107. JZ4740_CODEC_1_ADC_ENABLE_OFFSET, 0),
  108. SND_SOC_DAPM_DAC("DAC", "Playback", JZ4740_REG_CODEC_1,
  109. JZ4740_CODEC_1_DAC_ENABLE_OFFSET, 0),
  110. SND_SOC_DAPM_MIXER("Output Mixer", JZ4740_REG_CODEC_1,
  111. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET, 1,
  112. jz4740_codec_output_controls,
  113. ARRAY_SIZE(jz4740_codec_output_controls)),
  114. SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0,
  115. jz4740_codec_input_controls,
  116. ARRAY_SIZE(jz4740_codec_input_controls)),
  117. SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
  118. SND_SOC_DAPM_OUTPUT("LOUT"),
  119. SND_SOC_DAPM_OUTPUT("ROUT"),
  120. SND_SOC_DAPM_INPUT("MIC"),
  121. SND_SOC_DAPM_INPUT("LIN"),
  122. SND_SOC_DAPM_INPUT("RIN"),
  123. };
  124. static const struct snd_soc_dapm_route jz4740_codec_dapm_routes[] = {
  125. {"Line Input", NULL, "LIN"},
  126. {"Line Input", NULL, "RIN"},
  127. {"Input Mixer", "Line Capture Switch", "Line Input"},
  128. {"Input Mixer", "Mic Capture Switch", "MIC"},
  129. {"ADC", NULL, "Input Mixer"},
  130. {"Output Mixer", "Bypass Switch", "Input Mixer"},
  131. {"Output Mixer", "DAC Switch", "DAC"},
  132. {"LOUT", NULL, "Output Mixer"},
  133. {"ROUT", NULL, "Output Mixer"},
  134. };
  135. static int jz4740_codec_hw_params(struct snd_pcm_substream *substream,
  136. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  137. {
  138. uint32_t val;
  139. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  140. struct snd_soc_codec *codec =rtd->codec;
  141. switch (params_rate(params)) {
  142. case 8000:
  143. val = 0;
  144. break;
  145. case 11025:
  146. val = 1;
  147. break;
  148. case 12000:
  149. val = 2;
  150. break;
  151. case 16000:
  152. val = 3;
  153. break;
  154. case 22050:
  155. val = 4;
  156. break;
  157. case 24000:
  158. val = 5;
  159. break;
  160. case 32000:
  161. val = 6;
  162. break;
  163. case 44100:
  164. val = 7;
  165. break;
  166. case 48000:
  167. val = 8;
  168. break;
  169. default:
  170. return -EINVAL;
  171. }
  172. val <<= JZ4740_CODEC_2_SAMPLE_RATE_OFFSET;
  173. snd_soc_update_bits(codec, JZ4740_REG_CODEC_2,
  174. JZ4740_CODEC_2_SAMPLE_RATE_MASK, val);
  175. return 0;
  176. }
  177. static const struct snd_soc_dai_ops jz4740_codec_dai_ops = {
  178. .hw_params = jz4740_codec_hw_params,
  179. };
  180. static struct snd_soc_dai_driver jz4740_codec_dai = {
  181. .name = "jz4740-hifi",
  182. .playback = {
  183. .stream_name = "Playback",
  184. .channels_min = 2,
  185. .channels_max = 2,
  186. .rates = SNDRV_PCM_RATE_8000_48000,
  187. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
  188. },
  189. .capture = {
  190. .stream_name = "Capture",
  191. .channels_min = 2,
  192. .channels_max = 2,
  193. .rates = SNDRV_PCM_RATE_8000_48000,
  194. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
  195. },
  196. .ops = &jz4740_codec_dai_ops,
  197. .symmetric_rates = 1,
  198. };
  199. static void jz4740_codec_wakeup(struct snd_soc_codec *codec)
  200. {
  201. int i;
  202. uint32_t *cache = codec->reg_cache;
  203. snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
  204. JZ4740_CODEC_1_RESET, JZ4740_CODEC_1_RESET);
  205. udelay(2);
  206. snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
  207. JZ4740_CODEC_1_SUSPEND | JZ4740_CODEC_1_RESET, 0);
  208. for (i = 0; i < ARRAY_SIZE(jz4740_codec_regs); ++i)
  209. jz4740_codec_write(codec, i, cache[i]);
  210. }
  211. static int jz4740_codec_set_bias_level(struct snd_soc_codec *codec,
  212. enum snd_soc_bias_level level)
  213. {
  214. unsigned int mask;
  215. unsigned int value;
  216. switch (level) {
  217. case SND_SOC_BIAS_ON:
  218. break;
  219. case SND_SOC_BIAS_PREPARE:
  220. mask = JZ4740_CODEC_1_VREF_DISABLE |
  221. JZ4740_CODEC_1_VREF_AMP_DISABLE |
  222. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
  223. value = 0;
  224. snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value);
  225. break;
  226. case SND_SOC_BIAS_STANDBY:
  227. /* The only way to clear the suspend flag is to reset the codec */
  228. if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
  229. jz4740_codec_wakeup(codec);
  230. mask = JZ4740_CODEC_1_VREF_DISABLE |
  231. JZ4740_CODEC_1_VREF_AMP_DISABLE |
  232. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
  233. value = JZ4740_CODEC_1_VREF_DISABLE |
  234. JZ4740_CODEC_1_VREF_AMP_DISABLE |
  235. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
  236. snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value);
  237. break;
  238. case SND_SOC_BIAS_OFF:
  239. mask = JZ4740_CODEC_1_SUSPEND;
  240. value = JZ4740_CODEC_1_SUSPEND;
  241. snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value);
  242. break;
  243. default:
  244. break;
  245. }
  246. codec->dapm.bias_level = level;
  247. return 0;
  248. }
  249. static int jz4740_codec_dev_probe(struct snd_soc_codec *codec)
  250. {
  251. snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
  252. JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE);
  253. jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  254. return 0;
  255. }
  256. static int jz4740_codec_dev_remove(struct snd_soc_codec *codec)
  257. {
  258. jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
  259. return 0;
  260. }
  261. #ifdef CONFIG_PM_SLEEP
  262. static int jz4740_codec_suspend(struct snd_soc_codec *codec)
  263. {
  264. return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
  265. }
  266. static int jz4740_codec_resume(struct snd_soc_codec *codec)
  267. {
  268. return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  269. }
  270. #else
  271. #define jz4740_codec_suspend NULL
  272. #define jz4740_codec_resume NULL
  273. #endif
  274. static struct snd_soc_codec_driver soc_codec_dev_jz4740_codec = {
  275. .probe = jz4740_codec_dev_probe,
  276. .remove = jz4740_codec_dev_remove,
  277. .suspend = jz4740_codec_suspend,
  278. .resume = jz4740_codec_resume,
  279. .read = jz4740_codec_read,
  280. .write = jz4740_codec_write,
  281. .set_bias_level = jz4740_codec_set_bias_level,
  282. .reg_cache_default = jz4740_codec_regs,
  283. .reg_word_size = sizeof(u32),
  284. .reg_cache_size = 2,
  285. .controls = jz4740_codec_controls,
  286. .num_controls = ARRAY_SIZE(jz4740_codec_controls),
  287. .dapm_widgets = jz4740_codec_dapm_widgets,
  288. .num_dapm_widgets = ARRAY_SIZE(jz4740_codec_dapm_widgets),
  289. .dapm_routes = jz4740_codec_dapm_routes,
  290. .num_dapm_routes = ARRAY_SIZE(jz4740_codec_dapm_routes),
  291. };
  292. static int __devinit jz4740_codec_probe(struct platform_device *pdev)
  293. {
  294. int ret;
  295. struct jz4740_codec *jz4740_codec;
  296. struct resource *mem;
  297. jz4740_codec = devm_kzalloc(&pdev->dev, sizeof(*jz4740_codec),
  298. GFP_KERNEL);
  299. if (!jz4740_codec)
  300. return -ENOMEM;
  301. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  302. if (!mem) {
  303. dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
  304. ret = -ENOENT;
  305. goto err_out;
  306. }
  307. mem = request_mem_region(mem->start, resource_size(mem), pdev->name);
  308. if (!mem) {
  309. dev_err(&pdev->dev, "Failed to request mmio memory region\n");
  310. ret = -EBUSY;
  311. goto err_out;
  312. }
  313. jz4740_codec->base = ioremap(mem->start, resource_size(mem));
  314. if (!jz4740_codec->base) {
  315. dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
  316. ret = -EBUSY;
  317. goto err_release_mem_region;
  318. }
  319. jz4740_codec->mem = mem;
  320. platform_set_drvdata(pdev, jz4740_codec);
  321. ret = snd_soc_register_codec(&pdev->dev,
  322. &soc_codec_dev_jz4740_codec, &jz4740_codec_dai, 1);
  323. if (ret) {
  324. dev_err(&pdev->dev, "Failed to register codec\n");
  325. goto err_iounmap;
  326. }
  327. return 0;
  328. err_iounmap:
  329. iounmap(jz4740_codec->base);
  330. err_release_mem_region:
  331. release_mem_region(mem->start, resource_size(mem));
  332. err_out:
  333. return ret;
  334. }
  335. static int __devexit jz4740_codec_remove(struct platform_device *pdev)
  336. {
  337. struct jz4740_codec *jz4740_codec = platform_get_drvdata(pdev);
  338. struct resource *mem = jz4740_codec->mem;
  339. snd_soc_unregister_codec(&pdev->dev);
  340. iounmap(jz4740_codec->base);
  341. release_mem_region(mem->start, resource_size(mem));
  342. platform_set_drvdata(pdev, NULL);
  343. return 0;
  344. }
  345. static struct platform_driver jz4740_codec_driver = {
  346. .probe = jz4740_codec_probe,
  347. .remove = __devexit_p(jz4740_codec_remove),
  348. .driver = {
  349. .name = "jz4740-codec",
  350. .owner = THIS_MODULE,
  351. },
  352. };
  353. module_platform_driver(jz4740_codec_driver);
  354. MODULE_DESCRIPTION("JZ4740 SoC internal codec driver");
  355. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  356. MODULE_LICENSE("GPL v2");
  357. MODULE_ALIAS("platform:jz4740-codec");