bf5xx-sport.c 27 KB

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  1. /*
  2. * File: bf5xx_sport.c
  3. * Based on:
  4. * Author: Roy Huang <roy.huang@analog.com>
  5. *
  6. * Created: Tue Sep 21 10:52:42 CEST 2004
  7. * Description:
  8. * Blackfin SPORT Driver
  9. *
  10. * Copyright 2004-2007 Analog Devices Inc.
  11. *
  12. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, see the file COPYING, or write
  26. * to the Free Software Foundation, Inc.,
  27. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  28. */
  29. #include <linux/kernel.h>
  30. #include <linux/slab.h>
  31. #include <linux/delay.h>
  32. #include <linux/dma-mapping.h>
  33. #include <linux/gpio.h>
  34. #include <linux/bug.h>
  35. #include <linux/module.h>
  36. #include <asm/portmux.h>
  37. #include <asm/dma.h>
  38. #include <asm/blackfin.h>
  39. #include <asm/cacheflush.h>
  40. #include "bf5xx-sport.h"
  41. /* delay between frame sync pulse and first data bit in multichannel mode */
  42. #define FRAME_DELAY (1<<12)
  43. /* note: multichannel is in units of 8 channels,
  44. * tdm_count is # channels NOT / 8 ! */
  45. int sport_set_multichannel(struct sport_device *sport,
  46. int tdm_count, u32 mask, int packed)
  47. {
  48. pr_debug("%s tdm_count=%d mask:0x%08x packed=%d\n", __func__,
  49. tdm_count, mask, packed);
  50. if ((sport->regs->tcr1 & TSPEN) || (sport->regs->rcr1 & RSPEN))
  51. return -EBUSY;
  52. if (tdm_count & 0x7)
  53. return -EINVAL;
  54. if (tdm_count > 32)
  55. return -EINVAL; /* Only support less than 32 channels now */
  56. if (tdm_count) {
  57. sport->regs->mcmc1 = ((tdm_count>>3)-1) << 12;
  58. sport->regs->mcmc2 = FRAME_DELAY | MCMEN | \
  59. (packed ? (MCDTXPE|MCDRXPE) : 0);
  60. sport->regs->mtcs0 = mask;
  61. sport->regs->mrcs0 = mask;
  62. sport->regs->mtcs1 = 0;
  63. sport->regs->mrcs1 = 0;
  64. sport->regs->mtcs2 = 0;
  65. sport->regs->mrcs2 = 0;
  66. sport->regs->mtcs3 = 0;
  67. sport->regs->mrcs3 = 0;
  68. } else {
  69. sport->regs->mcmc1 = 0;
  70. sport->regs->mcmc2 = 0;
  71. sport->regs->mtcs0 = 0;
  72. sport->regs->mrcs0 = 0;
  73. }
  74. sport->regs->mtcs1 = 0; sport->regs->mtcs2 = 0; sport->regs->mtcs3 = 0;
  75. sport->regs->mrcs1 = 0; sport->regs->mrcs2 = 0; sport->regs->mrcs3 = 0;
  76. SSYNC();
  77. return 0;
  78. }
  79. EXPORT_SYMBOL(sport_set_multichannel);
  80. int sport_config_rx(struct sport_device *sport, unsigned int rcr1,
  81. unsigned int rcr2, unsigned int clkdiv, unsigned int fsdiv)
  82. {
  83. if ((sport->regs->tcr1 & TSPEN) || (sport->regs->rcr1 & RSPEN))
  84. return -EBUSY;
  85. sport->regs->rcr1 = rcr1;
  86. sport->regs->rcr2 = rcr2;
  87. sport->regs->rclkdiv = clkdiv;
  88. sport->regs->rfsdiv = fsdiv;
  89. SSYNC();
  90. return 0;
  91. }
  92. EXPORT_SYMBOL(sport_config_rx);
  93. int sport_config_tx(struct sport_device *sport, unsigned int tcr1,
  94. unsigned int tcr2, unsigned int clkdiv, unsigned int fsdiv)
  95. {
  96. if ((sport->regs->tcr1 & TSPEN) || (sport->regs->rcr1 & RSPEN))
  97. return -EBUSY;
  98. sport->regs->tcr1 = tcr1;
  99. sport->regs->tcr2 = tcr2;
  100. sport->regs->tclkdiv = clkdiv;
  101. sport->regs->tfsdiv = fsdiv;
  102. SSYNC();
  103. return 0;
  104. }
  105. EXPORT_SYMBOL(sport_config_tx);
  106. static void setup_desc(struct dmasg *desc, void *buf, int fragcount,
  107. size_t fragsize, unsigned int cfg,
  108. unsigned int x_count, unsigned int ycount, size_t wdsize)
  109. {
  110. int i;
  111. for (i = 0; i < fragcount; ++i) {
  112. desc[i].next_desc_addr = &(desc[i + 1]);
  113. desc[i].start_addr = (unsigned long)buf + i*fragsize;
  114. desc[i].cfg = cfg;
  115. desc[i].x_count = x_count;
  116. desc[i].x_modify = wdsize;
  117. desc[i].y_count = ycount;
  118. desc[i].y_modify = wdsize;
  119. }
  120. /* make circular */
  121. desc[fragcount-1].next_desc_addr = desc;
  122. pr_debug("setup desc: desc0=%p, next0=%p, desc1=%p,"
  123. "next1=%p\nx_count=%x,y_count=%x,addr=0x%lx,cfs=0x%x\n",
  124. desc, desc[0].next_desc_addr,
  125. desc+1, desc[1].next_desc_addr,
  126. desc[0].x_count, desc[0].y_count,
  127. desc[0].start_addr, desc[0].cfg);
  128. }
  129. static int sport_start(struct sport_device *sport)
  130. {
  131. enable_dma(sport->dma_rx_chan);
  132. enable_dma(sport->dma_tx_chan);
  133. sport->regs->rcr1 |= RSPEN;
  134. sport->regs->tcr1 |= TSPEN;
  135. SSYNC();
  136. return 0;
  137. }
  138. static int sport_stop(struct sport_device *sport)
  139. {
  140. sport->regs->tcr1 &= ~TSPEN;
  141. sport->regs->rcr1 &= ~RSPEN;
  142. SSYNC();
  143. disable_dma(sport->dma_rx_chan);
  144. disable_dma(sport->dma_tx_chan);
  145. return 0;
  146. }
  147. static inline int sport_hook_rx_dummy(struct sport_device *sport)
  148. {
  149. struct dmasg *desc, temp_desc;
  150. unsigned long flags;
  151. BUG_ON(sport->dummy_rx_desc == NULL);
  152. BUG_ON(sport->curr_rx_desc == sport->dummy_rx_desc);
  153. /* Maybe the dummy buffer descriptor ring is damaged */
  154. sport->dummy_rx_desc->next_desc_addr = sport->dummy_rx_desc + 1;
  155. local_irq_save(flags);
  156. desc = get_dma_next_desc_ptr(sport->dma_rx_chan);
  157. /* Copy the descriptor which will be damaged to backup */
  158. temp_desc = *desc;
  159. desc->x_count = sport->dummy_count / 2;
  160. desc->y_count = 0;
  161. desc->next_desc_addr = sport->dummy_rx_desc;
  162. local_irq_restore(flags);
  163. /* Waiting for dummy buffer descriptor is already hooked*/
  164. while ((get_dma_curr_desc_ptr(sport->dma_rx_chan) -
  165. sizeof(struct dmasg)) != sport->dummy_rx_desc)
  166. continue;
  167. sport->curr_rx_desc = sport->dummy_rx_desc;
  168. /* Restore the damaged descriptor */
  169. *desc = temp_desc;
  170. return 0;
  171. }
  172. static inline int sport_rx_dma_start(struct sport_device *sport, int dummy)
  173. {
  174. if (dummy) {
  175. sport->dummy_rx_desc->next_desc_addr = sport->dummy_rx_desc;
  176. sport->curr_rx_desc = sport->dummy_rx_desc;
  177. } else
  178. sport->curr_rx_desc = sport->dma_rx_desc;
  179. set_dma_next_desc_addr(sport->dma_rx_chan, sport->curr_rx_desc);
  180. set_dma_x_count(sport->dma_rx_chan, 0);
  181. set_dma_x_modify(sport->dma_rx_chan, 0);
  182. set_dma_config(sport->dma_rx_chan, (DMAFLOW_LARGE | NDSIZE_9 | \
  183. WDSIZE_32 | WNR));
  184. set_dma_curr_addr(sport->dma_rx_chan, sport->curr_rx_desc->start_addr);
  185. SSYNC();
  186. return 0;
  187. }
  188. static inline int sport_tx_dma_start(struct sport_device *sport, int dummy)
  189. {
  190. if (dummy) {
  191. sport->dummy_tx_desc->next_desc_addr = sport->dummy_tx_desc;
  192. sport->curr_tx_desc = sport->dummy_tx_desc;
  193. } else
  194. sport->curr_tx_desc = sport->dma_tx_desc;
  195. set_dma_next_desc_addr(sport->dma_tx_chan, sport->curr_tx_desc);
  196. set_dma_x_count(sport->dma_tx_chan, 0);
  197. set_dma_x_modify(sport->dma_tx_chan, 0);
  198. set_dma_config(sport->dma_tx_chan,
  199. (DMAFLOW_LARGE | NDSIZE_9 | WDSIZE_32));
  200. set_dma_curr_addr(sport->dma_tx_chan, sport->curr_tx_desc->start_addr);
  201. SSYNC();
  202. return 0;
  203. }
  204. int sport_rx_start(struct sport_device *sport)
  205. {
  206. unsigned long flags;
  207. pr_debug("%s enter\n", __func__);
  208. if (sport->rx_run)
  209. return -EBUSY;
  210. if (sport->tx_run) {
  211. /* tx is running, rx is not running */
  212. BUG_ON(sport->dma_rx_desc == NULL);
  213. BUG_ON(sport->curr_rx_desc != sport->dummy_rx_desc);
  214. local_irq_save(flags);
  215. while ((get_dma_curr_desc_ptr(sport->dma_rx_chan) -
  216. sizeof(struct dmasg)) != sport->dummy_rx_desc)
  217. continue;
  218. sport->dummy_rx_desc->next_desc_addr = sport->dma_rx_desc;
  219. local_irq_restore(flags);
  220. sport->curr_rx_desc = sport->dma_rx_desc;
  221. } else {
  222. sport_tx_dma_start(sport, 1);
  223. sport_rx_dma_start(sport, 0);
  224. sport_start(sport);
  225. }
  226. sport->rx_run = 1;
  227. return 0;
  228. }
  229. EXPORT_SYMBOL(sport_rx_start);
  230. int sport_rx_stop(struct sport_device *sport)
  231. {
  232. pr_debug("%s enter\n", __func__);
  233. if (!sport->rx_run)
  234. return 0;
  235. if (sport->tx_run) {
  236. /* TX dma is still running, hook the dummy buffer */
  237. sport_hook_rx_dummy(sport);
  238. } else {
  239. /* Both rx and tx dma will be stopped */
  240. sport_stop(sport);
  241. sport->curr_rx_desc = NULL;
  242. sport->curr_tx_desc = NULL;
  243. }
  244. sport->rx_run = 0;
  245. return 0;
  246. }
  247. EXPORT_SYMBOL(sport_rx_stop);
  248. static inline int sport_hook_tx_dummy(struct sport_device *sport)
  249. {
  250. struct dmasg *desc, temp_desc;
  251. unsigned long flags;
  252. BUG_ON(sport->dummy_tx_desc == NULL);
  253. BUG_ON(sport->curr_tx_desc == sport->dummy_tx_desc);
  254. sport->dummy_tx_desc->next_desc_addr = sport->dummy_tx_desc + 1;
  255. /* Shorten the time on last normal descriptor */
  256. local_irq_save(flags);
  257. desc = get_dma_next_desc_ptr(sport->dma_tx_chan);
  258. /* Store the descriptor which will be damaged */
  259. temp_desc = *desc;
  260. desc->x_count = sport->dummy_count / 2;
  261. desc->y_count = 0;
  262. desc->next_desc_addr = sport->dummy_tx_desc;
  263. local_irq_restore(flags);
  264. /* Waiting for dummy buffer descriptor is already hooked*/
  265. while ((get_dma_curr_desc_ptr(sport->dma_tx_chan) - \
  266. sizeof(struct dmasg)) != sport->dummy_tx_desc)
  267. continue;
  268. sport->curr_tx_desc = sport->dummy_tx_desc;
  269. /* Restore the damaged descriptor */
  270. *desc = temp_desc;
  271. return 0;
  272. }
  273. int sport_tx_start(struct sport_device *sport)
  274. {
  275. unsigned long flags;
  276. pr_debug("%s: tx_run:%d, rx_run:%d\n", __func__,
  277. sport->tx_run, sport->rx_run);
  278. if (sport->tx_run)
  279. return -EBUSY;
  280. if (sport->rx_run) {
  281. BUG_ON(sport->dma_tx_desc == NULL);
  282. BUG_ON(sport->curr_tx_desc != sport->dummy_tx_desc);
  283. /* Hook the normal buffer descriptor */
  284. local_irq_save(flags);
  285. while ((get_dma_curr_desc_ptr(sport->dma_tx_chan) -
  286. sizeof(struct dmasg)) != sport->dummy_tx_desc)
  287. continue;
  288. sport->dummy_tx_desc->next_desc_addr = sport->dma_tx_desc;
  289. local_irq_restore(flags);
  290. sport->curr_tx_desc = sport->dma_tx_desc;
  291. } else {
  292. sport_tx_dma_start(sport, 0);
  293. /* Let rx dma run the dummy buffer */
  294. sport_rx_dma_start(sport, 1);
  295. sport_start(sport);
  296. }
  297. sport->tx_run = 1;
  298. return 0;
  299. }
  300. EXPORT_SYMBOL(sport_tx_start);
  301. int sport_tx_stop(struct sport_device *sport)
  302. {
  303. if (!sport->tx_run)
  304. return 0;
  305. if (sport->rx_run) {
  306. /* RX is still running, hook the dummy buffer */
  307. sport_hook_tx_dummy(sport);
  308. } else {
  309. /* Both rx and tx dma stopped */
  310. sport_stop(sport);
  311. sport->curr_rx_desc = NULL;
  312. sport->curr_tx_desc = NULL;
  313. }
  314. sport->tx_run = 0;
  315. return 0;
  316. }
  317. EXPORT_SYMBOL(sport_tx_stop);
  318. static inline int compute_wdsize(size_t wdsize)
  319. {
  320. switch (wdsize) {
  321. case 1:
  322. return WDSIZE_8;
  323. case 2:
  324. return WDSIZE_16;
  325. case 4:
  326. default:
  327. return WDSIZE_32;
  328. }
  329. }
  330. int sport_config_rx_dma(struct sport_device *sport, void *buf,
  331. int fragcount, size_t fragsize)
  332. {
  333. unsigned int x_count;
  334. unsigned int y_count;
  335. unsigned int cfg;
  336. dma_addr_t addr;
  337. pr_debug("%s buf:%p, frag:%d, fragsize:0x%lx\n", __func__, \
  338. buf, fragcount, fragsize);
  339. x_count = fragsize / sport->wdsize;
  340. y_count = 0;
  341. /* for fragments larger than 64k words we use 2d dma,
  342. * denote fragecount as two numbers' mutliply and both of them
  343. * are less than 64k.*/
  344. if (x_count >= 0x10000) {
  345. int i, count = x_count;
  346. for (i = 16; i > 0; i--) {
  347. x_count = 1 << i;
  348. if ((count & (x_count - 1)) == 0) {
  349. y_count = count >> i;
  350. if (y_count < 0x10000)
  351. break;
  352. }
  353. }
  354. if (i == 0)
  355. return -EINVAL;
  356. }
  357. pr_debug("%s(x_count:0x%x, y_count:0x%x)\n", __func__,
  358. x_count, y_count);
  359. if (sport->dma_rx_desc)
  360. dma_free_coherent(NULL, sport->rx_desc_bytes,
  361. sport->dma_rx_desc, 0);
  362. /* Allocate a new descritor ring as current one. */
  363. sport->dma_rx_desc = dma_alloc_coherent(NULL, \
  364. fragcount * sizeof(struct dmasg), &addr, 0);
  365. sport->rx_desc_bytes = fragcount * sizeof(struct dmasg);
  366. if (!sport->dma_rx_desc) {
  367. pr_err("Failed to allocate memory for rx desc\n");
  368. return -ENOMEM;
  369. }
  370. sport->rx_buf = buf;
  371. sport->rx_fragsize = fragsize;
  372. sport->rx_frags = fragcount;
  373. cfg = 0x7000 | DI_EN | compute_wdsize(sport->wdsize) | WNR | \
  374. (DESC_ELEMENT_COUNT << 8); /* large descriptor mode */
  375. if (y_count != 0)
  376. cfg |= DMA2D;
  377. setup_desc(sport->dma_rx_desc, buf, fragcount, fragsize,
  378. cfg|DMAEN, x_count, y_count, sport->wdsize);
  379. return 0;
  380. }
  381. EXPORT_SYMBOL(sport_config_rx_dma);
  382. int sport_config_tx_dma(struct sport_device *sport, void *buf, \
  383. int fragcount, size_t fragsize)
  384. {
  385. unsigned int x_count;
  386. unsigned int y_count;
  387. unsigned int cfg;
  388. dma_addr_t addr;
  389. pr_debug("%s buf:%p, fragcount:%d, fragsize:0x%lx\n",
  390. __func__, buf, fragcount, fragsize);
  391. x_count = fragsize/sport->wdsize;
  392. y_count = 0;
  393. /* for fragments larger than 64k words we use 2d dma,
  394. * denote fragecount as two numbers' mutliply and both of them
  395. * are less than 64k.*/
  396. if (x_count >= 0x10000) {
  397. int i, count = x_count;
  398. for (i = 16; i > 0; i--) {
  399. x_count = 1 << i;
  400. if ((count & (x_count - 1)) == 0) {
  401. y_count = count >> i;
  402. if (y_count < 0x10000)
  403. break;
  404. }
  405. }
  406. if (i == 0)
  407. return -EINVAL;
  408. }
  409. pr_debug("%s x_count:0x%x, y_count:0x%x\n", __func__,
  410. x_count, y_count);
  411. if (sport->dma_tx_desc) {
  412. dma_free_coherent(NULL, sport->tx_desc_bytes, \
  413. sport->dma_tx_desc, 0);
  414. }
  415. sport->dma_tx_desc = dma_alloc_coherent(NULL, \
  416. fragcount * sizeof(struct dmasg), &addr, 0);
  417. sport->tx_desc_bytes = fragcount * sizeof(struct dmasg);
  418. if (!sport->dma_tx_desc) {
  419. pr_err("Failed to allocate memory for tx desc\n");
  420. return -ENOMEM;
  421. }
  422. sport->tx_buf = buf;
  423. sport->tx_fragsize = fragsize;
  424. sport->tx_frags = fragcount;
  425. cfg = 0x7000 | DI_EN | compute_wdsize(sport->wdsize) | \
  426. (DESC_ELEMENT_COUNT << 8); /* large descriptor mode */
  427. if (y_count != 0)
  428. cfg |= DMA2D;
  429. setup_desc(sport->dma_tx_desc, buf, fragcount, fragsize,
  430. cfg|DMAEN, x_count, y_count, sport->wdsize);
  431. return 0;
  432. }
  433. EXPORT_SYMBOL(sport_config_tx_dma);
  434. /* setup dummy dma descriptor ring, which don't generate interrupts,
  435. * the x_modify is set to 0 */
  436. static int sport_config_rx_dummy(struct sport_device *sport)
  437. {
  438. struct dmasg *desc;
  439. unsigned config;
  440. pr_debug("%s entered\n", __func__);
  441. if (L1_DATA_A_LENGTH)
  442. desc = l1_data_sram_zalloc(2 * sizeof(*desc));
  443. else {
  444. dma_addr_t addr;
  445. desc = dma_alloc_coherent(NULL, 2 * sizeof(*desc), &addr, 0);
  446. memset(desc, 0, 2 * sizeof(*desc));
  447. }
  448. if (desc == NULL) {
  449. pr_err("Failed to allocate memory for dummy rx desc\n");
  450. return -ENOMEM;
  451. }
  452. sport->dummy_rx_desc = desc;
  453. desc->start_addr = (unsigned long)sport->dummy_buf;
  454. config = DMAFLOW_LARGE | NDSIZE_9 | compute_wdsize(sport->wdsize)
  455. | WNR | DMAEN;
  456. desc->cfg = config;
  457. desc->x_count = sport->dummy_count/sport->wdsize;
  458. desc->x_modify = sport->wdsize;
  459. desc->y_count = 0;
  460. desc->y_modify = 0;
  461. memcpy(desc+1, desc, sizeof(*desc));
  462. desc->next_desc_addr = desc + 1;
  463. desc[1].next_desc_addr = desc;
  464. return 0;
  465. }
  466. static int sport_config_tx_dummy(struct sport_device *sport)
  467. {
  468. struct dmasg *desc;
  469. unsigned int config;
  470. pr_debug("%s entered\n", __func__);
  471. if (L1_DATA_A_LENGTH)
  472. desc = l1_data_sram_zalloc(2 * sizeof(*desc));
  473. else {
  474. dma_addr_t addr;
  475. desc = dma_alloc_coherent(NULL, 2 * sizeof(*desc), &addr, 0);
  476. memset(desc, 0, 2 * sizeof(*desc));
  477. }
  478. if (!desc) {
  479. pr_err("Failed to allocate memory for dummy tx desc\n");
  480. return -ENOMEM;
  481. }
  482. sport->dummy_tx_desc = desc;
  483. desc->start_addr = (unsigned long)sport->dummy_buf + \
  484. sport->dummy_count;
  485. config = DMAFLOW_LARGE | NDSIZE_9 |
  486. compute_wdsize(sport->wdsize) | DMAEN;
  487. desc->cfg = config;
  488. desc->x_count = sport->dummy_count/sport->wdsize;
  489. desc->x_modify = sport->wdsize;
  490. desc->y_count = 0;
  491. desc->y_modify = 0;
  492. memcpy(desc+1, desc, sizeof(*desc));
  493. desc->next_desc_addr = desc + 1;
  494. desc[1].next_desc_addr = desc;
  495. return 0;
  496. }
  497. unsigned long sport_curr_offset_rx(struct sport_device *sport)
  498. {
  499. unsigned long curr = get_dma_curr_addr(sport->dma_rx_chan);
  500. return (unsigned char *)curr - sport->rx_buf;
  501. }
  502. EXPORT_SYMBOL(sport_curr_offset_rx);
  503. unsigned long sport_curr_offset_tx(struct sport_device *sport)
  504. {
  505. unsigned long curr = get_dma_curr_addr(sport->dma_tx_chan);
  506. return (unsigned char *)curr - sport->tx_buf;
  507. }
  508. EXPORT_SYMBOL(sport_curr_offset_tx);
  509. void sport_incfrag(struct sport_device *sport, int *frag, int tx)
  510. {
  511. ++(*frag);
  512. if (tx == 1 && *frag == sport->tx_frags)
  513. *frag = 0;
  514. if (tx == 0 && *frag == sport->rx_frags)
  515. *frag = 0;
  516. }
  517. EXPORT_SYMBOL(sport_incfrag);
  518. void sport_decfrag(struct sport_device *sport, int *frag, int tx)
  519. {
  520. --(*frag);
  521. if (tx == 1 && *frag == 0)
  522. *frag = sport->tx_frags;
  523. if (tx == 0 && *frag == 0)
  524. *frag = sport->rx_frags;
  525. }
  526. EXPORT_SYMBOL(sport_decfrag);
  527. static int sport_check_status(struct sport_device *sport,
  528. unsigned int *sport_stat,
  529. unsigned int *rx_stat,
  530. unsigned int *tx_stat)
  531. {
  532. int status = 0;
  533. if (sport_stat) {
  534. SSYNC();
  535. status = sport->regs->stat;
  536. if (status & (TOVF|TUVF|ROVF|RUVF))
  537. sport->regs->stat = (status & (TOVF|TUVF|ROVF|RUVF));
  538. SSYNC();
  539. *sport_stat = status;
  540. }
  541. if (rx_stat) {
  542. SSYNC();
  543. status = get_dma_curr_irqstat(sport->dma_rx_chan);
  544. if (status & (DMA_DONE|DMA_ERR))
  545. clear_dma_irqstat(sport->dma_rx_chan);
  546. SSYNC();
  547. *rx_stat = status;
  548. }
  549. if (tx_stat) {
  550. SSYNC();
  551. status = get_dma_curr_irqstat(sport->dma_tx_chan);
  552. if (status & (DMA_DONE|DMA_ERR))
  553. clear_dma_irqstat(sport->dma_tx_chan);
  554. SSYNC();
  555. *tx_stat = status;
  556. }
  557. return 0;
  558. }
  559. int sport_dump_stat(struct sport_device *sport, char *buf, size_t len)
  560. {
  561. int ret;
  562. ret = snprintf(buf, len,
  563. "sts: 0x%04x\n"
  564. "rx dma %d sts: 0x%04x tx dma %d sts: 0x%04x\n",
  565. sport->regs->stat,
  566. sport->dma_rx_chan,
  567. get_dma_curr_irqstat(sport->dma_rx_chan),
  568. sport->dma_tx_chan,
  569. get_dma_curr_irqstat(sport->dma_tx_chan));
  570. buf += ret;
  571. len -= ret;
  572. ret += snprintf(buf, len,
  573. "curr_rx_desc:0x%p, curr_tx_desc:0x%p\n"
  574. "dma_rx_desc:0x%p, dma_tx_desc:0x%p\n"
  575. "dummy_rx_desc:0x%p, dummy_tx_desc:0x%p\n",
  576. sport->curr_rx_desc, sport->curr_tx_desc,
  577. sport->dma_rx_desc, sport->dma_tx_desc,
  578. sport->dummy_rx_desc, sport->dummy_tx_desc);
  579. return ret;
  580. }
  581. static irqreturn_t rx_handler(int irq, void *dev_id)
  582. {
  583. unsigned int rx_stat;
  584. struct sport_device *sport = dev_id;
  585. pr_debug("%s enter\n", __func__);
  586. sport_check_status(sport, NULL, &rx_stat, NULL);
  587. if (!(rx_stat & DMA_DONE))
  588. pr_err("rx dma is already stopped\n");
  589. if (sport->rx_callback) {
  590. sport->rx_callback(sport->rx_data);
  591. return IRQ_HANDLED;
  592. }
  593. return IRQ_NONE;
  594. }
  595. static irqreturn_t tx_handler(int irq, void *dev_id)
  596. {
  597. unsigned int tx_stat;
  598. struct sport_device *sport = dev_id;
  599. pr_debug("%s enter\n", __func__);
  600. sport_check_status(sport, NULL, NULL, &tx_stat);
  601. if (!(tx_stat & DMA_DONE)) {
  602. pr_err("tx dma is already stopped\n");
  603. return IRQ_HANDLED;
  604. }
  605. if (sport->tx_callback) {
  606. sport->tx_callback(sport->tx_data);
  607. return IRQ_HANDLED;
  608. }
  609. return IRQ_NONE;
  610. }
  611. static irqreturn_t err_handler(int irq, void *dev_id)
  612. {
  613. unsigned int status = 0;
  614. struct sport_device *sport = dev_id;
  615. pr_debug("%s\n", __func__);
  616. if (sport_check_status(sport, &status, NULL, NULL)) {
  617. pr_err("error checking status ??");
  618. return IRQ_NONE;
  619. }
  620. if (status & (TOVF|TUVF|ROVF|RUVF)) {
  621. pr_info("sport status error:%s%s%s%s\n",
  622. status & TOVF ? " TOVF" : "",
  623. status & TUVF ? " TUVF" : "",
  624. status & ROVF ? " ROVF" : "",
  625. status & RUVF ? " RUVF" : "");
  626. if (status & TOVF || status & TUVF) {
  627. disable_dma(sport->dma_tx_chan);
  628. if (sport->tx_run)
  629. sport_tx_dma_start(sport, 0);
  630. else
  631. sport_tx_dma_start(sport, 1);
  632. enable_dma(sport->dma_tx_chan);
  633. } else {
  634. disable_dma(sport->dma_rx_chan);
  635. if (sport->rx_run)
  636. sport_rx_dma_start(sport, 0);
  637. else
  638. sport_rx_dma_start(sport, 1);
  639. enable_dma(sport->dma_rx_chan);
  640. }
  641. }
  642. status = sport->regs->stat;
  643. if (status & (TOVF|TUVF|ROVF|RUVF))
  644. sport->regs->stat = (status & (TOVF|TUVF|ROVF|RUVF));
  645. SSYNC();
  646. if (sport->err_callback)
  647. sport->err_callback(sport->err_data);
  648. return IRQ_HANDLED;
  649. }
  650. int sport_set_rx_callback(struct sport_device *sport,
  651. void (*rx_callback)(void *), void *rx_data)
  652. {
  653. BUG_ON(rx_callback == NULL);
  654. sport->rx_callback = rx_callback;
  655. sport->rx_data = rx_data;
  656. return 0;
  657. }
  658. EXPORT_SYMBOL(sport_set_rx_callback);
  659. int sport_set_tx_callback(struct sport_device *sport,
  660. void (*tx_callback)(void *), void *tx_data)
  661. {
  662. BUG_ON(tx_callback == NULL);
  663. sport->tx_callback = tx_callback;
  664. sport->tx_data = tx_data;
  665. return 0;
  666. }
  667. EXPORT_SYMBOL(sport_set_tx_callback);
  668. int sport_set_err_callback(struct sport_device *sport,
  669. void (*err_callback)(void *), void *err_data)
  670. {
  671. BUG_ON(err_callback == NULL);
  672. sport->err_callback = err_callback;
  673. sport->err_data = err_data;
  674. return 0;
  675. }
  676. EXPORT_SYMBOL(sport_set_err_callback);
  677. static int sport_config_pdev(struct platform_device *pdev, struct sport_param *param)
  678. {
  679. /* Extract settings from platform data */
  680. struct device *dev = &pdev->dev;
  681. struct bfin_snd_platform_data *pdata = dev->platform_data;
  682. struct resource *res;
  683. param->num = pdev->id;
  684. if (!pdata) {
  685. dev_err(dev, "no platform_data\n");
  686. return -ENODEV;
  687. }
  688. param->pin_req = pdata->pin_req;
  689. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  690. if (!res) {
  691. dev_err(dev, "no MEM resource\n");
  692. return -ENODEV;
  693. }
  694. param->regs = (struct sport_register *)res->start;
  695. /* first RX, then TX */
  696. res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  697. if (!res) {
  698. dev_err(dev, "no rx DMA resource\n");
  699. return -ENODEV;
  700. }
  701. param->dma_rx_chan = res->start;
  702. res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  703. if (!res) {
  704. dev_err(dev, "no tx DMA resource\n");
  705. return -ENODEV;
  706. }
  707. param->dma_tx_chan = res->start;
  708. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  709. if (!res) {
  710. dev_err(dev, "no irq resource\n");
  711. return -ENODEV;
  712. }
  713. param->err_irq = res->start;
  714. return 0;
  715. }
  716. struct sport_device *sport_init(struct platform_device *pdev,
  717. unsigned int wdsize, unsigned int dummy_count, size_t priv_size)
  718. {
  719. struct device *dev = &pdev->dev;
  720. struct sport_param param;
  721. struct sport_device *sport;
  722. int ret;
  723. dev_dbg(dev, "%s enter\n", __func__);
  724. param.wdsize = wdsize;
  725. param.dummy_count = dummy_count;
  726. BUG_ON(param.wdsize == 0 || param.dummy_count == 0);
  727. ret = sport_config_pdev(pdev, &param);
  728. if (ret)
  729. return NULL;
  730. if (peripheral_request_list(param.pin_req, "soc-audio")) {
  731. dev_err(dev, "requesting Peripherals failed\n");
  732. return NULL;
  733. }
  734. sport = kzalloc(sizeof(*sport), GFP_KERNEL);
  735. if (!sport) {
  736. dev_err(dev, "failed to allocate for sport device\n");
  737. goto __init_err0;
  738. }
  739. sport->num = param.num;
  740. sport->dma_rx_chan = param.dma_rx_chan;
  741. sport->dma_tx_chan = param.dma_tx_chan;
  742. sport->err_irq = param.err_irq;
  743. sport->regs = param.regs;
  744. sport->pin_req = param.pin_req;
  745. if (request_dma(sport->dma_rx_chan, "SPORT RX Data") == -EBUSY) {
  746. dev_err(dev, "failed to request RX dma %d\n", sport->dma_rx_chan);
  747. goto __init_err1;
  748. }
  749. if (set_dma_callback(sport->dma_rx_chan, rx_handler, sport) != 0) {
  750. dev_err(dev, "failed to request RX irq %d\n", sport->dma_rx_chan);
  751. goto __init_err2;
  752. }
  753. if (request_dma(sport->dma_tx_chan, "SPORT TX Data") == -EBUSY) {
  754. dev_err(dev, "failed to request TX dma %d\n", sport->dma_tx_chan);
  755. goto __init_err2;
  756. }
  757. if (set_dma_callback(sport->dma_tx_chan, tx_handler, sport) != 0) {
  758. dev_err(dev, "failed to request TX irq %d\n", sport->dma_tx_chan);
  759. goto __init_err3;
  760. }
  761. if (request_irq(sport->err_irq, err_handler, IRQF_SHARED, "SPORT err",
  762. sport) < 0) {
  763. dev_err(dev, "failed to request err irq %d\n", sport->err_irq);
  764. goto __init_err3;
  765. }
  766. dev_info(dev, "dma rx:%d tx:%d, err irq:%d, regs:%p\n",
  767. sport->dma_rx_chan, sport->dma_tx_chan,
  768. sport->err_irq, sport->regs);
  769. sport->wdsize = param.wdsize;
  770. sport->dummy_count = param.dummy_count;
  771. sport->private_data = kzalloc(priv_size, GFP_KERNEL);
  772. if (!sport->private_data) {
  773. dev_err(dev, "could not alloc priv data %zu bytes\n", priv_size);
  774. goto __init_err4;
  775. }
  776. if (L1_DATA_A_LENGTH)
  777. sport->dummy_buf = l1_data_sram_zalloc(param.dummy_count * 2);
  778. else
  779. sport->dummy_buf = kzalloc(param.dummy_count * 2, GFP_KERNEL);
  780. if (sport->dummy_buf == NULL) {
  781. dev_err(dev, "failed to allocate dummy buffer\n");
  782. goto __error1;
  783. }
  784. ret = sport_config_rx_dummy(sport);
  785. if (ret) {
  786. dev_err(dev, "failed to config rx dummy ring\n");
  787. goto __error2;
  788. }
  789. ret = sport_config_tx_dummy(sport);
  790. if (ret) {
  791. dev_err(dev, "failed to config tx dummy ring\n");
  792. goto __error3;
  793. }
  794. platform_set_drvdata(pdev, sport);
  795. return sport;
  796. __error3:
  797. if (L1_DATA_A_LENGTH)
  798. l1_data_sram_free(sport->dummy_rx_desc);
  799. else
  800. dma_free_coherent(NULL, 2*sizeof(struct dmasg),
  801. sport->dummy_rx_desc, 0);
  802. __error2:
  803. if (L1_DATA_A_LENGTH)
  804. l1_data_sram_free(sport->dummy_buf);
  805. else
  806. kfree(sport->dummy_buf);
  807. __error1:
  808. kfree(sport->private_data);
  809. __init_err4:
  810. free_irq(sport->err_irq, sport);
  811. __init_err3:
  812. free_dma(sport->dma_tx_chan);
  813. __init_err2:
  814. free_dma(sport->dma_rx_chan);
  815. __init_err1:
  816. kfree(sport);
  817. __init_err0:
  818. peripheral_free_list(param.pin_req);
  819. return NULL;
  820. }
  821. EXPORT_SYMBOL(sport_init);
  822. void sport_done(struct sport_device *sport)
  823. {
  824. if (sport == NULL)
  825. return;
  826. sport_stop(sport);
  827. if (sport->dma_rx_desc)
  828. dma_free_coherent(NULL, sport->rx_desc_bytes,
  829. sport->dma_rx_desc, 0);
  830. if (sport->dma_tx_desc)
  831. dma_free_coherent(NULL, sport->tx_desc_bytes,
  832. sport->dma_tx_desc, 0);
  833. #if L1_DATA_A_LENGTH != 0
  834. l1_data_sram_free(sport->dummy_rx_desc);
  835. l1_data_sram_free(sport->dummy_tx_desc);
  836. l1_data_sram_free(sport->dummy_buf);
  837. #else
  838. dma_free_coherent(NULL, 2*sizeof(struct dmasg),
  839. sport->dummy_rx_desc, 0);
  840. dma_free_coherent(NULL, 2*sizeof(struct dmasg),
  841. sport->dummy_tx_desc, 0);
  842. kfree(sport->dummy_buf);
  843. #endif
  844. free_dma(sport->dma_rx_chan);
  845. free_dma(sport->dma_tx_chan);
  846. free_irq(sport->err_irq, sport);
  847. kfree(sport->private_data);
  848. peripheral_free_list(sport->pin_req);
  849. kfree(sport);
  850. }
  851. EXPORT_SYMBOL(sport_done);
  852. /*
  853. * It is only used to send several bytes when dma is not enabled
  854. * sport controller is configured but not enabled.
  855. * Multichannel cannot works with pio mode */
  856. /* Used by ac97 to write and read codec register */
  857. int sport_send_and_recv(struct sport_device *sport, u8 *out_data, \
  858. u8 *in_data, int len)
  859. {
  860. unsigned short dma_config;
  861. unsigned short status;
  862. unsigned long flags;
  863. unsigned long wait = 0;
  864. pr_debug("%s enter, out_data:%p, in_data:%p len:%d\n", \
  865. __func__, out_data, in_data, len);
  866. pr_debug("tcr1:0x%04x, tcr2:0x%04x, tclkdiv:0x%04x, tfsdiv:0x%04x\n"
  867. "mcmc1:0x%04x, mcmc2:0x%04x\n",
  868. sport->regs->tcr1, sport->regs->tcr2,
  869. sport->regs->tclkdiv, sport->regs->tfsdiv,
  870. sport->regs->mcmc1, sport->regs->mcmc2);
  871. flush_dcache_range((unsigned)out_data, (unsigned)(out_data + len));
  872. /* Enable tx dma */
  873. dma_config = (RESTART | WDSIZE_16 | DI_EN);
  874. set_dma_start_addr(sport->dma_tx_chan, (unsigned long)out_data);
  875. set_dma_x_count(sport->dma_tx_chan, len/2);
  876. set_dma_x_modify(sport->dma_tx_chan, 2);
  877. set_dma_config(sport->dma_tx_chan, dma_config);
  878. enable_dma(sport->dma_tx_chan);
  879. if (in_data != NULL) {
  880. invalidate_dcache_range((unsigned)in_data, \
  881. (unsigned)(in_data + len));
  882. /* Enable rx dma */
  883. dma_config = (RESTART | WDSIZE_16 | WNR | DI_EN);
  884. set_dma_start_addr(sport->dma_rx_chan, (unsigned long)in_data);
  885. set_dma_x_count(sport->dma_rx_chan, len/2);
  886. set_dma_x_modify(sport->dma_rx_chan, 2);
  887. set_dma_config(sport->dma_rx_chan, dma_config);
  888. enable_dma(sport->dma_rx_chan);
  889. }
  890. local_irq_save(flags);
  891. sport->regs->tcr1 |= TSPEN;
  892. sport->regs->rcr1 |= RSPEN;
  893. SSYNC();
  894. status = get_dma_curr_irqstat(sport->dma_tx_chan);
  895. while (status & DMA_RUN) {
  896. udelay(1);
  897. status = get_dma_curr_irqstat(sport->dma_tx_chan);
  898. pr_debug("DMA status:0x%04x\n", status);
  899. if (wait++ > 100)
  900. goto __over;
  901. }
  902. status = sport->regs->stat;
  903. wait = 0;
  904. while (!(status & TXHRE)) {
  905. pr_debug("sport status:0x%04x\n", status);
  906. udelay(1);
  907. status = *(unsigned short *)&sport->regs->stat;
  908. if (wait++ > 1000)
  909. goto __over;
  910. }
  911. /* Wait for the last byte sent out */
  912. udelay(20);
  913. pr_debug("sport status:0x%04x\n", status);
  914. __over:
  915. sport->regs->tcr1 &= ~TSPEN;
  916. sport->regs->rcr1 &= ~RSPEN;
  917. SSYNC();
  918. disable_dma(sport->dma_tx_chan);
  919. /* Clear the status */
  920. clear_dma_irqstat(sport->dma_tx_chan);
  921. if (in_data != NULL) {
  922. disable_dma(sport->dma_rx_chan);
  923. clear_dma_irqstat(sport->dma_rx_chan);
  924. }
  925. SSYNC();
  926. local_irq_restore(flags);
  927. return 0;
  928. }
  929. EXPORT_SYMBOL(sport_send_and_recv);
  930. MODULE_AUTHOR("Roy Huang");
  931. MODULE_DESCRIPTION("SPORT driver for ADI Blackfin");
  932. MODULE_LICENSE("GPL");