ice1712.c 82 KB

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  1. /*
  2. * ALSA driver for ICEnsemble ICE1712 (Envy24)
  3. *
  4. * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. /*
  22. NOTES:
  23. - spdif nonaudio consumer mode does not work (at least with my
  24. Sony STR-DB830)
  25. */
  26. /*
  27. * Changes:
  28. *
  29. * 2002.09.09 Takashi Iwai <tiwai@suse.de>
  30. * split the code to several files. each low-level routine
  31. * is stored in the local file and called from registration
  32. * function from card_info struct.
  33. *
  34. * 2002.11.26 James Stafford <jstafford@ampltd.com>
  35. * Added support for VT1724 (Envy24HT)
  36. * I have left out support for 176.4 and 192 KHz for the moment.
  37. * I also haven't done anything with the internal S/PDIF transmitter or the MPU-401
  38. *
  39. * 2003.02.20 Taksahi Iwai <tiwai@suse.de>
  40. * Split vt1724 part to an independent driver.
  41. * The GPIO is accessed through the callback functions now.
  42. *
  43. * 2004.03.31 Doug McLain <nostar@comcast.net>
  44. * Added support for Event Electronics EZ8 card to hoontech.c.
  45. */
  46. #include <linux/io.h>
  47. #include <linux/delay.h>
  48. #include <linux/interrupt.h>
  49. #include <linux/init.h>
  50. #include <linux/pci.h>
  51. #include <linux/dma-mapping.h>
  52. #include <linux/slab.h>
  53. #include <linux/module.h>
  54. #include <linux/mutex.h>
  55. #include <sound/core.h>
  56. #include <sound/cs8427.h>
  57. #include <sound/info.h>
  58. #include <sound/initval.h>
  59. #include <sound/tlv.h>
  60. #include <sound/asoundef.h>
  61. #include "ice1712.h"
  62. /* lowlevel routines */
  63. #include "delta.h"
  64. #include "ews.h"
  65. #include "hoontech.h"
  66. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  67. MODULE_DESCRIPTION("ICEnsemble ICE1712 (Envy24)");
  68. MODULE_LICENSE("GPL");
  69. MODULE_SUPPORTED_DEVICE("{"
  70. HOONTECH_DEVICE_DESC
  71. DELTA_DEVICE_DESC
  72. EWS_DEVICE_DESC
  73. "{ICEnsemble,Generic ICE1712},"
  74. "{ICEnsemble,Generic Envy24}}");
  75. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  76. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  77. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
  78. static char *model[SNDRV_CARDS];
  79. static bool omni[SNDRV_CARDS]; /* Delta44 & 66 Omni I/O support */
  80. static int cs8427_timeout[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 500}; /* CS8427 S/PDIF transceiver reset timeout value in msec */
  81. static int dxr_enable[SNDRV_CARDS]; /* DXR enable for DMX6FIRE */
  82. module_param_array(index, int, NULL, 0444);
  83. MODULE_PARM_DESC(index, "Index value for ICE1712 soundcard.");
  84. module_param_array(id, charp, NULL, 0444);
  85. MODULE_PARM_DESC(id, "ID string for ICE1712 soundcard.");
  86. module_param_array(enable, bool, NULL, 0444);
  87. MODULE_PARM_DESC(enable, "Enable ICE1712 soundcard.");
  88. module_param_array(omni, bool, NULL, 0444);
  89. MODULE_PARM_DESC(omni, "Enable Midiman M-Audio Delta Omni I/O support.");
  90. module_param_array(cs8427_timeout, int, NULL, 0444);
  91. MODULE_PARM_DESC(cs8427_timeout, "Define reset timeout for cs8427 chip in msec resolution.");
  92. module_param_array(model, charp, NULL, 0444);
  93. MODULE_PARM_DESC(model, "Use the given board model.");
  94. module_param_array(dxr_enable, int, NULL, 0444);
  95. MODULE_PARM_DESC(dxr_enable, "Enable DXR support for Terratec DMX6FIRE.");
  96. static DEFINE_PCI_DEVICE_TABLE(snd_ice1712_ids) = {
  97. { PCI_VDEVICE(ICE, PCI_DEVICE_ID_ICE_1712), 0 }, /* ICE1712 */
  98. { 0, }
  99. };
  100. MODULE_DEVICE_TABLE(pci, snd_ice1712_ids);
  101. static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice);
  102. static int snd_ice1712_build_controls(struct snd_ice1712 *ice);
  103. static int PRO_RATE_LOCKED;
  104. static int PRO_RATE_RESET = 1;
  105. static unsigned int PRO_RATE_DEFAULT = 44100;
  106. /*
  107. * Basic I/O
  108. */
  109. /* check whether the clock mode is spdif-in */
  110. static inline int is_spdif_master(struct snd_ice1712 *ice)
  111. {
  112. return (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER) ? 1 : 0;
  113. }
  114. static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
  115. {
  116. return is_spdif_master(ice) || PRO_RATE_LOCKED;
  117. }
  118. static inline void snd_ice1712_ds_write(struct snd_ice1712 *ice, u8 channel, u8 addr, u32 data)
  119. {
  120. outb((channel << 4) | addr, ICEDS(ice, INDEX));
  121. outl(data, ICEDS(ice, DATA));
  122. }
  123. static inline u32 snd_ice1712_ds_read(struct snd_ice1712 *ice, u8 channel, u8 addr)
  124. {
  125. outb((channel << 4) | addr, ICEDS(ice, INDEX));
  126. return inl(ICEDS(ice, DATA));
  127. }
  128. static void snd_ice1712_ac97_write(struct snd_ac97 *ac97,
  129. unsigned short reg,
  130. unsigned short val)
  131. {
  132. struct snd_ice1712 *ice = ac97->private_data;
  133. int tm;
  134. unsigned char old_cmd = 0;
  135. for (tm = 0; tm < 0x10000; tm++) {
  136. old_cmd = inb(ICEREG(ice, AC97_CMD));
  137. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  138. continue;
  139. if (!(old_cmd & ICE1712_AC97_READY))
  140. continue;
  141. break;
  142. }
  143. outb(reg, ICEREG(ice, AC97_INDEX));
  144. outw(val, ICEREG(ice, AC97_DATA));
  145. old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
  146. outb(old_cmd | ICE1712_AC97_WRITE, ICEREG(ice, AC97_CMD));
  147. for (tm = 0; tm < 0x10000; tm++)
  148. if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
  149. break;
  150. }
  151. static unsigned short snd_ice1712_ac97_read(struct snd_ac97 *ac97,
  152. unsigned short reg)
  153. {
  154. struct snd_ice1712 *ice = ac97->private_data;
  155. int tm;
  156. unsigned char old_cmd = 0;
  157. for (tm = 0; tm < 0x10000; tm++) {
  158. old_cmd = inb(ICEREG(ice, AC97_CMD));
  159. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  160. continue;
  161. if (!(old_cmd & ICE1712_AC97_READY))
  162. continue;
  163. break;
  164. }
  165. outb(reg, ICEREG(ice, AC97_INDEX));
  166. outb(old_cmd | ICE1712_AC97_READ, ICEREG(ice, AC97_CMD));
  167. for (tm = 0; tm < 0x10000; tm++)
  168. if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
  169. break;
  170. if (tm >= 0x10000) /* timeout */
  171. return ~0;
  172. return inw(ICEREG(ice, AC97_DATA));
  173. }
  174. /*
  175. * pro ac97 section
  176. */
  177. static void snd_ice1712_pro_ac97_write(struct snd_ac97 *ac97,
  178. unsigned short reg,
  179. unsigned short val)
  180. {
  181. struct snd_ice1712 *ice = ac97->private_data;
  182. int tm;
  183. unsigned char old_cmd = 0;
  184. for (tm = 0; tm < 0x10000; tm++) {
  185. old_cmd = inb(ICEMT(ice, AC97_CMD));
  186. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  187. continue;
  188. if (!(old_cmd & ICE1712_AC97_READY))
  189. continue;
  190. break;
  191. }
  192. outb(reg, ICEMT(ice, AC97_INDEX));
  193. outw(val, ICEMT(ice, AC97_DATA));
  194. old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
  195. outb(old_cmd | ICE1712_AC97_WRITE, ICEMT(ice, AC97_CMD));
  196. for (tm = 0; tm < 0x10000; tm++)
  197. if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
  198. break;
  199. }
  200. static unsigned short snd_ice1712_pro_ac97_read(struct snd_ac97 *ac97,
  201. unsigned short reg)
  202. {
  203. struct snd_ice1712 *ice = ac97->private_data;
  204. int tm;
  205. unsigned char old_cmd = 0;
  206. for (tm = 0; tm < 0x10000; tm++) {
  207. old_cmd = inb(ICEMT(ice, AC97_CMD));
  208. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  209. continue;
  210. if (!(old_cmd & ICE1712_AC97_READY))
  211. continue;
  212. break;
  213. }
  214. outb(reg, ICEMT(ice, AC97_INDEX));
  215. outb(old_cmd | ICE1712_AC97_READ, ICEMT(ice, AC97_CMD));
  216. for (tm = 0; tm < 0x10000; tm++)
  217. if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
  218. break;
  219. if (tm >= 0x10000) /* timeout */
  220. return ~0;
  221. return inw(ICEMT(ice, AC97_DATA));
  222. }
  223. /*
  224. * consumer ac97 digital mix
  225. */
  226. #define snd_ice1712_digmix_route_ac97_info snd_ctl_boolean_mono_info
  227. static int snd_ice1712_digmix_route_ac97_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  228. {
  229. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  230. ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_ROUTECTRL)) & ICE1712_ROUTE_AC97 ? 1 : 0;
  231. return 0;
  232. }
  233. static int snd_ice1712_digmix_route_ac97_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  234. {
  235. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  236. unsigned char val, nval;
  237. spin_lock_irq(&ice->reg_lock);
  238. val = inb(ICEMT(ice, MONITOR_ROUTECTRL));
  239. nval = val & ~ICE1712_ROUTE_AC97;
  240. if (ucontrol->value.integer.value[0])
  241. nval |= ICE1712_ROUTE_AC97;
  242. outb(nval, ICEMT(ice, MONITOR_ROUTECTRL));
  243. spin_unlock_irq(&ice->reg_lock);
  244. return val != nval;
  245. }
  246. static struct snd_kcontrol_new snd_ice1712_mixer_digmix_route_ac97 __devinitdata = {
  247. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  248. .name = "Digital Mixer To AC97",
  249. .info = snd_ice1712_digmix_route_ac97_info,
  250. .get = snd_ice1712_digmix_route_ac97_get,
  251. .put = snd_ice1712_digmix_route_ac97_put,
  252. };
  253. /*
  254. * gpio operations
  255. */
  256. static void snd_ice1712_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
  257. {
  258. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, data);
  259. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  260. }
  261. static unsigned int snd_ice1712_get_gpio_dir(struct snd_ice1712 *ice)
  262. {
  263. return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION);
  264. }
  265. static unsigned int snd_ice1712_get_gpio_mask(struct snd_ice1712 *ice)
  266. {
  267. return snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK);
  268. }
  269. static void snd_ice1712_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
  270. {
  271. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, data);
  272. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  273. }
  274. static unsigned int snd_ice1712_get_gpio_data(struct snd_ice1712 *ice)
  275. {
  276. return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
  277. }
  278. static void snd_ice1712_set_gpio_data(struct snd_ice1712 *ice, unsigned int val)
  279. {
  280. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, val);
  281. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  282. }
  283. /*
  284. *
  285. * CS8427 interface
  286. *
  287. */
  288. /*
  289. * change the input clock selection
  290. * spdif_clock = 1 - IEC958 input, 0 - Envy24
  291. */
  292. static int snd_ice1712_cs8427_set_input_clock(struct snd_ice1712 *ice, int spdif_clock)
  293. {
  294. unsigned char reg[2] = { 0x80 | 4, 0 }; /* CS8427 auto increment | register number 4 + data */
  295. unsigned char val, nval;
  296. int res = 0;
  297. snd_i2c_lock(ice->i2c);
  298. if (snd_i2c_sendbytes(ice->cs8427, reg, 1) != 1) {
  299. snd_i2c_unlock(ice->i2c);
  300. return -EIO;
  301. }
  302. if (snd_i2c_readbytes(ice->cs8427, &val, 1) != 1) {
  303. snd_i2c_unlock(ice->i2c);
  304. return -EIO;
  305. }
  306. nval = val & 0xf0;
  307. if (spdif_clock)
  308. nval |= 0x01;
  309. else
  310. nval |= 0x04;
  311. if (val != nval) {
  312. reg[1] = nval;
  313. if (snd_i2c_sendbytes(ice->cs8427, reg, 2) != 2) {
  314. res = -EIO;
  315. } else {
  316. res++;
  317. }
  318. }
  319. snd_i2c_unlock(ice->i2c);
  320. return res;
  321. }
  322. /*
  323. * spdif callbacks
  324. */
  325. static void open_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
  326. {
  327. snd_cs8427_iec958_active(ice->cs8427, 1);
  328. }
  329. static void close_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
  330. {
  331. snd_cs8427_iec958_active(ice->cs8427, 0);
  332. }
  333. static void setup_cs8427(struct snd_ice1712 *ice, int rate)
  334. {
  335. snd_cs8427_iec958_pcm(ice->cs8427, rate);
  336. }
  337. /*
  338. * create and initialize callbacks for cs8427 interface
  339. */
  340. int __devinit snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr)
  341. {
  342. int err;
  343. err = snd_cs8427_create(ice->i2c, addr,
  344. (ice->cs8427_timeout * HZ) / 1000, &ice->cs8427);
  345. if (err < 0) {
  346. snd_printk(KERN_ERR "CS8427 initialization failed\n");
  347. return err;
  348. }
  349. ice->spdif.ops.open = open_cs8427;
  350. ice->spdif.ops.close = close_cs8427;
  351. ice->spdif.ops.setup_rate = setup_cs8427;
  352. return 0;
  353. }
  354. static void snd_ice1712_set_input_clock_source(struct snd_ice1712 *ice, int spdif_is_master)
  355. {
  356. /* change CS8427 clock source too */
  357. if (ice->cs8427)
  358. snd_ice1712_cs8427_set_input_clock(ice, spdif_is_master);
  359. /* notify ak4524 chip as well */
  360. if (spdif_is_master) {
  361. unsigned int i;
  362. for (i = 0; i < ice->akm_codecs; i++) {
  363. if (ice->akm[i].ops.set_rate_val)
  364. ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
  365. }
  366. }
  367. }
  368. /*
  369. * Interrupt handler
  370. */
  371. static irqreturn_t snd_ice1712_interrupt(int irq, void *dev_id)
  372. {
  373. struct snd_ice1712 *ice = dev_id;
  374. unsigned char status;
  375. int handled = 0;
  376. while (1) {
  377. status = inb(ICEREG(ice, IRQSTAT));
  378. if (status == 0)
  379. break;
  380. handled = 1;
  381. if (status & ICE1712_IRQ_MPU1) {
  382. if (ice->rmidi[0])
  383. snd_mpu401_uart_interrupt(irq, ice->rmidi[0]->private_data);
  384. outb(ICE1712_IRQ_MPU1, ICEREG(ice, IRQSTAT));
  385. status &= ~ICE1712_IRQ_MPU1;
  386. }
  387. if (status & ICE1712_IRQ_TIMER)
  388. outb(ICE1712_IRQ_TIMER, ICEREG(ice, IRQSTAT));
  389. if (status & ICE1712_IRQ_MPU2) {
  390. if (ice->rmidi[1])
  391. snd_mpu401_uart_interrupt(irq, ice->rmidi[1]->private_data);
  392. outb(ICE1712_IRQ_MPU2, ICEREG(ice, IRQSTAT));
  393. status &= ~ICE1712_IRQ_MPU2;
  394. }
  395. if (status & ICE1712_IRQ_PROPCM) {
  396. unsigned char mtstat = inb(ICEMT(ice, IRQ));
  397. if (mtstat & ICE1712_MULTI_PBKSTATUS) {
  398. if (ice->playback_pro_substream)
  399. snd_pcm_period_elapsed(ice->playback_pro_substream);
  400. outb(ICE1712_MULTI_PBKSTATUS, ICEMT(ice, IRQ));
  401. }
  402. if (mtstat & ICE1712_MULTI_CAPSTATUS) {
  403. if (ice->capture_pro_substream)
  404. snd_pcm_period_elapsed(ice->capture_pro_substream);
  405. outb(ICE1712_MULTI_CAPSTATUS, ICEMT(ice, IRQ));
  406. }
  407. }
  408. if (status & ICE1712_IRQ_FM)
  409. outb(ICE1712_IRQ_FM, ICEREG(ice, IRQSTAT));
  410. if (status & ICE1712_IRQ_PBKDS) {
  411. u32 idx;
  412. u16 pbkstatus;
  413. struct snd_pcm_substream *substream;
  414. pbkstatus = inw(ICEDS(ice, INTSTAT));
  415. /* printk(KERN_DEBUG "pbkstatus = 0x%x\n", pbkstatus); */
  416. for (idx = 0; idx < 6; idx++) {
  417. if ((pbkstatus & (3 << (idx * 2))) == 0)
  418. continue;
  419. substream = ice->playback_con_substream_ds[idx];
  420. if (substream != NULL)
  421. snd_pcm_period_elapsed(substream);
  422. outw(3 << (idx * 2), ICEDS(ice, INTSTAT));
  423. }
  424. outb(ICE1712_IRQ_PBKDS, ICEREG(ice, IRQSTAT));
  425. }
  426. if (status & ICE1712_IRQ_CONCAP) {
  427. if (ice->capture_con_substream)
  428. snd_pcm_period_elapsed(ice->capture_con_substream);
  429. outb(ICE1712_IRQ_CONCAP, ICEREG(ice, IRQSTAT));
  430. }
  431. if (status & ICE1712_IRQ_CONPBK) {
  432. if (ice->playback_con_substream)
  433. snd_pcm_period_elapsed(ice->playback_con_substream);
  434. outb(ICE1712_IRQ_CONPBK, ICEREG(ice, IRQSTAT));
  435. }
  436. }
  437. return IRQ_RETVAL(handled);
  438. }
  439. /*
  440. * PCM part - misc
  441. */
  442. static int snd_ice1712_hw_params(struct snd_pcm_substream *substream,
  443. struct snd_pcm_hw_params *hw_params)
  444. {
  445. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  446. }
  447. static int snd_ice1712_hw_free(struct snd_pcm_substream *substream)
  448. {
  449. return snd_pcm_lib_free_pages(substream);
  450. }
  451. /*
  452. * PCM part - consumer I/O
  453. */
  454. static int snd_ice1712_playback_trigger(struct snd_pcm_substream *substream,
  455. int cmd)
  456. {
  457. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  458. int result = 0;
  459. u32 tmp;
  460. spin_lock(&ice->reg_lock);
  461. tmp = snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL);
  462. if (cmd == SNDRV_PCM_TRIGGER_START) {
  463. tmp |= 1;
  464. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  465. tmp &= ~1;
  466. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
  467. tmp |= 2;
  468. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
  469. tmp &= ~2;
  470. } else {
  471. result = -EINVAL;
  472. }
  473. snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
  474. spin_unlock(&ice->reg_lock);
  475. return result;
  476. }
  477. static int snd_ice1712_playback_ds_trigger(struct snd_pcm_substream *substream,
  478. int cmd)
  479. {
  480. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  481. int result = 0;
  482. u32 tmp;
  483. spin_lock(&ice->reg_lock);
  484. tmp = snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL);
  485. if (cmd == SNDRV_PCM_TRIGGER_START) {
  486. tmp |= 1;
  487. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  488. tmp &= ~1;
  489. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
  490. tmp |= 2;
  491. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
  492. tmp &= ~2;
  493. } else {
  494. result = -EINVAL;
  495. }
  496. snd_ice1712_ds_write(ice, substream->number * 2, ICE1712_DSC_CONTROL, tmp);
  497. spin_unlock(&ice->reg_lock);
  498. return result;
  499. }
  500. static int snd_ice1712_capture_trigger(struct snd_pcm_substream *substream,
  501. int cmd)
  502. {
  503. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  504. int result = 0;
  505. u8 tmp;
  506. spin_lock(&ice->reg_lock);
  507. tmp = snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL);
  508. if (cmd == SNDRV_PCM_TRIGGER_START) {
  509. tmp |= 1;
  510. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  511. tmp &= ~1;
  512. } else {
  513. result = -EINVAL;
  514. }
  515. snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
  516. spin_unlock(&ice->reg_lock);
  517. return result;
  518. }
  519. static int snd_ice1712_playback_prepare(struct snd_pcm_substream *substream)
  520. {
  521. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  522. struct snd_pcm_runtime *runtime = substream->runtime;
  523. u32 period_size, buf_size, rate, tmp;
  524. period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  525. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  526. tmp = 0x0000;
  527. if (snd_pcm_format_width(runtime->format) == 16)
  528. tmp |= 0x10;
  529. if (runtime->channels == 2)
  530. tmp |= 0x08;
  531. rate = (runtime->rate * 8192) / 375;
  532. if (rate > 0x000fffff)
  533. rate = 0x000fffff;
  534. spin_lock_irq(&ice->reg_lock);
  535. outb(0, ice->ddma_port + 15);
  536. outb(ICE1712_DMA_MODE_WRITE | ICE1712_DMA_AUTOINIT, ice->ddma_port + 0x0b);
  537. outl(runtime->dma_addr, ice->ddma_port + 0);
  538. outw(buf_size, ice->ddma_port + 4);
  539. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_LO, rate & 0xff);
  540. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_MID, (rate >> 8) & 0xff);
  541. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_HI, (rate >> 16) & 0xff);
  542. snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
  543. snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_LO, period_size & 0xff);
  544. snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_HI, period_size >> 8);
  545. snd_ice1712_write(ice, ICE1712_IREG_PBK_LEFT, 0);
  546. snd_ice1712_write(ice, ICE1712_IREG_PBK_RIGHT, 0);
  547. spin_unlock_irq(&ice->reg_lock);
  548. return 0;
  549. }
  550. static int snd_ice1712_playback_ds_prepare(struct snd_pcm_substream *substream)
  551. {
  552. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  553. struct snd_pcm_runtime *runtime = substream->runtime;
  554. u32 period_size, buf_size, rate, tmp, chn;
  555. period_size = snd_pcm_lib_period_bytes(substream) - 1;
  556. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  557. tmp = 0x0064;
  558. if (snd_pcm_format_width(runtime->format) == 16)
  559. tmp &= ~0x04;
  560. if (runtime->channels == 2)
  561. tmp |= 0x08;
  562. rate = (runtime->rate * 8192) / 375;
  563. if (rate > 0x000fffff)
  564. rate = 0x000fffff;
  565. ice->playback_con_active_buf[substream->number] = 0;
  566. ice->playback_con_virt_addr[substream->number] = runtime->dma_addr;
  567. chn = substream->number * 2;
  568. spin_lock_irq(&ice->reg_lock);
  569. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR0, runtime->dma_addr);
  570. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT0, period_size);
  571. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR1, runtime->dma_addr + (runtime->periods > 1 ? period_size + 1 : 0));
  572. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT1, period_size);
  573. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_RATE, rate);
  574. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_VOLUME, 0);
  575. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_CONTROL, tmp);
  576. if (runtime->channels == 2) {
  577. snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_RATE, rate);
  578. snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_VOLUME, 0);
  579. }
  580. spin_unlock_irq(&ice->reg_lock);
  581. return 0;
  582. }
  583. static int snd_ice1712_capture_prepare(struct snd_pcm_substream *substream)
  584. {
  585. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  586. struct snd_pcm_runtime *runtime = substream->runtime;
  587. u32 period_size, buf_size;
  588. u8 tmp;
  589. period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  590. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  591. tmp = 0x06;
  592. if (snd_pcm_format_width(runtime->format) == 16)
  593. tmp &= ~0x04;
  594. if (runtime->channels == 2)
  595. tmp &= ~0x02;
  596. spin_lock_irq(&ice->reg_lock);
  597. outl(ice->capture_con_virt_addr = runtime->dma_addr, ICEREG(ice, CONCAP_ADDR));
  598. outw(buf_size, ICEREG(ice, CONCAP_COUNT));
  599. snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_HI, period_size >> 8);
  600. snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_LO, period_size & 0xff);
  601. snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
  602. spin_unlock_irq(&ice->reg_lock);
  603. snd_ac97_set_rate(ice->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
  604. return 0;
  605. }
  606. static snd_pcm_uframes_t snd_ice1712_playback_pointer(struct snd_pcm_substream *substream)
  607. {
  608. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  609. struct snd_pcm_runtime *runtime = substream->runtime;
  610. size_t ptr;
  611. if (!(snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL) & 1))
  612. return 0;
  613. ptr = runtime->buffer_size - inw(ice->ddma_port + 4);
  614. ptr = bytes_to_frames(substream->runtime, ptr);
  615. if (ptr == runtime->buffer_size)
  616. ptr = 0;
  617. return ptr;
  618. }
  619. static snd_pcm_uframes_t snd_ice1712_playback_ds_pointer(struct snd_pcm_substream *substream)
  620. {
  621. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  622. u8 addr;
  623. size_t ptr;
  624. if (!(snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL) & 1))
  625. return 0;
  626. if (ice->playback_con_active_buf[substream->number])
  627. addr = ICE1712_DSC_ADDR1;
  628. else
  629. addr = ICE1712_DSC_ADDR0;
  630. ptr = snd_ice1712_ds_read(ice, substream->number * 2, addr) -
  631. ice->playback_con_virt_addr[substream->number];
  632. ptr = bytes_to_frames(substream->runtime, ptr);
  633. if (ptr == substream->runtime->buffer_size)
  634. ptr = 0;
  635. return ptr;
  636. }
  637. static snd_pcm_uframes_t snd_ice1712_capture_pointer(struct snd_pcm_substream *substream)
  638. {
  639. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  640. size_t ptr;
  641. if (!(snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL) & 1))
  642. return 0;
  643. ptr = inl(ICEREG(ice, CONCAP_ADDR)) - ice->capture_con_virt_addr;
  644. ptr = bytes_to_frames(substream->runtime, ptr);
  645. if (ptr == substream->runtime->buffer_size)
  646. ptr = 0;
  647. return ptr;
  648. }
  649. static const struct snd_pcm_hardware snd_ice1712_playback = {
  650. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  651. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  652. SNDRV_PCM_INFO_MMAP_VALID |
  653. SNDRV_PCM_INFO_PAUSE),
  654. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  655. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  656. .rate_min = 4000,
  657. .rate_max = 48000,
  658. .channels_min = 1,
  659. .channels_max = 2,
  660. .buffer_bytes_max = (64*1024),
  661. .period_bytes_min = 64,
  662. .period_bytes_max = (64*1024),
  663. .periods_min = 1,
  664. .periods_max = 1024,
  665. .fifo_size = 0,
  666. };
  667. static const struct snd_pcm_hardware snd_ice1712_playback_ds = {
  668. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  669. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  670. SNDRV_PCM_INFO_MMAP_VALID |
  671. SNDRV_PCM_INFO_PAUSE),
  672. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  673. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  674. .rate_min = 4000,
  675. .rate_max = 48000,
  676. .channels_min = 1,
  677. .channels_max = 2,
  678. .buffer_bytes_max = (128*1024),
  679. .period_bytes_min = 64,
  680. .period_bytes_max = (128*1024),
  681. .periods_min = 2,
  682. .periods_max = 2,
  683. .fifo_size = 0,
  684. };
  685. static const struct snd_pcm_hardware snd_ice1712_capture = {
  686. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  687. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  688. SNDRV_PCM_INFO_MMAP_VALID),
  689. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  690. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  691. .rate_min = 4000,
  692. .rate_max = 48000,
  693. .channels_min = 1,
  694. .channels_max = 2,
  695. .buffer_bytes_max = (64*1024),
  696. .period_bytes_min = 64,
  697. .period_bytes_max = (64*1024),
  698. .periods_min = 1,
  699. .periods_max = 1024,
  700. .fifo_size = 0,
  701. };
  702. static int snd_ice1712_playback_open(struct snd_pcm_substream *substream)
  703. {
  704. struct snd_pcm_runtime *runtime = substream->runtime;
  705. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  706. ice->playback_con_substream = substream;
  707. runtime->hw = snd_ice1712_playback;
  708. return 0;
  709. }
  710. static int snd_ice1712_playback_ds_open(struct snd_pcm_substream *substream)
  711. {
  712. struct snd_pcm_runtime *runtime = substream->runtime;
  713. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  714. u32 tmp;
  715. ice->playback_con_substream_ds[substream->number] = substream;
  716. runtime->hw = snd_ice1712_playback_ds;
  717. spin_lock_irq(&ice->reg_lock);
  718. tmp = inw(ICEDS(ice, INTMASK)) & ~(1 << (substream->number * 2));
  719. outw(tmp, ICEDS(ice, INTMASK));
  720. spin_unlock_irq(&ice->reg_lock);
  721. return 0;
  722. }
  723. static int snd_ice1712_capture_open(struct snd_pcm_substream *substream)
  724. {
  725. struct snd_pcm_runtime *runtime = substream->runtime;
  726. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  727. ice->capture_con_substream = substream;
  728. runtime->hw = snd_ice1712_capture;
  729. runtime->hw.rates = ice->ac97->rates[AC97_RATES_ADC];
  730. if (!(runtime->hw.rates & SNDRV_PCM_RATE_8000))
  731. runtime->hw.rate_min = 48000;
  732. return 0;
  733. }
  734. static int snd_ice1712_playback_close(struct snd_pcm_substream *substream)
  735. {
  736. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  737. ice->playback_con_substream = NULL;
  738. return 0;
  739. }
  740. static int snd_ice1712_playback_ds_close(struct snd_pcm_substream *substream)
  741. {
  742. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  743. u32 tmp;
  744. spin_lock_irq(&ice->reg_lock);
  745. tmp = inw(ICEDS(ice, INTMASK)) | (3 << (substream->number * 2));
  746. outw(tmp, ICEDS(ice, INTMASK));
  747. spin_unlock_irq(&ice->reg_lock);
  748. ice->playback_con_substream_ds[substream->number] = NULL;
  749. return 0;
  750. }
  751. static int snd_ice1712_capture_close(struct snd_pcm_substream *substream)
  752. {
  753. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  754. ice->capture_con_substream = NULL;
  755. return 0;
  756. }
  757. static struct snd_pcm_ops snd_ice1712_playback_ops = {
  758. .open = snd_ice1712_playback_open,
  759. .close = snd_ice1712_playback_close,
  760. .ioctl = snd_pcm_lib_ioctl,
  761. .hw_params = snd_ice1712_hw_params,
  762. .hw_free = snd_ice1712_hw_free,
  763. .prepare = snd_ice1712_playback_prepare,
  764. .trigger = snd_ice1712_playback_trigger,
  765. .pointer = snd_ice1712_playback_pointer,
  766. };
  767. static struct snd_pcm_ops snd_ice1712_playback_ds_ops = {
  768. .open = snd_ice1712_playback_ds_open,
  769. .close = snd_ice1712_playback_ds_close,
  770. .ioctl = snd_pcm_lib_ioctl,
  771. .hw_params = snd_ice1712_hw_params,
  772. .hw_free = snd_ice1712_hw_free,
  773. .prepare = snd_ice1712_playback_ds_prepare,
  774. .trigger = snd_ice1712_playback_ds_trigger,
  775. .pointer = snd_ice1712_playback_ds_pointer,
  776. };
  777. static struct snd_pcm_ops snd_ice1712_capture_ops = {
  778. .open = snd_ice1712_capture_open,
  779. .close = snd_ice1712_capture_close,
  780. .ioctl = snd_pcm_lib_ioctl,
  781. .hw_params = snd_ice1712_hw_params,
  782. .hw_free = snd_ice1712_hw_free,
  783. .prepare = snd_ice1712_capture_prepare,
  784. .trigger = snd_ice1712_capture_trigger,
  785. .pointer = snd_ice1712_capture_pointer,
  786. };
  787. static int __devinit snd_ice1712_pcm(struct snd_ice1712 *ice, int device, struct snd_pcm **rpcm)
  788. {
  789. struct snd_pcm *pcm;
  790. int err;
  791. if (rpcm)
  792. *rpcm = NULL;
  793. err = snd_pcm_new(ice->card, "ICE1712 consumer", device, 1, 1, &pcm);
  794. if (err < 0)
  795. return err;
  796. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ops);
  797. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_ops);
  798. pcm->private_data = ice;
  799. pcm->info_flags = 0;
  800. strcpy(pcm->name, "ICE1712 consumer");
  801. ice->pcm = pcm;
  802. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  803. snd_dma_pci_data(ice->pci), 64*1024, 64*1024);
  804. if (rpcm)
  805. *rpcm = pcm;
  806. printk(KERN_WARNING "Consumer PCM code does not work well at the moment --jk\n");
  807. return 0;
  808. }
  809. static int __devinit snd_ice1712_pcm_ds(struct snd_ice1712 *ice, int device, struct snd_pcm **rpcm)
  810. {
  811. struct snd_pcm *pcm;
  812. int err;
  813. if (rpcm)
  814. *rpcm = NULL;
  815. err = snd_pcm_new(ice->card, "ICE1712 consumer (DS)", device, 6, 0, &pcm);
  816. if (err < 0)
  817. return err;
  818. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ds_ops);
  819. pcm->private_data = ice;
  820. pcm->info_flags = 0;
  821. strcpy(pcm->name, "ICE1712 consumer (DS)");
  822. ice->pcm_ds = pcm;
  823. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  824. snd_dma_pci_data(ice->pci), 64*1024, 128*1024);
  825. if (rpcm)
  826. *rpcm = pcm;
  827. return 0;
  828. }
  829. /*
  830. * PCM code - professional part (multitrack)
  831. */
  832. static unsigned int rates[] = { 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  833. 32000, 44100, 48000, 64000, 88200, 96000 };
  834. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  835. .count = ARRAY_SIZE(rates),
  836. .list = rates,
  837. .mask = 0,
  838. };
  839. static int snd_ice1712_pro_trigger(struct snd_pcm_substream *substream,
  840. int cmd)
  841. {
  842. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  843. switch (cmd) {
  844. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  845. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  846. {
  847. unsigned int what;
  848. unsigned int old;
  849. if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
  850. return -EINVAL;
  851. what = ICE1712_PLAYBACK_PAUSE;
  852. snd_pcm_trigger_done(substream, substream);
  853. spin_lock(&ice->reg_lock);
  854. old = inl(ICEMT(ice, PLAYBACK_CONTROL));
  855. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  856. old |= what;
  857. else
  858. old &= ~what;
  859. outl(old, ICEMT(ice, PLAYBACK_CONTROL));
  860. spin_unlock(&ice->reg_lock);
  861. break;
  862. }
  863. case SNDRV_PCM_TRIGGER_START:
  864. case SNDRV_PCM_TRIGGER_STOP:
  865. {
  866. unsigned int what = 0;
  867. unsigned int old;
  868. struct snd_pcm_substream *s;
  869. snd_pcm_group_for_each_entry(s, substream) {
  870. if (s == ice->playback_pro_substream) {
  871. what |= ICE1712_PLAYBACK_START;
  872. snd_pcm_trigger_done(s, substream);
  873. } else if (s == ice->capture_pro_substream) {
  874. what |= ICE1712_CAPTURE_START_SHADOW;
  875. snd_pcm_trigger_done(s, substream);
  876. }
  877. }
  878. spin_lock(&ice->reg_lock);
  879. old = inl(ICEMT(ice, PLAYBACK_CONTROL));
  880. if (cmd == SNDRV_PCM_TRIGGER_START)
  881. old |= what;
  882. else
  883. old &= ~what;
  884. outl(old, ICEMT(ice, PLAYBACK_CONTROL));
  885. spin_unlock(&ice->reg_lock);
  886. break;
  887. }
  888. default:
  889. return -EINVAL;
  890. }
  891. return 0;
  892. }
  893. /*
  894. */
  895. static void snd_ice1712_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate, int force)
  896. {
  897. unsigned long flags;
  898. unsigned char val, old;
  899. unsigned int i;
  900. switch (rate) {
  901. case 8000: val = 6; break;
  902. case 9600: val = 3; break;
  903. case 11025: val = 10; break;
  904. case 12000: val = 2; break;
  905. case 16000: val = 5; break;
  906. case 22050: val = 9; break;
  907. case 24000: val = 1; break;
  908. case 32000: val = 4; break;
  909. case 44100: val = 8; break;
  910. case 48000: val = 0; break;
  911. case 64000: val = 15; break;
  912. case 88200: val = 11; break;
  913. case 96000: val = 7; break;
  914. default:
  915. snd_BUG();
  916. val = 0;
  917. rate = 48000;
  918. break;
  919. }
  920. spin_lock_irqsave(&ice->reg_lock, flags);
  921. if (inb(ICEMT(ice, PLAYBACK_CONTROL)) & (ICE1712_CAPTURE_START_SHADOW|
  922. ICE1712_PLAYBACK_PAUSE|
  923. ICE1712_PLAYBACK_START)) {
  924. __out:
  925. spin_unlock_irqrestore(&ice->reg_lock, flags);
  926. return;
  927. }
  928. if (!force && is_pro_rate_locked(ice))
  929. goto __out;
  930. old = inb(ICEMT(ice, RATE));
  931. if (!force && old == val)
  932. goto __out;
  933. outb(val, ICEMT(ice, RATE));
  934. spin_unlock_irqrestore(&ice->reg_lock, flags);
  935. if (ice->gpio.set_pro_rate)
  936. ice->gpio.set_pro_rate(ice, rate);
  937. for (i = 0; i < ice->akm_codecs; i++) {
  938. if (ice->akm[i].ops.set_rate_val)
  939. ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
  940. }
  941. if (ice->spdif.ops.setup_rate)
  942. ice->spdif.ops.setup_rate(ice, rate);
  943. }
  944. static int snd_ice1712_playback_pro_prepare(struct snd_pcm_substream *substream)
  945. {
  946. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  947. ice->playback_pro_size = snd_pcm_lib_buffer_bytes(substream);
  948. spin_lock_irq(&ice->reg_lock);
  949. outl(substream->runtime->dma_addr, ICEMT(ice, PLAYBACK_ADDR));
  950. outw((ice->playback_pro_size >> 2) - 1, ICEMT(ice, PLAYBACK_SIZE));
  951. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, PLAYBACK_COUNT));
  952. spin_unlock_irq(&ice->reg_lock);
  953. return 0;
  954. }
  955. static int snd_ice1712_playback_pro_hw_params(struct snd_pcm_substream *substream,
  956. struct snd_pcm_hw_params *hw_params)
  957. {
  958. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  959. snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
  960. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  961. }
  962. static int snd_ice1712_capture_pro_prepare(struct snd_pcm_substream *substream)
  963. {
  964. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  965. ice->capture_pro_size = snd_pcm_lib_buffer_bytes(substream);
  966. spin_lock_irq(&ice->reg_lock);
  967. outl(substream->runtime->dma_addr, ICEMT(ice, CAPTURE_ADDR));
  968. outw((ice->capture_pro_size >> 2) - 1, ICEMT(ice, CAPTURE_SIZE));
  969. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, CAPTURE_COUNT));
  970. spin_unlock_irq(&ice->reg_lock);
  971. return 0;
  972. }
  973. static int snd_ice1712_capture_pro_hw_params(struct snd_pcm_substream *substream,
  974. struct snd_pcm_hw_params *hw_params)
  975. {
  976. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  977. snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
  978. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  979. }
  980. static snd_pcm_uframes_t snd_ice1712_playback_pro_pointer(struct snd_pcm_substream *substream)
  981. {
  982. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  983. size_t ptr;
  984. if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_PLAYBACK_START))
  985. return 0;
  986. ptr = ice->playback_pro_size - (inw(ICEMT(ice, PLAYBACK_SIZE)) << 2);
  987. ptr = bytes_to_frames(substream->runtime, ptr);
  988. if (ptr == substream->runtime->buffer_size)
  989. ptr = 0;
  990. return ptr;
  991. }
  992. static snd_pcm_uframes_t snd_ice1712_capture_pro_pointer(struct snd_pcm_substream *substream)
  993. {
  994. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  995. size_t ptr;
  996. if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_CAPTURE_START_SHADOW))
  997. return 0;
  998. ptr = ice->capture_pro_size - (inw(ICEMT(ice, CAPTURE_SIZE)) << 2);
  999. ptr = bytes_to_frames(substream->runtime, ptr);
  1000. if (ptr == substream->runtime->buffer_size)
  1001. ptr = 0;
  1002. return ptr;
  1003. }
  1004. static const struct snd_pcm_hardware snd_ice1712_playback_pro = {
  1005. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1006. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  1007. SNDRV_PCM_INFO_MMAP_VALID |
  1008. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  1009. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  1010. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
  1011. .rate_min = 4000,
  1012. .rate_max = 96000,
  1013. .channels_min = 10,
  1014. .channels_max = 10,
  1015. .buffer_bytes_max = (256*1024),
  1016. .period_bytes_min = 10 * 4 * 2,
  1017. .period_bytes_max = 131040,
  1018. .periods_min = 1,
  1019. .periods_max = 1024,
  1020. .fifo_size = 0,
  1021. };
  1022. static const struct snd_pcm_hardware snd_ice1712_capture_pro = {
  1023. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1024. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  1025. SNDRV_PCM_INFO_MMAP_VALID |
  1026. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  1027. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  1028. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
  1029. .rate_min = 4000,
  1030. .rate_max = 96000,
  1031. .channels_min = 12,
  1032. .channels_max = 12,
  1033. .buffer_bytes_max = (256*1024),
  1034. .period_bytes_min = 12 * 4 * 2,
  1035. .period_bytes_max = 131040,
  1036. .periods_min = 1,
  1037. .periods_max = 1024,
  1038. .fifo_size = 0,
  1039. };
  1040. static int snd_ice1712_playback_pro_open(struct snd_pcm_substream *substream)
  1041. {
  1042. struct snd_pcm_runtime *runtime = substream->runtime;
  1043. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1044. ice->playback_pro_substream = substream;
  1045. runtime->hw = snd_ice1712_playback_pro;
  1046. snd_pcm_set_sync(substream);
  1047. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1048. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  1049. if (is_pro_rate_locked(ice)) {
  1050. runtime->hw.rate_min = PRO_RATE_DEFAULT;
  1051. runtime->hw.rate_max = PRO_RATE_DEFAULT;
  1052. }
  1053. if (ice->spdif.ops.open)
  1054. ice->spdif.ops.open(ice, substream);
  1055. return 0;
  1056. }
  1057. static int snd_ice1712_capture_pro_open(struct snd_pcm_substream *substream)
  1058. {
  1059. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1060. struct snd_pcm_runtime *runtime = substream->runtime;
  1061. ice->capture_pro_substream = substream;
  1062. runtime->hw = snd_ice1712_capture_pro;
  1063. snd_pcm_set_sync(substream);
  1064. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1065. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  1066. if (is_pro_rate_locked(ice)) {
  1067. runtime->hw.rate_min = PRO_RATE_DEFAULT;
  1068. runtime->hw.rate_max = PRO_RATE_DEFAULT;
  1069. }
  1070. return 0;
  1071. }
  1072. static int snd_ice1712_playback_pro_close(struct snd_pcm_substream *substream)
  1073. {
  1074. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1075. if (PRO_RATE_RESET)
  1076. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
  1077. ice->playback_pro_substream = NULL;
  1078. if (ice->spdif.ops.close)
  1079. ice->spdif.ops.close(ice, substream);
  1080. return 0;
  1081. }
  1082. static int snd_ice1712_capture_pro_close(struct snd_pcm_substream *substream)
  1083. {
  1084. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1085. if (PRO_RATE_RESET)
  1086. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
  1087. ice->capture_pro_substream = NULL;
  1088. return 0;
  1089. }
  1090. static struct snd_pcm_ops snd_ice1712_playback_pro_ops = {
  1091. .open = snd_ice1712_playback_pro_open,
  1092. .close = snd_ice1712_playback_pro_close,
  1093. .ioctl = snd_pcm_lib_ioctl,
  1094. .hw_params = snd_ice1712_playback_pro_hw_params,
  1095. .hw_free = snd_ice1712_hw_free,
  1096. .prepare = snd_ice1712_playback_pro_prepare,
  1097. .trigger = snd_ice1712_pro_trigger,
  1098. .pointer = snd_ice1712_playback_pro_pointer,
  1099. };
  1100. static struct snd_pcm_ops snd_ice1712_capture_pro_ops = {
  1101. .open = snd_ice1712_capture_pro_open,
  1102. .close = snd_ice1712_capture_pro_close,
  1103. .ioctl = snd_pcm_lib_ioctl,
  1104. .hw_params = snd_ice1712_capture_pro_hw_params,
  1105. .hw_free = snd_ice1712_hw_free,
  1106. .prepare = snd_ice1712_capture_pro_prepare,
  1107. .trigger = snd_ice1712_pro_trigger,
  1108. .pointer = snd_ice1712_capture_pro_pointer,
  1109. };
  1110. static int __devinit snd_ice1712_pcm_profi(struct snd_ice1712 *ice, int device, struct snd_pcm **rpcm)
  1111. {
  1112. struct snd_pcm *pcm;
  1113. int err;
  1114. if (rpcm)
  1115. *rpcm = NULL;
  1116. err = snd_pcm_new(ice->card, "ICE1712 multi", device, 1, 1, &pcm);
  1117. if (err < 0)
  1118. return err;
  1119. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_pro_ops);
  1120. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_pro_ops);
  1121. pcm->private_data = ice;
  1122. pcm->info_flags = 0;
  1123. strcpy(pcm->name, "ICE1712 multi");
  1124. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1125. snd_dma_pci_data(ice->pci), 256*1024, 256*1024);
  1126. ice->pcm_pro = pcm;
  1127. if (rpcm)
  1128. *rpcm = pcm;
  1129. if (ice->cs8427) {
  1130. /* assign channels to iec958 */
  1131. err = snd_cs8427_iec958_build(ice->cs8427,
  1132. pcm->streams[0].substream,
  1133. pcm->streams[1].substream);
  1134. if (err < 0)
  1135. return err;
  1136. }
  1137. err = snd_ice1712_build_pro_mixer(ice);
  1138. if (err < 0)
  1139. return err;
  1140. return 0;
  1141. }
  1142. /*
  1143. * Mixer section
  1144. */
  1145. static void snd_ice1712_update_volume(struct snd_ice1712 *ice, int index)
  1146. {
  1147. unsigned int vol = ice->pro_volumes[index];
  1148. unsigned short val = 0;
  1149. val |= (vol & 0x8000) == 0 ? (96 - (vol & 0x7f)) : 0x7f;
  1150. val |= ((vol & 0x80000000) == 0 ? (96 - ((vol >> 16) & 0x7f)) : 0x7f) << 8;
  1151. outb(index, ICEMT(ice, MONITOR_INDEX));
  1152. outw(val, ICEMT(ice, MONITOR_VOLUME));
  1153. }
  1154. #define snd_ice1712_pro_mixer_switch_info snd_ctl_boolean_stereo_info
  1155. static int snd_ice1712_pro_mixer_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1156. {
  1157. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1158. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1159. kcontrol->private_value;
  1160. spin_lock_irq(&ice->reg_lock);
  1161. ucontrol->value.integer.value[0] =
  1162. !((ice->pro_volumes[priv_idx] >> 15) & 1);
  1163. ucontrol->value.integer.value[1] =
  1164. !((ice->pro_volumes[priv_idx] >> 31) & 1);
  1165. spin_unlock_irq(&ice->reg_lock);
  1166. return 0;
  1167. }
  1168. static int snd_ice1712_pro_mixer_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1169. {
  1170. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1171. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1172. kcontrol->private_value;
  1173. unsigned int nval, change;
  1174. nval = (ucontrol->value.integer.value[0] ? 0 : 0x00008000) |
  1175. (ucontrol->value.integer.value[1] ? 0 : 0x80000000);
  1176. spin_lock_irq(&ice->reg_lock);
  1177. nval |= ice->pro_volumes[priv_idx] & ~0x80008000;
  1178. change = nval != ice->pro_volumes[priv_idx];
  1179. ice->pro_volumes[priv_idx] = nval;
  1180. snd_ice1712_update_volume(ice, priv_idx);
  1181. spin_unlock_irq(&ice->reg_lock);
  1182. return change;
  1183. }
  1184. static int snd_ice1712_pro_mixer_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1185. {
  1186. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1187. uinfo->count = 2;
  1188. uinfo->value.integer.min = 0;
  1189. uinfo->value.integer.max = 96;
  1190. return 0;
  1191. }
  1192. static int snd_ice1712_pro_mixer_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1193. {
  1194. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1195. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1196. kcontrol->private_value;
  1197. spin_lock_irq(&ice->reg_lock);
  1198. ucontrol->value.integer.value[0] =
  1199. (ice->pro_volumes[priv_idx] >> 0) & 127;
  1200. ucontrol->value.integer.value[1] =
  1201. (ice->pro_volumes[priv_idx] >> 16) & 127;
  1202. spin_unlock_irq(&ice->reg_lock);
  1203. return 0;
  1204. }
  1205. static int snd_ice1712_pro_mixer_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1206. {
  1207. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1208. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1209. kcontrol->private_value;
  1210. unsigned int nval, change;
  1211. nval = (ucontrol->value.integer.value[0] & 127) |
  1212. ((ucontrol->value.integer.value[1] & 127) << 16);
  1213. spin_lock_irq(&ice->reg_lock);
  1214. nval |= ice->pro_volumes[priv_idx] & ~0x007f007f;
  1215. change = nval != ice->pro_volumes[priv_idx];
  1216. ice->pro_volumes[priv_idx] = nval;
  1217. snd_ice1712_update_volume(ice, priv_idx);
  1218. spin_unlock_irq(&ice->reg_lock);
  1219. return change;
  1220. }
  1221. static const DECLARE_TLV_DB_SCALE(db_scale_playback, -14400, 150, 0);
  1222. static struct snd_kcontrol_new snd_ice1712_multi_playback_ctrls[] __devinitdata = {
  1223. {
  1224. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1225. .name = "Multi Playback Switch",
  1226. .info = snd_ice1712_pro_mixer_switch_info,
  1227. .get = snd_ice1712_pro_mixer_switch_get,
  1228. .put = snd_ice1712_pro_mixer_switch_put,
  1229. .private_value = 0,
  1230. .count = 10,
  1231. },
  1232. {
  1233. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1234. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1235. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  1236. .name = "Multi Playback Volume",
  1237. .info = snd_ice1712_pro_mixer_volume_info,
  1238. .get = snd_ice1712_pro_mixer_volume_get,
  1239. .put = snd_ice1712_pro_mixer_volume_put,
  1240. .private_value = 0,
  1241. .count = 10,
  1242. .tlv = { .p = db_scale_playback }
  1243. },
  1244. };
  1245. static struct snd_kcontrol_new snd_ice1712_multi_capture_analog_switch __devinitdata = {
  1246. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1247. .name = "H/W Multi Capture Switch",
  1248. .info = snd_ice1712_pro_mixer_switch_info,
  1249. .get = snd_ice1712_pro_mixer_switch_get,
  1250. .put = snd_ice1712_pro_mixer_switch_put,
  1251. .private_value = 10,
  1252. };
  1253. static struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_switch __devinitdata = {
  1254. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1255. .name = SNDRV_CTL_NAME_IEC958("Multi ", CAPTURE, SWITCH),
  1256. .info = snd_ice1712_pro_mixer_switch_info,
  1257. .get = snd_ice1712_pro_mixer_switch_get,
  1258. .put = snd_ice1712_pro_mixer_switch_put,
  1259. .private_value = 18,
  1260. .count = 2,
  1261. };
  1262. static struct snd_kcontrol_new snd_ice1712_multi_capture_analog_volume __devinitdata = {
  1263. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1264. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1265. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  1266. .name = "H/W Multi Capture Volume",
  1267. .info = snd_ice1712_pro_mixer_volume_info,
  1268. .get = snd_ice1712_pro_mixer_volume_get,
  1269. .put = snd_ice1712_pro_mixer_volume_put,
  1270. .private_value = 10,
  1271. .tlv = { .p = db_scale_playback }
  1272. };
  1273. static struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_volume __devinitdata = {
  1274. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1275. .name = SNDRV_CTL_NAME_IEC958("Multi ", CAPTURE, VOLUME),
  1276. .info = snd_ice1712_pro_mixer_volume_info,
  1277. .get = snd_ice1712_pro_mixer_volume_get,
  1278. .put = snd_ice1712_pro_mixer_volume_put,
  1279. .private_value = 18,
  1280. .count = 2,
  1281. };
  1282. static int __devinit snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice)
  1283. {
  1284. struct snd_card *card = ice->card;
  1285. unsigned int idx;
  1286. int err;
  1287. /* multi-channel mixer */
  1288. for (idx = 0; idx < ARRAY_SIZE(snd_ice1712_multi_playback_ctrls); idx++) {
  1289. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_playback_ctrls[idx], ice));
  1290. if (err < 0)
  1291. return err;
  1292. }
  1293. if (ice->num_total_adcs > 0) {
  1294. struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_switch;
  1295. tmp.count = ice->num_total_adcs;
  1296. err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
  1297. if (err < 0)
  1298. return err;
  1299. }
  1300. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_switch, ice));
  1301. if (err < 0)
  1302. return err;
  1303. if (ice->num_total_adcs > 0) {
  1304. struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_volume;
  1305. tmp.count = ice->num_total_adcs;
  1306. err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
  1307. if (err < 0)
  1308. return err;
  1309. }
  1310. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_volume, ice));
  1311. if (err < 0)
  1312. return err;
  1313. /* initialize volumes */
  1314. for (idx = 0; idx < 10; idx++) {
  1315. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1316. snd_ice1712_update_volume(ice, idx);
  1317. }
  1318. for (idx = 10; idx < 10 + ice->num_total_adcs; idx++) {
  1319. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1320. snd_ice1712_update_volume(ice, idx);
  1321. }
  1322. for (idx = 18; idx < 20; idx++) {
  1323. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1324. snd_ice1712_update_volume(ice, idx);
  1325. }
  1326. return 0;
  1327. }
  1328. static void snd_ice1712_mixer_free_ac97(struct snd_ac97 *ac97)
  1329. {
  1330. struct snd_ice1712 *ice = ac97->private_data;
  1331. ice->ac97 = NULL;
  1332. }
  1333. static int __devinit snd_ice1712_ac97_mixer(struct snd_ice1712 *ice)
  1334. {
  1335. int err, bus_num = 0;
  1336. struct snd_ac97_template ac97;
  1337. struct snd_ac97_bus *pbus;
  1338. static struct snd_ac97_bus_ops con_ops = {
  1339. .write = snd_ice1712_ac97_write,
  1340. .read = snd_ice1712_ac97_read,
  1341. };
  1342. static struct snd_ac97_bus_ops pro_ops = {
  1343. .write = snd_ice1712_pro_ac97_write,
  1344. .read = snd_ice1712_pro_ac97_read,
  1345. };
  1346. if (ice_has_con_ac97(ice)) {
  1347. err = snd_ac97_bus(ice->card, bus_num++, &con_ops, NULL, &pbus);
  1348. if (err < 0)
  1349. return err;
  1350. memset(&ac97, 0, sizeof(ac97));
  1351. ac97.private_data = ice;
  1352. ac97.private_free = snd_ice1712_mixer_free_ac97;
  1353. err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
  1354. if (err < 0)
  1355. printk(KERN_WARNING "ice1712: cannot initialize ac97 for consumer, skipped\n");
  1356. else {
  1357. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_digmix_route_ac97, ice));
  1358. if (err < 0)
  1359. return err;
  1360. return 0;
  1361. }
  1362. }
  1363. if (!(ice->eeprom.data[ICE_EEP1_ACLINK] & ICE1712_CFG_PRO_I2S)) {
  1364. err = snd_ac97_bus(ice->card, bus_num, &pro_ops, NULL, &pbus);
  1365. if (err < 0)
  1366. return err;
  1367. memset(&ac97, 0, sizeof(ac97));
  1368. ac97.private_data = ice;
  1369. ac97.private_free = snd_ice1712_mixer_free_ac97;
  1370. err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
  1371. if (err < 0)
  1372. printk(KERN_WARNING "ice1712: cannot initialize pro ac97, skipped\n");
  1373. else
  1374. return 0;
  1375. }
  1376. /* I2S mixer only */
  1377. strcat(ice->card->mixername, "ICE1712 - multitrack");
  1378. return 0;
  1379. }
  1380. /*
  1381. *
  1382. */
  1383. static inline unsigned int eeprom_double(struct snd_ice1712 *ice, int idx)
  1384. {
  1385. return (unsigned int)ice->eeprom.data[idx] | ((unsigned int)ice->eeprom.data[idx + 1] << 8);
  1386. }
  1387. static void snd_ice1712_proc_read(struct snd_info_entry *entry,
  1388. struct snd_info_buffer *buffer)
  1389. {
  1390. struct snd_ice1712 *ice = entry->private_data;
  1391. unsigned int idx;
  1392. snd_iprintf(buffer, "%s\n\n", ice->card->longname);
  1393. snd_iprintf(buffer, "EEPROM:\n");
  1394. snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
  1395. snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
  1396. snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
  1397. snd_iprintf(buffer, " Codec : 0x%x\n", ice->eeprom.data[ICE_EEP1_CODEC]);
  1398. snd_iprintf(buffer, " ACLink : 0x%x\n", ice->eeprom.data[ICE_EEP1_ACLINK]);
  1399. snd_iprintf(buffer, " I2S ID : 0x%x\n", ice->eeprom.data[ICE_EEP1_I2SID]);
  1400. snd_iprintf(buffer, " S/PDIF : 0x%x\n", ice->eeprom.data[ICE_EEP1_SPDIF]);
  1401. snd_iprintf(buffer, " GPIO mask : 0x%x\n", ice->eeprom.gpiomask);
  1402. snd_iprintf(buffer, " GPIO state : 0x%x\n", ice->eeprom.gpiostate);
  1403. snd_iprintf(buffer, " GPIO direction : 0x%x\n", ice->eeprom.gpiodir);
  1404. snd_iprintf(buffer, " AC'97 main : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_MAIN_LO));
  1405. snd_iprintf(buffer, " AC'97 pcm : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_PCM_LO));
  1406. snd_iprintf(buffer, " AC'97 record : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_REC_LO));
  1407. snd_iprintf(buffer, " AC'97 record src : 0x%x\n", ice->eeprom.data[ICE_EEP1_AC97_RECSRC]);
  1408. for (idx = 0; idx < 4; idx++)
  1409. snd_iprintf(buffer, " DAC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_DAC_ID + idx]);
  1410. for (idx = 0; idx < 4; idx++)
  1411. snd_iprintf(buffer, " ADC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_ADC_ID + idx]);
  1412. for (idx = 0x1c; idx < ice->eeprom.size; idx++)
  1413. snd_iprintf(buffer, " Extra #%02i : 0x%x\n", idx, ice->eeprom.data[idx]);
  1414. snd_iprintf(buffer, "\nRegisters:\n");
  1415. snd_iprintf(buffer, " PSDOUT03 : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_PSDOUT03)));
  1416. snd_iprintf(buffer, " CAPTURE : 0x%08x\n", inl(ICEMT(ice, ROUTE_CAPTURE)));
  1417. snd_iprintf(buffer, " SPDOUT : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_SPDOUT)));
  1418. snd_iprintf(buffer, " RATE : 0x%02x\n", (unsigned)inb(ICEMT(ice, RATE)));
  1419. snd_iprintf(buffer, " GPIO_DATA : 0x%02x\n", (unsigned)snd_ice1712_get_gpio_data(ice));
  1420. snd_iprintf(buffer, " GPIO_WRITE_MASK : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK));
  1421. snd_iprintf(buffer, " GPIO_DIRECTION : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION));
  1422. }
  1423. static void __devinit snd_ice1712_proc_init(struct snd_ice1712 *ice)
  1424. {
  1425. struct snd_info_entry *entry;
  1426. if (!snd_card_proc_new(ice->card, "ice1712", &entry))
  1427. snd_info_set_text_ops(entry, ice, snd_ice1712_proc_read);
  1428. }
  1429. /*
  1430. *
  1431. */
  1432. static int snd_ice1712_eeprom_info(struct snd_kcontrol *kcontrol,
  1433. struct snd_ctl_elem_info *uinfo)
  1434. {
  1435. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  1436. uinfo->count = sizeof(struct snd_ice1712_eeprom);
  1437. return 0;
  1438. }
  1439. static int snd_ice1712_eeprom_get(struct snd_kcontrol *kcontrol,
  1440. struct snd_ctl_elem_value *ucontrol)
  1441. {
  1442. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1443. memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
  1444. return 0;
  1445. }
  1446. static struct snd_kcontrol_new snd_ice1712_eeprom __devinitdata = {
  1447. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  1448. .name = "ICE1712 EEPROM",
  1449. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1450. .info = snd_ice1712_eeprom_info,
  1451. .get = snd_ice1712_eeprom_get
  1452. };
  1453. /*
  1454. */
  1455. static int snd_ice1712_spdif_info(struct snd_kcontrol *kcontrol,
  1456. struct snd_ctl_elem_info *uinfo)
  1457. {
  1458. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1459. uinfo->count = 1;
  1460. return 0;
  1461. }
  1462. static int snd_ice1712_spdif_default_get(struct snd_kcontrol *kcontrol,
  1463. struct snd_ctl_elem_value *ucontrol)
  1464. {
  1465. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1466. if (ice->spdif.ops.default_get)
  1467. ice->spdif.ops.default_get(ice, ucontrol);
  1468. return 0;
  1469. }
  1470. static int snd_ice1712_spdif_default_put(struct snd_kcontrol *kcontrol,
  1471. struct snd_ctl_elem_value *ucontrol)
  1472. {
  1473. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1474. if (ice->spdif.ops.default_put)
  1475. return ice->spdif.ops.default_put(ice, ucontrol);
  1476. return 0;
  1477. }
  1478. static struct snd_kcontrol_new snd_ice1712_spdif_default __devinitdata =
  1479. {
  1480. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1481. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
  1482. .info = snd_ice1712_spdif_info,
  1483. .get = snd_ice1712_spdif_default_get,
  1484. .put = snd_ice1712_spdif_default_put
  1485. };
  1486. static int snd_ice1712_spdif_maskc_get(struct snd_kcontrol *kcontrol,
  1487. struct snd_ctl_elem_value *ucontrol)
  1488. {
  1489. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1490. if (ice->spdif.ops.default_get) {
  1491. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1492. IEC958_AES0_PROFESSIONAL |
  1493. IEC958_AES0_CON_NOT_COPYRIGHT |
  1494. IEC958_AES0_CON_EMPHASIS;
  1495. ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
  1496. IEC958_AES1_CON_CATEGORY;
  1497. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
  1498. } else {
  1499. ucontrol->value.iec958.status[0] = 0xff;
  1500. ucontrol->value.iec958.status[1] = 0xff;
  1501. ucontrol->value.iec958.status[2] = 0xff;
  1502. ucontrol->value.iec958.status[3] = 0xff;
  1503. ucontrol->value.iec958.status[4] = 0xff;
  1504. }
  1505. return 0;
  1506. }
  1507. static int snd_ice1712_spdif_maskp_get(struct snd_kcontrol *kcontrol,
  1508. struct snd_ctl_elem_value *ucontrol)
  1509. {
  1510. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1511. if (ice->spdif.ops.default_get) {
  1512. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1513. IEC958_AES0_PROFESSIONAL |
  1514. IEC958_AES0_PRO_FS |
  1515. IEC958_AES0_PRO_EMPHASIS;
  1516. ucontrol->value.iec958.status[1] = IEC958_AES1_PRO_MODE;
  1517. } else {
  1518. ucontrol->value.iec958.status[0] = 0xff;
  1519. ucontrol->value.iec958.status[1] = 0xff;
  1520. ucontrol->value.iec958.status[2] = 0xff;
  1521. ucontrol->value.iec958.status[3] = 0xff;
  1522. ucontrol->value.iec958.status[4] = 0xff;
  1523. }
  1524. return 0;
  1525. }
  1526. static struct snd_kcontrol_new snd_ice1712_spdif_maskc __devinitdata =
  1527. {
  1528. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1529. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1530. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
  1531. .info = snd_ice1712_spdif_info,
  1532. .get = snd_ice1712_spdif_maskc_get,
  1533. };
  1534. static struct snd_kcontrol_new snd_ice1712_spdif_maskp __devinitdata =
  1535. {
  1536. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1537. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1538. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
  1539. .info = snd_ice1712_spdif_info,
  1540. .get = snd_ice1712_spdif_maskp_get,
  1541. };
  1542. static int snd_ice1712_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1543. struct snd_ctl_elem_value *ucontrol)
  1544. {
  1545. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1546. if (ice->spdif.ops.stream_get)
  1547. ice->spdif.ops.stream_get(ice, ucontrol);
  1548. return 0;
  1549. }
  1550. static int snd_ice1712_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1551. struct snd_ctl_elem_value *ucontrol)
  1552. {
  1553. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1554. if (ice->spdif.ops.stream_put)
  1555. return ice->spdif.ops.stream_put(ice, ucontrol);
  1556. return 0;
  1557. }
  1558. static struct snd_kcontrol_new snd_ice1712_spdif_stream __devinitdata =
  1559. {
  1560. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1561. SNDRV_CTL_ELEM_ACCESS_INACTIVE),
  1562. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1563. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
  1564. .info = snd_ice1712_spdif_info,
  1565. .get = snd_ice1712_spdif_stream_get,
  1566. .put = snd_ice1712_spdif_stream_put
  1567. };
  1568. int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol,
  1569. struct snd_ctl_elem_value *ucontrol)
  1570. {
  1571. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1572. unsigned char mask = kcontrol->private_value & 0xff;
  1573. int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
  1574. snd_ice1712_save_gpio_status(ice);
  1575. ucontrol->value.integer.value[0] =
  1576. (snd_ice1712_gpio_read(ice) & mask ? 1 : 0) ^ invert;
  1577. snd_ice1712_restore_gpio_status(ice);
  1578. return 0;
  1579. }
  1580. int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
  1581. struct snd_ctl_elem_value *ucontrol)
  1582. {
  1583. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1584. unsigned char mask = kcontrol->private_value & 0xff;
  1585. int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
  1586. unsigned int val, nval;
  1587. if (kcontrol->private_value & (1 << 31))
  1588. return -EPERM;
  1589. nval = (ucontrol->value.integer.value[0] ? mask : 0) ^ invert;
  1590. snd_ice1712_save_gpio_status(ice);
  1591. val = snd_ice1712_gpio_read(ice);
  1592. nval |= val & ~mask;
  1593. if (val != nval)
  1594. snd_ice1712_gpio_write(ice, nval);
  1595. snd_ice1712_restore_gpio_status(ice);
  1596. return val != nval;
  1597. }
  1598. /*
  1599. * rate
  1600. */
  1601. static int snd_ice1712_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
  1602. struct snd_ctl_elem_info *uinfo)
  1603. {
  1604. static const char * const texts[] = {
  1605. "8000", /* 0: 6 */
  1606. "9600", /* 1: 3 */
  1607. "11025", /* 2: 10 */
  1608. "12000", /* 3: 2 */
  1609. "16000", /* 4: 5 */
  1610. "22050", /* 5: 9 */
  1611. "24000", /* 6: 1 */
  1612. "32000", /* 7: 4 */
  1613. "44100", /* 8: 8 */
  1614. "48000", /* 9: 0 */
  1615. "64000", /* 10: 15 */
  1616. "88200", /* 11: 11 */
  1617. "96000", /* 12: 7 */
  1618. "IEC958 Input", /* 13: -- */
  1619. };
  1620. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1621. uinfo->count = 1;
  1622. uinfo->value.enumerated.items = 14;
  1623. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1624. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1625. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1626. return 0;
  1627. }
  1628. static int snd_ice1712_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
  1629. struct snd_ctl_elem_value *ucontrol)
  1630. {
  1631. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1632. static const unsigned char xlate[16] = {
  1633. 9, 6, 3, 1, 7, 4, 0, 12, 8, 5, 2, 11, 255, 255, 255, 10
  1634. };
  1635. unsigned char val;
  1636. spin_lock_irq(&ice->reg_lock);
  1637. if (is_spdif_master(ice)) {
  1638. ucontrol->value.enumerated.item[0] = 13;
  1639. } else {
  1640. val = xlate[inb(ICEMT(ice, RATE)) & 15];
  1641. if (val == 255) {
  1642. snd_BUG();
  1643. val = 0;
  1644. }
  1645. ucontrol->value.enumerated.item[0] = val;
  1646. }
  1647. spin_unlock_irq(&ice->reg_lock);
  1648. return 0;
  1649. }
  1650. static int snd_ice1712_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
  1651. struct snd_ctl_elem_value *ucontrol)
  1652. {
  1653. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1654. static const unsigned int xrate[13] = {
  1655. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1656. 32000, 44100, 48000, 64000, 88200, 96000
  1657. };
  1658. unsigned char oval;
  1659. int change = 0;
  1660. spin_lock_irq(&ice->reg_lock);
  1661. oval = inb(ICEMT(ice, RATE));
  1662. if (ucontrol->value.enumerated.item[0] == 13) {
  1663. outb(oval | ICE1712_SPDIF_MASTER, ICEMT(ice, RATE));
  1664. } else {
  1665. PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
  1666. spin_unlock_irq(&ice->reg_lock);
  1667. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 1);
  1668. spin_lock_irq(&ice->reg_lock);
  1669. }
  1670. change = inb(ICEMT(ice, RATE)) != oval;
  1671. spin_unlock_irq(&ice->reg_lock);
  1672. if ((oval & ICE1712_SPDIF_MASTER) !=
  1673. (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER))
  1674. snd_ice1712_set_input_clock_source(ice, is_spdif_master(ice));
  1675. return change;
  1676. }
  1677. static struct snd_kcontrol_new snd_ice1712_pro_internal_clock __devinitdata = {
  1678. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1679. .name = "Multi Track Internal Clock",
  1680. .info = snd_ice1712_pro_internal_clock_info,
  1681. .get = snd_ice1712_pro_internal_clock_get,
  1682. .put = snd_ice1712_pro_internal_clock_put
  1683. };
  1684. static int snd_ice1712_pro_internal_clock_default_info(struct snd_kcontrol *kcontrol,
  1685. struct snd_ctl_elem_info *uinfo)
  1686. {
  1687. static const char * const texts[] = {
  1688. "8000", /* 0: 6 */
  1689. "9600", /* 1: 3 */
  1690. "11025", /* 2: 10 */
  1691. "12000", /* 3: 2 */
  1692. "16000", /* 4: 5 */
  1693. "22050", /* 5: 9 */
  1694. "24000", /* 6: 1 */
  1695. "32000", /* 7: 4 */
  1696. "44100", /* 8: 8 */
  1697. "48000", /* 9: 0 */
  1698. "64000", /* 10: 15 */
  1699. "88200", /* 11: 11 */
  1700. "96000", /* 12: 7 */
  1701. /* "IEC958 Input", 13: -- */
  1702. };
  1703. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1704. uinfo->count = 1;
  1705. uinfo->value.enumerated.items = 13;
  1706. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1707. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1708. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1709. return 0;
  1710. }
  1711. static int snd_ice1712_pro_internal_clock_default_get(struct snd_kcontrol *kcontrol,
  1712. struct snd_ctl_elem_value *ucontrol)
  1713. {
  1714. int val;
  1715. static const unsigned int xrate[13] = {
  1716. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1717. 32000, 44100, 48000, 64000, 88200, 96000
  1718. };
  1719. for (val = 0; val < 13; val++) {
  1720. if (xrate[val] == PRO_RATE_DEFAULT)
  1721. break;
  1722. }
  1723. ucontrol->value.enumerated.item[0] = val;
  1724. return 0;
  1725. }
  1726. static int snd_ice1712_pro_internal_clock_default_put(struct snd_kcontrol *kcontrol,
  1727. struct snd_ctl_elem_value *ucontrol)
  1728. {
  1729. static const unsigned int xrate[13] = {
  1730. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1731. 32000, 44100, 48000, 64000, 88200, 96000
  1732. };
  1733. unsigned char oval;
  1734. int change = 0;
  1735. oval = PRO_RATE_DEFAULT;
  1736. PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
  1737. change = PRO_RATE_DEFAULT != oval;
  1738. return change;
  1739. }
  1740. static struct snd_kcontrol_new snd_ice1712_pro_internal_clock_default __devinitdata = {
  1741. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1742. .name = "Multi Track Internal Clock Default",
  1743. .info = snd_ice1712_pro_internal_clock_default_info,
  1744. .get = snd_ice1712_pro_internal_clock_default_get,
  1745. .put = snd_ice1712_pro_internal_clock_default_put
  1746. };
  1747. #define snd_ice1712_pro_rate_locking_info snd_ctl_boolean_mono_info
  1748. static int snd_ice1712_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
  1749. struct snd_ctl_elem_value *ucontrol)
  1750. {
  1751. ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
  1752. return 0;
  1753. }
  1754. static int snd_ice1712_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
  1755. struct snd_ctl_elem_value *ucontrol)
  1756. {
  1757. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1758. int change = 0, nval;
  1759. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1760. spin_lock_irq(&ice->reg_lock);
  1761. change = PRO_RATE_LOCKED != nval;
  1762. PRO_RATE_LOCKED = nval;
  1763. spin_unlock_irq(&ice->reg_lock);
  1764. return change;
  1765. }
  1766. static struct snd_kcontrol_new snd_ice1712_pro_rate_locking __devinitdata = {
  1767. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1768. .name = "Multi Track Rate Locking",
  1769. .info = snd_ice1712_pro_rate_locking_info,
  1770. .get = snd_ice1712_pro_rate_locking_get,
  1771. .put = snd_ice1712_pro_rate_locking_put
  1772. };
  1773. #define snd_ice1712_pro_rate_reset_info snd_ctl_boolean_mono_info
  1774. static int snd_ice1712_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
  1775. struct snd_ctl_elem_value *ucontrol)
  1776. {
  1777. ucontrol->value.integer.value[0] = PRO_RATE_RESET;
  1778. return 0;
  1779. }
  1780. static int snd_ice1712_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
  1781. struct snd_ctl_elem_value *ucontrol)
  1782. {
  1783. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1784. int change = 0, nval;
  1785. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1786. spin_lock_irq(&ice->reg_lock);
  1787. change = PRO_RATE_RESET != nval;
  1788. PRO_RATE_RESET = nval;
  1789. spin_unlock_irq(&ice->reg_lock);
  1790. return change;
  1791. }
  1792. static struct snd_kcontrol_new snd_ice1712_pro_rate_reset __devinitdata = {
  1793. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1794. .name = "Multi Track Rate Reset",
  1795. .info = snd_ice1712_pro_rate_reset_info,
  1796. .get = snd_ice1712_pro_rate_reset_get,
  1797. .put = snd_ice1712_pro_rate_reset_put
  1798. };
  1799. /*
  1800. * routing
  1801. */
  1802. static int snd_ice1712_pro_route_info(struct snd_kcontrol *kcontrol,
  1803. struct snd_ctl_elem_info *uinfo)
  1804. {
  1805. static const char * const texts[] = {
  1806. "PCM Out", /* 0 */
  1807. "H/W In 0", "H/W In 1", "H/W In 2", "H/W In 3", /* 1-4 */
  1808. "H/W In 4", "H/W In 5", "H/W In 6", "H/W In 7", /* 5-8 */
  1809. "IEC958 In L", "IEC958 In R", /* 9-10 */
  1810. "Digital Mixer", /* 11 - optional */
  1811. };
  1812. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1813. uinfo->count = 1;
  1814. uinfo->value.enumerated.items =
  1815. snd_ctl_get_ioffidx(kcontrol, &uinfo->id) < 2 ? 12 : 11;
  1816. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1817. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1818. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1819. return 0;
  1820. }
  1821. static int snd_ice1712_pro_route_analog_get(struct snd_kcontrol *kcontrol,
  1822. struct snd_ctl_elem_value *ucontrol)
  1823. {
  1824. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1825. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1826. unsigned int val, cval;
  1827. spin_lock_irq(&ice->reg_lock);
  1828. val = inw(ICEMT(ice, ROUTE_PSDOUT03));
  1829. cval = inl(ICEMT(ice, ROUTE_CAPTURE));
  1830. spin_unlock_irq(&ice->reg_lock);
  1831. val >>= ((idx % 2) * 8) + ((idx / 2) * 2);
  1832. val &= 3;
  1833. cval >>= ((idx / 2) * 8) + ((idx % 2) * 4);
  1834. if (val == 1 && idx < 2)
  1835. ucontrol->value.enumerated.item[0] = 11;
  1836. else if (val == 2)
  1837. ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
  1838. else if (val == 3)
  1839. ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
  1840. else
  1841. ucontrol->value.enumerated.item[0] = 0;
  1842. return 0;
  1843. }
  1844. static int snd_ice1712_pro_route_analog_put(struct snd_kcontrol *kcontrol,
  1845. struct snd_ctl_elem_value *ucontrol)
  1846. {
  1847. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1848. int change, shift;
  1849. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1850. unsigned int val, old_val, nval;
  1851. /* update PSDOUT */
  1852. if (ucontrol->value.enumerated.item[0] >= 11)
  1853. nval = idx < 2 ? 1 : 0; /* dig mixer (or pcm) */
  1854. else if (ucontrol->value.enumerated.item[0] >= 9)
  1855. nval = 3; /* spdif in */
  1856. else if (ucontrol->value.enumerated.item[0] >= 1)
  1857. nval = 2; /* analog in */
  1858. else
  1859. nval = 0; /* pcm */
  1860. shift = ((idx % 2) * 8) + ((idx / 2) * 2);
  1861. spin_lock_irq(&ice->reg_lock);
  1862. val = old_val = inw(ICEMT(ice, ROUTE_PSDOUT03));
  1863. val &= ~(0x03 << shift);
  1864. val |= nval << shift;
  1865. change = val != old_val;
  1866. if (change)
  1867. outw(val, ICEMT(ice, ROUTE_PSDOUT03));
  1868. spin_unlock_irq(&ice->reg_lock);
  1869. if (nval < 2) /* dig mixer of pcm */
  1870. return change;
  1871. /* update CAPTURE */
  1872. spin_lock_irq(&ice->reg_lock);
  1873. val = old_val = inl(ICEMT(ice, ROUTE_CAPTURE));
  1874. shift = ((idx / 2) * 8) + ((idx % 2) * 4);
  1875. if (nval == 2) { /* analog in */
  1876. nval = ucontrol->value.enumerated.item[0] - 1;
  1877. val &= ~(0x07 << shift);
  1878. val |= nval << shift;
  1879. } else { /* spdif in */
  1880. nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
  1881. val &= ~(0x08 << shift);
  1882. val |= nval << shift;
  1883. }
  1884. if (val != old_val) {
  1885. change = 1;
  1886. outl(val, ICEMT(ice, ROUTE_CAPTURE));
  1887. }
  1888. spin_unlock_irq(&ice->reg_lock);
  1889. return change;
  1890. }
  1891. static int snd_ice1712_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
  1892. struct snd_ctl_elem_value *ucontrol)
  1893. {
  1894. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1895. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1896. unsigned int val, cval;
  1897. val = inw(ICEMT(ice, ROUTE_SPDOUT));
  1898. cval = (val >> (idx * 4 + 8)) & 0x0f;
  1899. val = (val >> (idx * 2)) & 0x03;
  1900. if (val == 1)
  1901. ucontrol->value.enumerated.item[0] = 11;
  1902. else if (val == 2)
  1903. ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
  1904. else if (val == 3)
  1905. ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
  1906. else
  1907. ucontrol->value.enumerated.item[0] = 0;
  1908. return 0;
  1909. }
  1910. static int snd_ice1712_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
  1911. struct snd_ctl_elem_value *ucontrol)
  1912. {
  1913. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1914. int change, shift;
  1915. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1916. unsigned int val, old_val, nval;
  1917. /* update SPDOUT */
  1918. spin_lock_irq(&ice->reg_lock);
  1919. val = old_val = inw(ICEMT(ice, ROUTE_SPDOUT));
  1920. if (ucontrol->value.enumerated.item[0] >= 11)
  1921. nval = 1;
  1922. else if (ucontrol->value.enumerated.item[0] >= 9)
  1923. nval = 3;
  1924. else if (ucontrol->value.enumerated.item[0] >= 1)
  1925. nval = 2;
  1926. else
  1927. nval = 0;
  1928. shift = idx * 2;
  1929. val &= ~(0x03 << shift);
  1930. val |= nval << shift;
  1931. shift = idx * 4 + 8;
  1932. if (nval == 2) {
  1933. nval = ucontrol->value.enumerated.item[0] - 1;
  1934. val &= ~(0x07 << shift);
  1935. val |= nval << shift;
  1936. } else if (nval == 3) {
  1937. nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
  1938. val &= ~(0x08 << shift);
  1939. val |= nval << shift;
  1940. }
  1941. change = val != old_val;
  1942. if (change)
  1943. outw(val, ICEMT(ice, ROUTE_SPDOUT));
  1944. spin_unlock_irq(&ice->reg_lock);
  1945. return change;
  1946. }
  1947. static struct snd_kcontrol_new snd_ice1712_mixer_pro_analog_route __devinitdata = {
  1948. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1949. .name = "H/W Playback Route",
  1950. .info = snd_ice1712_pro_route_info,
  1951. .get = snd_ice1712_pro_route_analog_get,
  1952. .put = snd_ice1712_pro_route_analog_put,
  1953. };
  1954. static struct snd_kcontrol_new snd_ice1712_mixer_pro_spdif_route __devinitdata = {
  1955. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1956. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, NONE) "Route",
  1957. .info = snd_ice1712_pro_route_info,
  1958. .get = snd_ice1712_pro_route_spdif_get,
  1959. .put = snd_ice1712_pro_route_spdif_put,
  1960. .count = 2,
  1961. };
  1962. static int snd_ice1712_pro_volume_rate_info(struct snd_kcontrol *kcontrol,
  1963. struct snd_ctl_elem_info *uinfo)
  1964. {
  1965. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1966. uinfo->count = 1;
  1967. uinfo->value.integer.min = 0;
  1968. uinfo->value.integer.max = 255;
  1969. return 0;
  1970. }
  1971. static int snd_ice1712_pro_volume_rate_get(struct snd_kcontrol *kcontrol,
  1972. struct snd_ctl_elem_value *ucontrol)
  1973. {
  1974. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1975. ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_RATE));
  1976. return 0;
  1977. }
  1978. static int snd_ice1712_pro_volume_rate_put(struct snd_kcontrol *kcontrol,
  1979. struct snd_ctl_elem_value *ucontrol)
  1980. {
  1981. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1982. int change;
  1983. spin_lock_irq(&ice->reg_lock);
  1984. change = inb(ICEMT(ice, MONITOR_RATE)) != ucontrol->value.integer.value[0];
  1985. outb(ucontrol->value.integer.value[0], ICEMT(ice, MONITOR_RATE));
  1986. spin_unlock_irq(&ice->reg_lock);
  1987. return change;
  1988. }
  1989. static struct snd_kcontrol_new snd_ice1712_mixer_pro_volume_rate __devinitdata = {
  1990. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1991. .name = "Multi Track Volume Rate",
  1992. .info = snd_ice1712_pro_volume_rate_info,
  1993. .get = snd_ice1712_pro_volume_rate_get,
  1994. .put = snd_ice1712_pro_volume_rate_put
  1995. };
  1996. static int snd_ice1712_pro_peak_info(struct snd_kcontrol *kcontrol,
  1997. struct snd_ctl_elem_info *uinfo)
  1998. {
  1999. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  2000. uinfo->count = 22;
  2001. uinfo->value.integer.min = 0;
  2002. uinfo->value.integer.max = 255;
  2003. return 0;
  2004. }
  2005. static int snd_ice1712_pro_peak_get(struct snd_kcontrol *kcontrol,
  2006. struct snd_ctl_elem_value *ucontrol)
  2007. {
  2008. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  2009. int idx;
  2010. spin_lock_irq(&ice->reg_lock);
  2011. for (idx = 0; idx < 22; idx++) {
  2012. outb(idx, ICEMT(ice, MONITOR_PEAKINDEX));
  2013. ucontrol->value.integer.value[idx] = inb(ICEMT(ice, MONITOR_PEAKDATA));
  2014. }
  2015. spin_unlock_irq(&ice->reg_lock);
  2016. return 0;
  2017. }
  2018. static struct snd_kcontrol_new snd_ice1712_mixer_pro_peak __devinitdata = {
  2019. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  2020. .name = "Multi Track Peak",
  2021. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  2022. .info = snd_ice1712_pro_peak_info,
  2023. .get = snd_ice1712_pro_peak_get
  2024. };
  2025. /*
  2026. *
  2027. */
  2028. /*
  2029. * list of available boards
  2030. */
  2031. static struct snd_ice1712_card_info *card_tables[] __devinitdata = {
  2032. snd_ice1712_hoontech_cards,
  2033. snd_ice1712_delta_cards,
  2034. snd_ice1712_ews_cards,
  2035. NULL,
  2036. };
  2037. static unsigned char __devinit snd_ice1712_read_i2c(struct snd_ice1712 *ice,
  2038. unsigned char dev,
  2039. unsigned char addr)
  2040. {
  2041. long t = 0x10000;
  2042. outb(addr, ICEREG(ice, I2C_BYTE_ADDR));
  2043. outb(dev & ~ICE1712_I2C_WRITE, ICEREG(ice, I2C_DEV_ADDR));
  2044. while (t-- > 0 && (inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_BUSY)) ;
  2045. return inb(ICEREG(ice, I2C_DATA));
  2046. }
  2047. static int __devinit snd_ice1712_read_eeprom(struct snd_ice1712 *ice,
  2048. const char *modelname)
  2049. {
  2050. int dev = 0xa0; /* EEPROM device address */
  2051. unsigned int i, size;
  2052. struct snd_ice1712_card_info * const *tbl, *c;
  2053. if (!modelname || !*modelname) {
  2054. ice->eeprom.subvendor = 0;
  2055. if ((inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_EEPROM) != 0)
  2056. ice->eeprom.subvendor = (snd_ice1712_read_i2c(ice, dev, 0x00) << 0) |
  2057. (snd_ice1712_read_i2c(ice, dev, 0x01) << 8) |
  2058. (snd_ice1712_read_i2c(ice, dev, 0x02) << 16) |
  2059. (snd_ice1712_read_i2c(ice, dev, 0x03) << 24);
  2060. if (ice->eeprom.subvendor == 0 ||
  2061. ice->eeprom.subvendor == (unsigned int)-1) {
  2062. /* invalid subvendor from EEPROM, try the PCI subststem ID instead */
  2063. u16 vendor, device;
  2064. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID, &vendor);
  2065. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
  2066. ice->eeprom.subvendor = ((unsigned int)swab16(vendor) << 16) | swab16(device);
  2067. if (ice->eeprom.subvendor == 0 || ice->eeprom.subvendor == (unsigned int)-1) {
  2068. printk(KERN_ERR "ice1712: No valid ID is found\n");
  2069. return -ENXIO;
  2070. }
  2071. }
  2072. }
  2073. for (tbl = card_tables; *tbl; tbl++) {
  2074. for (c = *tbl; c->subvendor; c++) {
  2075. if (modelname && c->model && !strcmp(modelname, c->model)) {
  2076. printk(KERN_INFO "ice1712: Using board model %s\n", c->name);
  2077. ice->eeprom.subvendor = c->subvendor;
  2078. } else if (c->subvendor != ice->eeprom.subvendor)
  2079. continue;
  2080. if (!c->eeprom_size || !c->eeprom_data)
  2081. goto found;
  2082. /* if the EEPROM is given by the driver, use it */
  2083. snd_printdd("using the defined eeprom..\n");
  2084. ice->eeprom.version = 1;
  2085. ice->eeprom.size = c->eeprom_size + 6;
  2086. memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
  2087. goto read_skipped;
  2088. }
  2089. }
  2090. printk(KERN_WARNING "ice1712: No matching model found for ID 0x%x\n",
  2091. ice->eeprom.subvendor);
  2092. found:
  2093. ice->eeprom.size = snd_ice1712_read_i2c(ice, dev, 0x04);
  2094. if (ice->eeprom.size < 6)
  2095. ice->eeprom.size = 32; /* FIXME: any cards without the correct size? */
  2096. else if (ice->eeprom.size > 32) {
  2097. snd_printk(KERN_ERR "invalid EEPROM (size = %i)\n", ice->eeprom.size);
  2098. return -EIO;
  2099. }
  2100. ice->eeprom.version = snd_ice1712_read_i2c(ice, dev, 0x05);
  2101. if (ice->eeprom.version != 1) {
  2102. snd_printk(KERN_ERR "invalid EEPROM version %i\n",
  2103. ice->eeprom.version);
  2104. /* return -EIO; */
  2105. }
  2106. size = ice->eeprom.size - 6;
  2107. for (i = 0; i < size; i++)
  2108. ice->eeprom.data[i] = snd_ice1712_read_i2c(ice, dev, i + 6);
  2109. read_skipped:
  2110. ice->eeprom.gpiomask = ice->eeprom.data[ICE_EEP1_GPIO_MASK];
  2111. ice->eeprom.gpiostate = ice->eeprom.data[ICE_EEP1_GPIO_STATE];
  2112. ice->eeprom.gpiodir = ice->eeprom.data[ICE_EEP1_GPIO_DIR];
  2113. return 0;
  2114. }
  2115. static int __devinit snd_ice1712_chip_init(struct snd_ice1712 *ice)
  2116. {
  2117. outb(ICE1712_RESET | ICE1712_NATIVE, ICEREG(ice, CONTROL));
  2118. udelay(200);
  2119. outb(ICE1712_NATIVE, ICEREG(ice, CONTROL));
  2120. udelay(200);
  2121. if (ice->eeprom.subvendor == ICE1712_SUBDEVICE_DMX6FIRE &&
  2122. !ice->dxr_enable)
  2123. /* Set eeprom value to limit active ADCs and DACs to 6;
  2124. * Also disable AC97 as no hardware in standard 6fire card/box
  2125. * Note: DXR extensions are not currently supported
  2126. */
  2127. ice->eeprom.data[ICE_EEP1_CODEC] = 0x3a;
  2128. pci_write_config_byte(ice->pci, 0x60, ice->eeprom.data[ICE_EEP1_CODEC]);
  2129. pci_write_config_byte(ice->pci, 0x61, ice->eeprom.data[ICE_EEP1_ACLINK]);
  2130. pci_write_config_byte(ice->pci, 0x62, ice->eeprom.data[ICE_EEP1_I2SID]);
  2131. pci_write_config_byte(ice->pci, 0x63, ice->eeprom.data[ICE_EEP1_SPDIF]);
  2132. if (ice->eeprom.subvendor != ICE1712_SUBDEVICE_STDSP24) {
  2133. ice->gpio.write_mask = ice->eeprom.gpiomask;
  2134. ice->gpio.direction = ice->eeprom.gpiodir;
  2135. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK,
  2136. ice->eeprom.gpiomask);
  2137. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION,
  2138. ice->eeprom.gpiodir);
  2139. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
  2140. ice->eeprom.gpiostate);
  2141. } else {
  2142. ice->gpio.write_mask = 0xc0;
  2143. ice->gpio.direction = 0xff;
  2144. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, 0xc0);
  2145. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, 0xff);
  2146. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
  2147. ICE1712_STDSP24_CLOCK_BIT);
  2148. }
  2149. snd_ice1712_write(ice, ICE1712_IREG_PRO_POWERDOWN, 0);
  2150. if (!(ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97)) {
  2151. outb(ICE1712_AC97_WARM, ICEREG(ice, AC97_CMD));
  2152. udelay(100);
  2153. outb(0, ICEREG(ice, AC97_CMD));
  2154. udelay(200);
  2155. snd_ice1712_write(ice, ICE1712_IREG_CONSUMER_POWERDOWN, 0);
  2156. }
  2157. snd_ice1712_set_pro_rate(ice, 48000, 1);
  2158. return 0;
  2159. }
  2160. int __devinit snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice)
  2161. {
  2162. int err;
  2163. struct snd_kcontrol *kctl;
  2164. if (snd_BUG_ON(!ice->pcm_pro))
  2165. return -EIO;
  2166. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_default, ice));
  2167. if (err < 0)
  2168. return err;
  2169. kctl->id.device = ice->pcm_pro->device;
  2170. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskc, ice));
  2171. if (err < 0)
  2172. return err;
  2173. kctl->id.device = ice->pcm_pro->device;
  2174. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskp, ice));
  2175. if (err < 0)
  2176. return err;
  2177. kctl->id.device = ice->pcm_pro->device;
  2178. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_stream, ice));
  2179. if (err < 0)
  2180. return err;
  2181. kctl->id.device = ice->pcm_pro->device;
  2182. ice->spdif.stream_ctl = kctl;
  2183. return 0;
  2184. }
  2185. static int __devinit snd_ice1712_build_controls(struct snd_ice1712 *ice)
  2186. {
  2187. int err;
  2188. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_eeprom, ice));
  2189. if (err < 0)
  2190. return err;
  2191. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock, ice));
  2192. if (err < 0)
  2193. return err;
  2194. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock_default, ice));
  2195. if (err < 0)
  2196. return err;
  2197. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_locking, ice));
  2198. if (err < 0)
  2199. return err;
  2200. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_reset, ice));
  2201. if (err < 0)
  2202. return err;
  2203. if (ice->num_total_dacs > 0) {
  2204. struct snd_kcontrol_new tmp = snd_ice1712_mixer_pro_analog_route;
  2205. tmp.count = ice->num_total_dacs;
  2206. err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
  2207. if (err < 0)
  2208. return err;
  2209. }
  2210. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_spdif_route, ice));
  2211. if (err < 0)
  2212. return err;
  2213. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_volume_rate, ice));
  2214. if (err < 0)
  2215. return err;
  2216. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_peak, ice));
  2217. if (err < 0)
  2218. return err;
  2219. return 0;
  2220. }
  2221. static int snd_ice1712_free(struct snd_ice1712 *ice)
  2222. {
  2223. if (!ice->port)
  2224. goto __hw_end;
  2225. /* mask all interrupts */
  2226. outb(0xc0, ICEMT(ice, IRQ));
  2227. outb(0xff, ICEREG(ice, IRQMASK));
  2228. /* --- */
  2229. __hw_end:
  2230. if (ice->irq >= 0)
  2231. free_irq(ice->irq, ice);
  2232. if (ice->port)
  2233. pci_release_regions(ice->pci);
  2234. snd_ice1712_akm4xxx_free(ice);
  2235. pci_disable_device(ice->pci);
  2236. kfree(ice->spec);
  2237. kfree(ice);
  2238. return 0;
  2239. }
  2240. static int snd_ice1712_dev_free(struct snd_device *device)
  2241. {
  2242. struct snd_ice1712 *ice = device->device_data;
  2243. return snd_ice1712_free(ice);
  2244. }
  2245. static int __devinit snd_ice1712_create(struct snd_card *card,
  2246. struct pci_dev *pci,
  2247. const char *modelname,
  2248. int omni,
  2249. int cs8427_timeout,
  2250. int dxr_enable,
  2251. struct snd_ice1712 **r_ice1712)
  2252. {
  2253. struct snd_ice1712 *ice;
  2254. int err;
  2255. static struct snd_device_ops ops = {
  2256. .dev_free = snd_ice1712_dev_free,
  2257. };
  2258. *r_ice1712 = NULL;
  2259. /* enable PCI device */
  2260. err = pci_enable_device(pci);
  2261. if (err < 0)
  2262. return err;
  2263. /* check, if we can restrict PCI DMA transfers to 28 bits */
  2264. if (pci_set_dma_mask(pci, DMA_BIT_MASK(28)) < 0 ||
  2265. pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(28)) < 0) {
  2266. snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
  2267. pci_disable_device(pci);
  2268. return -ENXIO;
  2269. }
  2270. ice = kzalloc(sizeof(*ice), GFP_KERNEL);
  2271. if (ice == NULL) {
  2272. pci_disable_device(pci);
  2273. return -ENOMEM;
  2274. }
  2275. ice->omni = omni ? 1 : 0;
  2276. if (cs8427_timeout < 1)
  2277. cs8427_timeout = 1;
  2278. else if (cs8427_timeout > 1000)
  2279. cs8427_timeout = 1000;
  2280. ice->cs8427_timeout = cs8427_timeout;
  2281. ice->dxr_enable = dxr_enable;
  2282. spin_lock_init(&ice->reg_lock);
  2283. mutex_init(&ice->gpio_mutex);
  2284. mutex_init(&ice->i2c_mutex);
  2285. mutex_init(&ice->open_mutex);
  2286. ice->gpio.set_mask = snd_ice1712_set_gpio_mask;
  2287. ice->gpio.get_mask = snd_ice1712_get_gpio_mask;
  2288. ice->gpio.set_dir = snd_ice1712_set_gpio_dir;
  2289. ice->gpio.get_dir = snd_ice1712_get_gpio_dir;
  2290. ice->gpio.set_data = snd_ice1712_set_gpio_data;
  2291. ice->gpio.get_data = snd_ice1712_get_gpio_data;
  2292. ice->spdif.cs8403_bits =
  2293. ice->spdif.cs8403_stream_bits = (0x01 | /* consumer format */
  2294. 0x10 | /* no emphasis */
  2295. 0x20); /* PCM encoder/decoder */
  2296. ice->card = card;
  2297. ice->pci = pci;
  2298. ice->irq = -1;
  2299. pci_set_master(pci);
  2300. pci_write_config_word(ice->pci, 0x40, 0x807f);
  2301. pci_write_config_word(ice->pci, 0x42, 0x0006);
  2302. snd_ice1712_proc_init(ice);
  2303. synchronize_irq(pci->irq);
  2304. card->private_data = ice;
  2305. err = pci_request_regions(pci, "ICE1712");
  2306. if (err < 0) {
  2307. kfree(ice);
  2308. pci_disable_device(pci);
  2309. return err;
  2310. }
  2311. ice->port = pci_resource_start(pci, 0);
  2312. ice->ddma_port = pci_resource_start(pci, 1);
  2313. ice->dmapath_port = pci_resource_start(pci, 2);
  2314. ice->profi_port = pci_resource_start(pci, 3);
  2315. if (request_irq(pci->irq, snd_ice1712_interrupt, IRQF_SHARED,
  2316. KBUILD_MODNAME, ice)) {
  2317. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  2318. snd_ice1712_free(ice);
  2319. return -EIO;
  2320. }
  2321. ice->irq = pci->irq;
  2322. if (snd_ice1712_read_eeprom(ice, modelname) < 0) {
  2323. snd_ice1712_free(ice);
  2324. return -EIO;
  2325. }
  2326. if (snd_ice1712_chip_init(ice) < 0) {
  2327. snd_ice1712_free(ice);
  2328. return -EIO;
  2329. }
  2330. /* unmask used interrupts */
  2331. outb(((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) == 0 ?
  2332. ICE1712_IRQ_MPU2 : 0) |
  2333. ((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97) ?
  2334. ICE1712_IRQ_PBKDS | ICE1712_IRQ_CONCAP | ICE1712_IRQ_CONPBK : 0),
  2335. ICEREG(ice, IRQMASK));
  2336. outb(0x00, ICEMT(ice, IRQ));
  2337. err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops);
  2338. if (err < 0) {
  2339. snd_ice1712_free(ice);
  2340. return err;
  2341. }
  2342. snd_card_set_dev(card, &pci->dev);
  2343. *r_ice1712 = ice;
  2344. return 0;
  2345. }
  2346. /*
  2347. *
  2348. * Registration
  2349. *
  2350. */
  2351. static struct snd_ice1712_card_info no_matched __devinitdata;
  2352. static int __devinit snd_ice1712_probe(struct pci_dev *pci,
  2353. const struct pci_device_id *pci_id)
  2354. {
  2355. static int dev;
  2356. struct snd_card *card;
  2357. struct snd_ice1712 *ice;
  2358. int pcm_dev = 0, err;
  2359. struct snd_ice1712_card_info * const *tbl, *c;
  2360. if (dev >= SNDRV_CARDS)
  2361. return -ENODEV;
  2362. if (!enable[dev]) {
  2363. dev++;
  2364. return -ENOENT;
  2365. }
  2366. err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
  2367. if (err < 0)
  2368. return err;
  2369. strcpy(card->driver, "ICE1712");
  2370. strcpy(card->shortname, "ICEnsemble ICE1712");
  2371. err = snd_ice1712_create(card, pci, model[dev], omni[dev],
  2372. cs8427_timeout[dev], dxr_enable[dev], &ice);
  2373. if (err < 0) {
  2374. snd_card_free(card);
  2375. return err;
  2376. }
  2377. for (tbl = card_tables; *tbl; tbl++) {
  2378. for (c = *tbl; c->subvendor; c++) {
  2379. if (c->subvendor == ice->eeprom.subvendor) {
  2380. strcpy(card->shortname, c->name);
  2381. if (c->driver) /* specific driver? */
  2382. strcpy(card->driver, c->driver);
  2383. if (c->chip_init) {
  2384. err = c->chip_init(ice);
  2385. if (err < 0) {
  2386. snd_card_free(card);
  2387. return err;
  2388. }
  2389. }
  2390. goto __found;
  2391. }
  2392. }
  2393. }
  2394. c = &no_matched;
  2395. __found:
  2396. err = snd_ice1712_pcm_profi(ice, pcm_dev++, NULL);
  2397. if (err < 0) {
  2398. snd_card_free(card);
  2399. return err;
  2400. }
  2401. if (ice_has_con_ac97(ice)) {
  2402. err = snd_ice1712_pcm(ice, pcm_dev++, NULL);
  2403. if (err < 0) {
  2404. snd_card_free(card);
  2405. return err;
  2406. }
  2407. }
  2408. err = snd_ice1712_ac97_mixer(ice);
  2409. if (err < 0) {
  2410. snd_card_free(card);
  2411. return err;
  2412. }
  2413. err = snd_ice1712_build_controls(ice);
  2414. if (err < 0) {
  2415. snd_card_free(card);
  2416. return err;
  2417. }
  2418. if (c->build_controls) {
  2419. err = c->build_controls(ice);
  2420. if (err < 0) {
  2421. snd_card_free(card);
  2422. return err;
  2423. }
  2424. }
  2425. if (ice_has_con_ac97(ice)) {
  2426. err = snd_ice1712_pcm_ds(ice, pcm_dev++, NULL);
  2427. if (err < 0) {
  2428. snd_card_free(card);
  2429. return err;
  2430. }
  2431. }
  2432. if (!c->no_mpu401) {
  2433. err = snd_mpu401_uart_new(card, 0, MPU401_HW_ICE1712,
  2434. ICEREG(ice, MPU1_CTRL),
  2435. c->mpu401_1_info_flags |
  2436. MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
  2437. -1, &ice->rmidi[0]);
  2438. if (err < 0) {
  2439. snd_card_free(card);
  2440. return err;
  2441. }
  2442. if (c->mpu401_1_name)
  2443. /* Preferred name available in card_info */
  2444. snprintf(ice->rmidi[0]->name,
  2445. sizeof(ice->rmidi[0]->name),
  2446. "%s %d", c->mpu401_1_name, card->number);
  2447. if (ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) {
  2448. /* 2nd port used */
  2449. err = snd_mpu401_uart_new(card, 1, MPU401_HW_ICE1712,
  2450. ICEREG(ice, MPU2_CTRL),
  2451. c->mpu401_2_info_flags |
  2452. MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
  2453. -1, &ice->rmidi[1]);
  2454. if (err < 0) {
  2455. snd_card_free(card);
  2456. return err;
  2457. }
  2458. if (c->mpu401_2_name)
  2459. /* Preferred name available in card_info */
  2460. snprintf(ice->rmidi[1]->name,
  2461. sizeof(ice->rmidi[1]->name),
  2462. "%s %d", c->mpu401_2_name,
  2463. card->number);
  2464. }
  2465. }
  2466. snd_ice1712_set_input_clock_source(ice, 0);
  2467. sprintf(card->longname, "%s at 0x%lx, irq %i",
  2468. card->shortname, ice->port, ice->irq);
  2469. err = snd_card_register(card);
  2470. if (err < 0) {
  2471. snd_card_free(card);
  2472. return err;
  2473. }
  2474. pci_set_drvdata(pci, card);
  2475. dev++;
  2476. return 0;
  2477. }
  2478. static void __devexit snd_ice1712_remove(struct pci_dev *pci)
  2479. {
  2480. snd_card_free(pci_get_drvdata(pci));
  2481. pci_set_drvdata(pci, NULL);
  2482. }
  2483. static struct pci_driver driver = {
  2484. .name = KBUILD_MODNAME,
  2485. .id_table = snd_ice1712_ids,
  2486. .probe = snd_ice1712_probe,
  2487. .remove = __devexit_p(snd_ice1712_remove),
  2488. };
  2489. static int __init alsa_card_ice1712_init(void)
  2490. {
  2491. return pci_register_driver(&driver);
  2492. }
  2493. static void __exit alsa_card_ice1712_exit(void)
  2494. {
  2495. pci_unregister_driver(&driver);
  2496. }
  2497. module_init(alsa_card_ice1712_init)
  2498. module_exit(alsa_card_ice1712_exit)