spi-nuc900.c 9.9 KB

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  1. /*
  2. * Copyright (c) 2009 Nuvoton technology.
  3. * Wan ZongShun <mcuos.com@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. */
  10. #include <linux/module.h>
  11. #include <linux/init.h>
  12. #include <linux/spinlock.h>
  13. #include <linux/workqueue.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/delay.h>
  16. #include <linux/errno.h>
  17. #include <linux/err.h>
  18. #include <linux/clk.h>
  19. #include <linux/device.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/gpio.h>
  22. #include <linux/io.h>
  23. #include <linux/slab.h>
  24. #include <linux/spi/spi.h>
  25. #include <linux/spi/spi_bitbang.h>
  26. #include <mach/nuc900_spi.h>
  27. /* usi registers offset */
  28. #define USI_CNT 0x00
  29. #define USI_DIV 0x04
  30. #define USI_SSR 0x08
  31. #define USI_RX0 0x10
  32. #define USI_TX0 0x10
  33. /* usi register bit */
  34. #define ENINT (0x01 << 17)
  35. #define ENFLG (0x01 << 16)
  36. #define TXNUM (0x03 << 8)
  37. #define TXNEG (0x01 << 2)
  38. #define RXNEG (0x01 << 1)
  39. #define LSB (0x01 << 10)
  40. #define SELECTLEV (0x01 << 2)
  41. #define SELECTPOL (0x01 << 31)
  42. #define SELECTSLAVE 0x01
  43. #define GOBUSY 0x01
  44. struct nuc900_spi {
  45. struct spi_bitbang bitbang;
  46. struct completion done;
  47. void __iomem *regs;
  48. int irq;
  49. int len;
  50. int count;
  51. const unsigned char *tx;
  52. unsigned char *rx;
  53. struct clk *clk;
  54. struct resource *ioarea;
  55. struct spi_master *master;
  56. struct spi_device *curdev;
  57. struct device *dev;
  58. struct nuc900_spi_info *pdata;
  59. spinlock_t lock;
  60. struct resource *res;
  61. };
  62. static inline struct nuc900_spi *to_hw(struct spi_device *sdev)
  63. {
  64. return spi_master_get_devdata(sdev->master);
  65. }
  66. static void nuc900_slave_select(struct spi_device *spi, unsigned int ssr)
  67. {
  68. struct nuc900_spi *hw = to_hw(spi);
  69. unsigned int val;
  70. unsigned int cs = spi->mode & SPI_CS_HIGH ? 1 : 0;
  71. unsigned int cpol = spi->mode & SPI_CPOL ? 1 : 0;
  72. unsigned long flags;
  73. spin_lock_irqsave(&hw->lock, flags);
  74. val = __raw_readl(hw->regs + USI_SSR);
  75. if (!cs)
  76. val &= ~SELECTLEV;
  77. else
  78. val |= SELECTLEV;
  79. if (!ssr)
  80. val &= ~SELECTSLAVE;
  81. else
  82. val |= SELECTSLAVE;
  83. __raw_writel(val, hw->regs + USI_SSR);
  84. val = __raw_readl(hw->regs + USI_CNT);
  85. if (!cpol)
  86. val &= ~SELECTPOL;
  87. else
  88. val |= SELECTPOL;
  89. __raw_writel(val, hw->regs + USI_CNT);
  90. spin_unlock_irqrestore(&hw->lock, flags);
  91. }
  92. static void nuc900_spi_chipsel(struct spi_device *spi, int value)
  93. {
  94. switch (value) {
  95. case BITBANG_CS_INACTIVE:
  96. nuc900_slave_select(spi, 0);
  97. break;
  98. case BITBANG_CS_ACTIVE:
  99. nuc900_slave_select(spi, 1);
  100. break;
  101. }
  102. }
  103. static void nuc900_spi_setup_txnum(struct nuc900_spi *hw,
  104. unsigned int txnum)
  105. {
  106. unsigned int val;
  107. unsigned long flags;
  108. spin_lock_irqsave(&hw->lock, flags);
  109. val = __raw_readl(hw->regs + USI_CNT);
  110. if (!txnum)
  111. val &= ~TXNUM;
  112. else
  113. val |= txnum << 0x08;
  114. __raw_writel(val, hw->regs + USI_CNT);
  115. spin_unlock_irqrestore(&hw->lock, flags);
  116. }
  117. static void nuc900_spi_setup_txbitlen(struct nuc900_spi *hw,
  118. unsigned int txbitlen)
  119. {
  120. unsigned int val;
  121. unsigned long flags;
  122. spin_lock_irqsave(&hw->lock, flags);
  123. val = __raw_readl(hw->regs + USI_CNT);
  124. val |= (txbitlen << 0x03);
  125. __raw_writel(val, hw->regs + USI_CNT);
  126. spin_unlock_irqrestore(&hw->lock, flags);
  127. }
  128. static void nuc900_spi_gobusy(struct nuc900_spi *hw)
  129. {
  130. unsigned int val;
  131. unsigned long flags;
  132. spin_lock_irqsave(&hw->lock, flags);
  133. val = __raw_readl(hw->regs + USI_CNT);
  134. val |= GOBUSY;
  135. __raw_writel(val, hw->regs + USI_CNT);
  136. spin_unlock_irqrestore(&hw->lock, flags);
  137. }
  138. static int nuc900_spi_setupxfer(struct spi_device *spi,
  139. struct spi_transfer *t)
  140. {
  141. return 0;
  142. }
  143. static int nuc900_spi_setup(struct spi_device *spi)
  144. {
  145. return 0;
  146. }
  147. static inline unsigned int hw_txbyte(struct nuc900_spi *hw, int count)
  148. {
  149. return hw->tx ? hw->tx[count] : 0;
  150. }
  151. static int nuc900_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
  152. {
  153. struct nuc900_spi *hw = to_hw(spi);
  154. hw->tx = t->tx_buf;
  155. hw->rx = t->rx_buf;
  156. hw->len = t->len;
  157. hw->count = 0;
  158. __raw_writel(hw_txbyte(hw, 0x0), hw->regs + USI_TX0);
  159. nuc900_spi_gobusy(hw);
  160. wait_for_completion(&hw->done);
  161. return hw->count;
  162. }
  163. static irqreturn_t nuc900_spi_irq(int irq, void *dev)
  164. {
  165. struct nuc900_spi *hw = dev;
  166. unsigned int status;
  167. unsigned int count = hw->count;
  168. status = __raw_readl(hw->regs + USI_CNT);
  169. __raw_writel(status, hw->regs + USI_CNT);
  170. if (status & ENFLG) {
  171. hw->count++;
  172. if (hw->rx)
  173. hw->rx[count] = __raw_readl(hw->regs + USI_RX0);
  174. count++;
  175. if (count < hw->len) {
  176. __raw_writel(hw_txbyte(hw, count), hw->regs + USI_TX0);
  177. nuc900_spi_gobusy(hw);
  178. } else {
  179. complete(&hw->done);
  180. }
  181. return IRQ_HANDLED;
  182. }
  183. complete(&hw->done);
  184. return IRQ_HANDLED;
  185. }
  186. static void nuc900_tx_edge(struct nuc900_spi *hw, unsigned int edge)
  187. {
  188. unsigned int val;
  189. unsigned long flags;
  190. spin_lock_irqsave(&hw->lock, flags);
  191. val = __raw_readl(hw->regs + USI_CNT);
  192. if (edge)
  193. val |= TXNEG;
  194. else
  195. val &= ~TXNEG;
  196. __raw_writel(val, hw->regs + USI_CNT);
  197. spin_unlock_irqrestore(&hw->lock, flags);
  198. }
  199. static void nuc900_rx_edge(struct nuc900_spi *hw, unsigned int edge)
  200. {
  201. unsigned int val;
  202. unsigned long flags;
  203. spin_lock_irqsave(&hw->lock, flags);
  204. val = __raw_readl(hw->regs + USI_CNT);
  205. if (edge)
  206. val |= RXNEG;
  207. else
  208. val &= ~RXNEG;
  209. __raw_writel(val, hw->regs + USI_CNT);
  210. spin_unlock_irqrestore(&hw->lock, flags);
  211. }
  212. static void nuc900_send_first(struct nuc900_spi *hw, unsigned int lsb)
  213. {
  214. unsigned int val;
  215. unsigned long flags;
  216. spin_lock_irqsave(&hw->lock, flags);
  217. val = __raw_readl(hw->regs + USI_CNT);
  218. if (lsb)
  219. val |= LSB;
  220. else
  221. val &= ~LSB;
  222. __raw_writel(val, hw->regs + USI_CNT);
  223. spin_unlock_irqrestore(&hw->lock, flags);
  224. }
  225. static void nuc900_set_sleep(struct nuc900_spi *hw, unsigned int sleep)
  226. {
  227. unsigned int val;
  228. unsigned long flags;
  229. spin_lock_irqsave(&hw->lock, flags);
  230. val = __raw_readl(hw->regs + USI_CNT);
  231. if (sleep)
  232. val |= (sleep << 12);
  233. else
  234. val &= ~(0x0f << 12);
  235. __raw_writel(val, hw->regs + USI_CNT);
  236. spin_unlock_irqrestore(&hw->lock, flags);
  237. }
  238. static void nuc900_enable_int(struct nuc900_spi *hw)
  239. {
  240. unsigned int val;
  241. unsigned long flags;
  242. spin_lock_irqsave(&hw->lock, flags);
  243. val = __raw_readl(hw->regs + USI_CNT);
  244. val |= ENINT;
  245. __raw_writel(val, hw->regs + USI_CNT);
  246. spin_unlock_irqrestore(&hw->lock, flags);
  247. }
  248. static void nuc900_set_divider(struct nuc900_spi *hw)
  249. {
  250. __raw_writel(hw->pdata->divider, hw->regs + USI_DIV);
  251. }
  252. static void nuc900_init_spi(struct nuc900_spi *hw)
  253. {
  254. clk_enable(hw->clk);
  255. spin_lock_init(&hw->lock);
  256. nuc900_tx_edge(hw, hw->pdata->txneg);
  257. nuc900_rx_edge(hw, hw->pdata->rxneg);
  258. nuc900_send_first(hw, hw->pdata->lsb);
  259. nuc900_set_sleep(hw, hw->pdata->sleep);
  260. nuc900_spi_setup_txbitlen(hw, hw->pdata->txbitlen);
  261. nuc900_spi_setup_txnum(hw, hw->pdata->txnum);
  262. nuc900_set_divider(hw);
  263. nuc900_enable_int(hw);
  264. }
  265. static int __devinit nuc900_spi_probe(struct platform_device *pdev)
  266. {
  267. struct nuc900_spi *hw;
  268. struct spi_master *master;
  269. int err = 0;
  270. master = spi_alloc_master(&pdev->dev, sizeof(struct nuc900_spi));
  271. if (master == NULL) {
  272. dev_err(&pdev->dev, "No memory for spi_master\n");
  273. err = -ENOMEM;
  274. goto err_nomem;
  275. }
  276. hw = spi_master_get_devdata(master);
  277. hw->master = spi_master_get(master);
  278. hw->pdata = pdev->dev.platform_data;
  279. hw->dev = &pdev->dev;
  280. if (hw->pdata == NULL) {
  281. dev_err(&pdev->dev, "No platform data supplied\n");
  282. err = -ENOENT;
  283. goto err_pdata;
  284. }
  285. platform_set_drvdata(pdev, hw);
  286. init_completion(&hw->done);
  287. master->mode_bits = SPI_MODE_0;
  288. master->num_chipselect = hw->pdata->num_cs;
  289. master->bus_num = hw->pdata->bus_num;
  290. hw->bitbang.master = hw->master;
  291. hw->bitbang.setup_transfer = nuc900_spi_setupxfer;
  292. hw->bitbang.chipselect = nuc900_spi_chipsel;
  293. hw->bitbang.txrx_bufs = nuc900_spi_txrx;
  294. hw->bitbang.master->setup = nuc900_spi_setup;
  295. hw->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  296. if (hw->res == NULL) {
  297. dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
  298. err = -ENOENT;
  299. goto err_pdata;
  300. }
  301. hw->ioarea = request_mem_region(hw->res->start,
  302. resource_size(hw->res), pdev->name);
  303. if (hw->ioarea == NULL) {
  304. dev_err(&pdev->dev, "Cannot reserve region\n");
  305. err = -ENXIO;
  306. goto err_pdata;
  307. }
  308. hw->regs = ioremap(hw->res->start, resource_size(hw->res));
  309. if (hw->regs == NULL) {
  310. dev_err(&pdev->dev, "Cannot map IO\n");
  311. err = -ENXIO;
  312. goto err_iomap;
  313. }
  314. hw->irq = platform_get_irq(pdev, 0);
  315. if (hw->irq < 0) {
  316. dev_err(&pdev->dev, "No IRQ specified\n");
  317. err = -ENOENT;
  318. goto err_irq;
  319. }
  320. err = request_irq(hw->irq, nuc900_spi_irq, 0, pdev->name, hw);
  321. if (err) {
  322. dev_err(&pdev->dev, "Cannot claim IRQ\n");
  323. goto err_irq;
  324. }
  325. hw->clk = clk_get(&pdev->dev, "spi");
  326. if (IS_ERR(hw->clk)) {
  327. dev_err(&pdev->dev, "No clock for device\n");
  328. err = PTR_ERR(hw->clk);
  329. goto err_clk;
  330. }
  331. mfp_set_groupg(&pdev->dev, NULL);
  332. nuc900_init_spi(hw);
  333. err = spi_bitbang_start(&hw->bitbang);
  334. if (err) {
  335. dev_err(&pdev->dev, "Failed to register SPI master\n");
  336. goto err_register;
  337. }
  338. return 0;
  339. err_register:
  340. clk_disable(hw->clk);
  341. clk_put(hw->clk);
  342. err_clk:
  343. free_irq(hw->irq, hw);
  344. err_irq:
  345. iounmap(hw->regs);
  346. err_iomap:
  347. release_mem_region(hw->res->start, resource_size(hw->res));
  348. kfree(hw->ioarea);
  349. err_pdata:
  350. spi_master_put(hw->master);
  351. err_nomem:
  352. return err;
  353. }
  354. static int __devexit nuc900_spi_remove(struct platform_device *dev)
  355. {
  356. struct nuc900_spi *hw = platform_get_drvdata(dev);
  357. free_irq(hw->irq, hw);
  358. platform_set_drvdata(dev, NULL);
  359. spi_bitbang_stop(&hw->bitbang);
  360. clk_disable(hw->clk);
  361. clk_put(hw->clk);
  362. iounmap(hw->regs);
  363. release_mem_region(hw->res->start, resource_size(hw->res));
  364. kfree(hw->ioarea);
  365. spi_master_put(hw->master);
  366. return 0;
  367. }
  368. static struct platform_driver nuc900_spi_driver = {
  369. .probe = nuc900_spi_probe,
  370. .remove = __devexit_p(nuc900_spi_remove),
  371. .driver = {
  372. .name = "nuc900-spi",
  373. .owner = THIS_MODULE,
  374. },
  375. };
  376. module_platform_driver(nuc900_spi_driver);
  377. MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
  378. MODULE_DESCRIPTION("nuc900 spi driver!");
  379. MODULE_LICENSE("GPL");
  380. MODULE_ALIAS("platform:nuc900-spi");