national.c 4.3 KB

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  1. /*
  2. * drivers/net/phy/national.c
  3. *
  4. * Driver for National Semiconductor PHYs
  5. *
  6. * Author: Stuart Menefy <stuart.menefy@st.com>
  7. * Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  8. *
  9. * Copyright (c) 2008 STMicroelectronics Limited
  10. *
  11. * This program is free software; you can redistribute it and/or modify it
  12. * under the terms of the GNU General Public License as published by the
  13. * Free Software Foundation; either version 2 of the License, or (at your
  14. * option) any later version.
  15. *
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/mii.h>
  20. #include <linux/ethtool.h>
  21. #include <linux/phy.h>
  22. #include <linux/netdevice.h>
  23. /* DP83865 phy identifier values */
  24. #define DP83865_PHY_ID 0x20005c7a
  25. #define DP83865_INT_STATUS 0x14
  26. #define DP83865_INT_MASK 0x15
  27. #define DP83865_INT_CLEAR 0x17
  28. #define DP83865_INT_REMOTE_FAULT 0x0008
  29. #define DP83865_INT_ANE_COMPLETED 0x0010
  30. #define DP83865_INT_LINK_CHANGE 0xe000
  31. #define DP83865_INT_MASK_DEFAULT (DP83865_INT_REMOTE_FAULT | \
  32. DP83865_INT_ANE_COMPLETED | \
  33. DP83865_INT_LINK_CHANGE)
  34. /* Advanced proprietary configuration */
  35. #define NS_EXP_MEM_CTL 0x16
  36. #define NS_EXP_MEM_DATA 0x1d
  37. #define NS_EXP_MEM_ADD 0x1e
  38. #define LED_CTRL_REG 0x13
  39. #define AN_FALLBACK_AN 0x0001
  40. #define AN_FALLBACK_CRC 0x0002
  41. #define AN_FALLBACK_IE 0x0004
  42. #define ALL_FALLBACK_ON (AN_FALLBACK_AN | AN_FALLBACK_CRC | AN_FALLBACK_IE)
  43. enum hdx_loopback {
  44. hdx_loopback_on = 0,
  45. hdx_loopback_off = 1,
  46. };
  47. static u8 ns_exp_read(struct phy_device *phydev, u16 reg)
  48. {
  49. phy_write(phydev, NS_EXP_MEM_ADD, reg);
  50. return phy_read(phydev, NS_EXP_MEM_DATA);
  51. }
  52. static void ns_exp_write(struct phy_device *phydev, u16 reg, u8 data)
  53. {
  54. phy_write(phydev, NS_EXP_MEM_ADD, reg);
  55. phy_write(phydev, NS_EXP_MEM_DATA, data);
  56. }
  57. static int ns_config_intr(struct phy_device *phydev)
  58. {
  59. int err;
  60. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  61. err = phy_write(phydev, DP83865_INT_MASK,
  62. DP83865_INT_MASK_DEFAULT);
  63. else
  64. err = phy_write(phydev, DP83865_INT_MASK, 0);
  65. return err;
  66. }
  67. static int ns_ack_interrupt(struct phy_device *phydev)
  68. {
  69. int ret = phy_read(phydev, DP83865_INT_STATUS);
  70. if (ret < 0)
  71. return ret;
  72. /* Clear the interrupt status bit by writing a “1”
  73. * to the corresponding bit in INT_CLEAR (2:0 are reserved) */
  74. ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7);
  75. return ret;
  76. }
  77. static void ns_giga_speed_fallback(struct phy_device *phydev, int mode)
  78. {
  79. int bmcr = phy_read(phydev, MII_BMCR);
  80. phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN));
  81. /* Enable 8 bit expended memory read/write (no auto increment) */
  82. phy_write(phydev, NS_EXP_MEM_CTL, 0);
  83. phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0);
  84. phy_write(phydev, NS_EXP_MEM_DATA, 0x0008);
  85. phy_write(phydev, MII_BMCR, (bmcr & ~BMCR_PDOWN));
  86. phy_write(phydev, LED_CTRL_REG, mode);
  87. }
  88. static void ns_10_base_t_hdx_loopack(struct phy_device *phydev, int disable)
  89. {
  90. if (disable)
  91. ns_exp_write(phydev, 0x1c0, ns_exp_read(phydev, 0x1c0) | 1);
  92. else
  93. ns_exp_write(phydev, 0x1c0,
  94. ns_exp_read(phydev, 0x1c0) & 0xfffe);
  95. printk(KERN_DEBUG "DP83865 PHY: 10BASE-T HDX loopback %s\n",
  96. (ns_exp_read(phydev, 0x1c0) & 0x0001) ? "off" : "on");
  97. }
  98. static int ns_config_init(struct phy_device *phydev)
  99. {
  100. ns_giga_speed_fallback(phydev, ALL_FALLBACK_ON);
  101. /* In the latest MAC or switches design, the 10 Mbps loopback
  102. is desired to be turned off. */
  103. ns_10_base_t_hdx_loopack(phydev, hdx_loopback_off);
  104. return ns_ack_interrupt(phydev);
  105. }
  106. static struct phy_driver dp83865_driver = {
  107. .phy_id = DP83865_PHY_ID,
  108. .phy_id_mask = 0xfffffff0,
  109. .name = "NatSemi DP83865",
  110. .features = PHY_GBIT_FEATURES | SUPPORTED_Pause | SUPPORTED_Asym_Pause,
  111. .flags = PHY_HAS_INTERRUPT,
  112. .config_init = ns_config_init,
  113. .config_aneg = genphy_config_aneg,
  114. .read_status = genphy_read_status,
  115. .ack_interrupt = ns_ack_interrupt,
  116. .config_intr = ns_config_intr,
  117. .driver = {.owner = THIS_MODULE,}
  118. };
  119. static int __init ns_init(void)
  120. {
  121. return phy_driver_register(&dp83865_driver);
  122. }
  123. static void __exit ns_exit(void)
  124. {
  125. phy_driver_unregister(&dp83865_driver);
  126. }
  127. MODULE_DESCRIPTION("NatSemi PHY driver");
  128. MODULE_AUTHOR("Stuart Menefy");
  129. MODULE_LICENSE("GPL");
  130. module_init(ns_init);
  131. module_exit(ns_exit);
  132. static struct mdio_device_id __maybe_unused ns_tbl[] = {
  133. { DP83865_PHY_ID, 0xfffffff0 },
  134. { }
  135. };
  136. MODULE_DEVICE_TABLE(mdio, ns_tbl);