icplus.c 6.2 KB

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  1. /*
  2. * Driver for ICPlus PHYs
  3. *
  4. * Copyright (c) 2007 Freescale Semiconductor, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. *
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/string.h>
  14. #include <linux/errno.h>
  15. #include <linux/unistd.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/init.h>
  18. #include <linux/delay.h>
  19. #include <linux/netdevice.h>
  20. #include <linux/etherdevice.h>
  21. #include <linux/skbuff.h>
  22. #include <linux/spinlock.h>
  23. #include <linux/mm.h>
  24. #include <linux/module.h>
  25. #include <linux/mii.h>
  26. #include <linux/ethtool.h>
  27. #include <linux/phy.h>
  28. #include <asm/io.h>
  29. #include <asm/irq.h>
  30. #include <asm/uaccess.h>
  31. MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IP101G/IC1001 PHY drivers");
  32. MODULE_AUTHOR("Michael Barkowski");
  33. MODULE_LICENSE("GPL");
  34. /* IP101A/G - IP1001 */
  35. #define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
  36. #define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
  37. #define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */
  38. #define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
  39. #define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */
  40. #define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
  41. static int ip175c_config_init(struct phy_device *phydev)
  42. {
  43. int err, i;
  44. static int full_reset_performed = 0;
  45. if (full_reset_performed == 0) {
  46. /* master reset */
  47. err = mdiobus_write(phydev->bus, 30, 0, 0x175c);
  48. if (err < 0)
  49. return err;
  50. /* ensure no bus delays overlap reset period */
  51. err = mdiobus_read(phydev->bus, 30, 0);
  52. /* data sheet specifies reset period is 2 msec */
  53. mdelay(2);
  54. /* enable IP175C mode */
  55. err = mdiobus_write(phydev->bus, 29, 31, 0x175c);
  56. if (err < 0)
  57. return err;
  58. /* Set MII0 speed and duplex (in PHY mode) */
  59. err = mdiobus_write(phydev->bus, 29, 22, 0x420);
  60. if (err < 0)
  61. return err;
  62. /* reset switch ports */
  63. for (i = 0; i < 5; i++) {
  64. err = mdiobus_write(phydev->bus, i,
  65. MII_BMCR, BMCR_RESET);
  66. if (err < 0)
  67. return err;
  68. }
  69. for (i = 0; i < 5; i++)
  70. err = mdiobus_read(phydev->bus, i, MII_BMCR);
  71. mdelay(2);
  72. full_reset_performed = 1;
  73. }
  74. if (phydev->addr != 4) {
  75. phydev->state = PHY_RUNNING;
  76. phydev->speed = SPEED_100;
  77. phydev->duplex = DUPLEX_FULL;
  78. phydev->link = 1;
  79. netif_carrier_on(phydev->attached_dev);
  80. }
  81. return 0;
  82. }
  83. static int ip1xx_reset(struct phy_device *phydev)
  84. {
  85. int bmcr;
  86. /* Software Reset PHY */
  87. bmcr = phy_read(phydev, MII_BMCR);
  88. if (bmcr < 0)
  89. return bmcr;
  90. bmcr |= BMCR_RESET;
  91. bmcr = phy_write(phydev, MII_BMCR, bmcr);
  92. if (bmcr < 0)
  93. return bmcr;
  94. do {
  95. bmcr = phy_read(phydev, MII_BMCR);
  96. if (bmcr < 0)
  97. return bmcr;
  98. } while (bmcr & BMCR_RESET);
  99. return 0;
  100. }
  101. static int ip1001_config_init(struct phy_device *phydev)
  102. {
  103. int c;
  104. c = ip1xx_reset(phydev);
  105. if (c < 0)
  106. return c;
  107. /* Enable Auto Power Saving mode */
  108. c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
  109. if (c < 0)
  110. return c;
  111. c |= IP1001_APS_ON;
  112. c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
  113. if (c < 0)
  114. return c;
  115. if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
  116. /* Additional delay (2ns) used to adjust RX clock phase
  117. * at RGMII interface */
  118. c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
  119. if (c < 0)
  120. return c;
  121. c |= IP1001_PHASE_SEL_MASK;
  122. c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
  123. if (c < 0)
  124. return c;
  125. }
  126. return 0;
  127. }
  128. static int ip101a_g_config_init(struct phy_device *phydev)
  129. {
  130. int c;
  131. c = ip1xx_reset(phydev);
  132. if (c < 0)
  133. return c;
  134. /* Enable Auto Power Saving mode */
  135. c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
  136. c |= IP101A_G_APS_ON;
  137. return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
  138. }
  139. static int ip175c_read_status(struct phy_device *phydev)
  140. {
  141. if (phydev->addr == 4) /* WAN port */
  142. genphy_read_status(phydev);
  143. else
  144. /* Don't need to read status for switch ports */
  145. phydev->irq = PHY_IGNORE_INTERRUPT;
  146. return 0;
  147. }
  148. static int ip175c_config_aneg(struct phy_device *phydev)
  149. {
  150. if (phydev->addr == 4) /* WAN port */
  151. genphy_config_aneg(phydev);
  152. return 0;
  153. }
  154. static int ip101a_g_ack_interrupt(struct phy_device *phydev)
  155. {
  156. int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
  157. if (err < 0)
  158. return err;
  159. return 0;
  160. }
  161. static struct phy_driver ip175c_driver = {
  162. .phy_id = 0x02430d80,
  163. .name = "ICPlus IP175C",
  164. .phy_id_mask = 0x0ffffff0,
  165. .features = PHY_BASIC_FEATURES,
  166. .config_init = &ip175c_config_init,
  167. .config_aneg = &ip175c_config_aneg,
  168. .read_status = &ip175c_read_status,
  169. .suspend = genphy_suspend,
  170. .resume = genphy_resume,
  171. .driver = { .owner = THIS_MODULE,},
  172. };
  173. static struct phy_driver ip1001_driver = {
  174. .phy_id = 0x02430d90,
  175. .name = "ICPlus IP1001",
  176. .phy_id_mask = 0x0ffffff0,
  177. .features = PHY_GBIT_FEATURES | SUPPORTED_Pause |
  178. SUPPORTED_Asym_Pause,
  179. .config_init = &ip1001_config_init,
  180. .config_aneg = &genphy_config_aneg,
  181. .read_status = &genphy_read_status,
  182. .suspend = genphy_suspend,
  183. .resume = genphy_resume,
  184. .driver = { .owner = THIS_MODULE,},
  185. };
  186. static struct phy_driver ip101a_g_driver = {
  187. .phy_id = 0x02430c54,
  188. .name = "ICPlus IP101A/G",
  189. .phy_id_mask = 0x0ffffff0,
  190. .features = PHY_BASIC_FEATURES | SUPPORTED_Pause |
  191. SUPPORTED_Asym_Pause,
  192. .flags = PHY_HAS_INTERRUPT,
  193. .ack_interrupt = ip101a_g_ack_interrupt,
  194. .config_init = &ip101a_g_config_init,
  195. .config_aneg = &genphy_config_aneg,
  196. .read_status = &genphy_read_status,
  197. .suspend = genphy_suspend,
  198. .resume = genphy_resume,
  199. .driver = { .owner = THIS_MODULE,},
  200. };
  201. static int __init icplus_init(void)
  202. {
  203. int ret = 0;
  204. ret = phy_driver_register(&ip1001_driver);
  205. if (ret < 0)
  206. return -ENODEV;
  207. ret = phy_driver_register(&ip101a_g_driver);
  208. if (ret < 0)
  209. return -ENODEV;
  210. return phy_driver_register(&ip175c_driver);
  211. }
  212. static void __exit icplus_exit(void)
  213. {
  214. phy_driver_unregister(&ip1001_driver);
  215. phy_driver_unregister(&ip101a_g_driver);
  216. phy_driver_unregister(&ip175c_driver);
  217. }
  218. module_init(icplus_init);
  219. module_exit(icplus_exit);
  220. static struct mdio_device_id __maybe_unused icplus_tbl[] = {
  221. { 0x02430d80, 0x0ffffff0 },
  222. { 0x02430d90, 0x0ffffff0 },
  223. { 0x02430c54, 0x0ffffff0 },
  224. { }
  225. };
  226. MODULE_DEVICE_TABLE(mdio, icplus_tbl);