mcdi.c 31 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2008-2011 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. #include <linux/delay.h>
  10. #include "net_driver.h"
  11. #include "nic.h"
  12. #include "io.h"
  13. #include "regs.h"
  14. #include "mcdi_pcol.h"
  15. #include "phy.h"
  16. /**************************************************************************
  17. *
  18. * Management-Controller-to-Driver Interface
  19. *
  20. **************************************************************************
  21. */
  22. #define MCDI_RPC_TIMEOUT (10 * HZ)
  23. #define MCDI_PDU(efx) \
  24. (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
  25. #define MCDI_DOORBELL(efx) \
  26. (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
  27. #define MCDI_STATUS(efx) \
  28. (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
  29. /* A reboot/assertion causes the MCDI status word to be set after the
  30. * command word is set or a REBOOT event is sent. If we notice a reboot
  31. * via these mechanisms then wait 10ms for the status word to be set. */
  32. #define MCDI_STATUS_DELAY_US 100
  33. #define MCDI_STATUS_DELAY_COUNT 100
  34. #define MCDI_STATUS_SLEEP_MS \
  35. (MCDI_STATUS_DELAY_US * MCDI_STATUS_DELAY_COUNT / 1000)
  36. #define SEQ_MASK \
  37. EFX_MASK32(EFX_WIDTH(MCDI_HEADER_SEQ))
  38. static inline struct efx_mcdi_iface *efx_mcdi(struct efx_nic *efx)
  39. {
  40. struct siena_nic_data *nic_data;
  41. EFX_BUG_ON_PARANOID(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  42. nic_data = efx->nic_data;
  43. return &nic_data->mcdi;
  44. }
  45. void efx_mcdi_init(struct efx_nic *efx)
  46. {
  47. struct efx_mcdi_iface *mcdi;
  48. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  49. return;
  50. mcdi = efx_mcdi(efx);
  51. init_waitqueue_head(&mcdi->wq);
  52. spin_lock_init(&mcdi->iface_lock);
  53. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  54. mcdi->mode = MCDI_MODE_POLL;
  55. (void) efx_mcdi_poll_reboot(efx);
  56. }
  57. static void efx_mcdi_copyin(struct efx_nic *efx, unsigned cmd,
  58. const u8 *inbuf, size_t inlen)
  59. {
  60. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  61. unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  62. unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
  63. unsigned int i;
  64. efx_dword_t hdr;
  65. u32 xflags, seqno;
  66. BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
  67. BUG_ON(inlen & 3 || inlen >= MC_SMEM_PDU_LEN);
  68. seqno = mcdi->seqno & SEQ_MASK;
  69. xflags = 0;
  70. if (mcdi->mode == MCDI_MODE_EVENTS)
  71. xflags |= MCDI_HEADER_XFLAGS_EVREQ;
  72. EFX_POPULATE_DWORD_6(hdr,
  73. MCDI_HEADER_RESPONSE, 0,
  74. MCDI_HEADER_RESYNC, 1,
  75. MCDI_HEADER_CODE, cmd,
  76. MCDI_HEADER_DATALEN, inlen,
  77. MCDI_HEADER_SEQ, seqno,
  78. MCDI_HEADER_XFLAGS, xflags);
  79. efx_writed(efx, &hdr, pdu);
  80. for (i = 0; i < inlen; i += 4)
  81. _efx_writed(efx, *((__le32 *)(inbuf + i)), pdu + 4 + i);
  82. /* Ensure the payload is written out before the header */
  83. wmb();
  84. /* ring the doorbell with a distinctive value */
  85. _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
  86. }
  87. static void efx_mcdi_copyout(struct efx_nic *efx, u8 *outbuf, size_t outlen)
  88. {
  89. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  90. unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  91. int i;
  92. BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
  93. BUG_ON(outlen & 3 || outlen >= MC_SMEM_PDU_LEN);
  94. for (i = 0; i < outlen; i += 4)
  95. *((__le32 *)(outbuf + i)) = _efx_readd(efx, pdu + 4 + i);
  96. }
  97. static int efx_mcdi_poll(struct efx_nic *efx)
  98. {
  99. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  100. unsigned long time, finish;
  101. unsigned int respseq, respcmd, error;
  102. unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  103. unsigned int rc, spins;
  104. efx_dword_t reg;
  105. /* Check for a reboot atomically with respect to efx_mcdi_copyout() */
  106. rc = -efx_mcdi_poll_reboot(efx);
  107. if (rc)
  108. goto out;
  109. /* Poll for completion. Poll quickly (once a us) for the 1st jiffy,
  110. * because generally mcdi responses are fast. After that, back off
  111. * and poll once a jiffy (approximately)
  112. */
  113. spins = TICK_USEC;
  114. finish = jiffies + MCDI_RPC_TIMEOUT;
  115. while (1) {
  116. if (spins != 0) {
  117. --spins;
  118. udelay(1);
  119. } else {
  120. schedule_timeout_uninterruptible(1);
  121. }
  122. time = jiffies;
  123. rmb();
  124. efx_readd(efx, &reg, pdu);
  125. /* All 1's indicates that shared memory is in reset (and is
  126. * not a valid header). Wait for it to come out reset before
  127. * completing the command */
  128. if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) != 0xffffffff &&
  129. EFX_DWORD_FIELD(reg, MCDI_HEADER_RESPONSE))
  130. break;
  131. if (time_after(time, finish))
  132. return -ETIMEDOUT;
  133. }
  134. mcdi->resplen = EFX_DWORD_FIELD(reg, MCDI_HEADER_DATALEN);
  135. respseq = EFX_DWORD_FIELD(reg, MCDI_HEADER_SEQ);
  136. respcmd = EFX_DWORD_FIELD(reg, MCDI_HEADER_CODE);
  137. error = EFX_DWORD_FIELD(reg, MCDI_HEADER_ERROR);
  138. if (error && mcdi->resplen == 0) {
  139. netif_err(efx, hw, efx->net_dev, "MC rebooted\n");
  140. rc = EIO;
  141. } else if ((respseq ^ mcdi->seqno) & SEQ_MASK) {
  142. netif_err(efx, hw, efx->net_dev,
  143. "MC response mismatch tx seq 0x%x rx seq 0x%x\n",
  144. respseq, mcdi->seqno);
  145. rc = EIO;
  146. } else if (error) {
  147. efx_readd(efx, &reg, pdu + 4);
  148. switch (EFX_DWORD_FIELD(reg, EFX_DWORD_0)) {
  149. #define TRANSLATE_ERROR(name) \
  150. case MC_CMD_ERR_ ## name: \
  151. rc = name; \
  152. break
  153. TRANSLATE_ERROR(ENOENT);
  154. TRANSLATE_ERROR(EINTR);
  155. TRANSLATE_ERROR(EACCES);
  156. TRANSLATE_ERROR(EBUSY);
  157. TRANSLATE_ERROR(EINVAL);
  158. TRANSLATE_ERROR(EDEADLK);
  159. TRANSLATE_ERROR(ENOSYS);
  160. TRANSLATE_ERROR(ETIME);
  161. #undef TRANSLATE_ERROR
  162. default:
  163. rc = EIO;
  164. break;
  165. }
  166. } else
  167. rc = 0;
  168. out:
  169. mcdi->resprc = rc;
  170. if (rc)
  171. mcdi->resplen = 0;
  172. /* Return rc=0 like wait_event_timeout() */
  173. return 0;
  174. }
  175. /* Test and clear MC-rebooted flag for this port/function */
  176. int efx_mcdi_poll_reboot(struct efx_nic *efx)
  177. {
  178. unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
  179. efx_dword_t reg;
  180. uint32_t value;
  181. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  182. return false;
  183. efx_readd(efx, &reg, addr);
  184. value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
  185. if (value == 0)
  186. return 0;
  187. EFX_ZERO_DWORD(reg);
  188. efx_writed(efx, &reg, addr);
  189. if (value == MC_STATUS_DWORD_ASSERT)
  190. return -EINTR;
  191. else
  192. return -EIO;
  193. }
  194. static void efx_mcdi_acquire(struct efx_mcdi_iface *mcdi)
  195. {
  196. /* Wait until the interface becomes QUIESCENT and we win the race
  197. * to mark it RUNNING. */
  198. wait_event(mcdi->wq,
  199. atomic_cmpxchg(&mcdi->state,
  200. MCDI_STATE_QUIESCENT,
  201. MCDI_STATE_RUNNING)
  202. == MCDI_STATE_QUIESCENT);
  203. }
  204. static int efx_mcdi_await_completion(struct efx_nic *efx)
  205. {
  206. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  207. if (wait_event_timeout(
  208. mcdi->wq,
  209. atomic_read(&mcdi->state) == MCDI_STATE_COMPLETED,
  210. MCDI_RPC_TIMEOUT) == 0)
  211. return -ETIMEDOUT;
  212. /* Check if efx_mcdi_set_mode() switched us back to polled completions.
  213. * In which case, poll for completions directly. If efx_mcdi_ev_cpl()
  214. * completed the request first, then we'll just end up completing the
  215. * request again, which is safe.
  216. *
  217. * We need an smp_rmb() to synchronise with efx_mcdi_mode_poll(), which
  218. * wait_event_timeout() implicitly provides.
  219. */
  220. if (mcdi->mode == MCDI_MODE_POLL)
  221. return efx_mcdi_poll(efx);
  222. return 0;
  223. }
  224. static bool efx_mcdi_complete(struct efx_mcdi_iface *mcdi)
  225. {
  226. /* If the interface is RUNNING, then move to COMPLETED and wake any
  227. * waiters. If the interface isn't in RUNNING then we've received a
  228. * duplicate completion after we've already transitioned back to
  229. * QUIESCENT. [A subsequent invocation would increment seqno, so would
  230. * have failed the seqno check].
  231. */
  232. if (atomic_cmpxchg(&mcdi->state,
  233. MCDI_STATE_RUNNING,
  234. MCDI_STATE_COMPLETED) == MCDI_STATE_RUNNING) {
  235. wake_up(&mcdi->wq);
  236. return true;
  237. }
  238. return false;
  239. }
  240. static void efx_mcdi_release(struct efx_mcdi_iface *mcdi)
  241. {
  242. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  243. wake_up(&mcdi->wq);
  244. }
  245. static void efx_mcdi_ev_cpl(struct efx_nic *efx, unsigned int seqno,
  246. unsigned int datalen, unsigned int errno)
  247. {
  248. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  249. bool wake = false;
  250. spin_lock(&mcdi->iface_lock);
  251. if ((seqno ^ mcdi->seqno) & SEQ_MASK) {
  252. if (mcdi->credits)
  253. /* The request has been cancelled */
  254. --mcdi->credits;
  255. else
  256. netif_err(efx, hw, efx->net_dev,
  257. "MC response mismatch tx seq 0x%x rx "
  258. "seq 0x%x\n", seqno, mcdi->seqno);
  259. } else {
  260. mcdi->resprc = errno;
  261. mcdi->resplen = datalen;
  262. wake = true;
  263. }
  264. spin_unlock(&mcdi->iface_lock);
  265. if (wake)
  266. efx_mcdi_complete(mcdi);
  267. }
  268. /* Issue the given command by writing the data into the shared memory PDU,
  269. * ring the doorbell and wait for completion. Copyout the result. */
  270. int efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd,
  271. const u8 *inbuf, size_t inlen, u8 *outbuf, size_t outlen,
  272. size_t *outlen_actual)
  273. {
  274. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  275. int rc;
  276. BUG_ON(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  277. efx_mcdi_acquire(mcdi);
  278. /* Serialise with efx_mcdi_ev_cpl() and efx_mcdi_ev_death() */
  279. spin_lock_bh(&mcdi->iface_lock);
  280. ++mcdi->seqno;
  281. spin_unlock_bh(&mcdi->iface_lock);
  282. efx_mcdi_copyin(efx, cmd, inbuf, inlen);
  283. if (mcdi->mode == MCDI_MODE_POLL)
  284. rc = efx_mcdi_poll(efx);
  285. else
  286. rc = efx_mcdi_await_completion(efx);
  287. if (rc != 0) {
  288. /* Close the race with efx_mcdi_ev_cpl() executing just too late
  289. * and completing a request we've just cancelled, by ensuring
  290. * that the seqno check therein fails.
  291. */
  292. spin_lock_bh(&mcdi->iface_lock);
  293. ++mcdi->seqno;
  294. ++mcdi->credits;
  295. spin_unlock_bh(&mcdi->iface_lock);
  296. netif_err(efx, hw, efx->net_dev,
  297. "MC command 0x%x inlen %d mode %d timed out\n",
  298. cmd, (int)inlen, mcdi->mode);
  299. } else {
  300. size_t resplen;
  301. /* At the very least we need a memory barrier here to ensure
  302. * we pick up changes from efx_mcdi_ev_cpl(). Protect against
  303. * a spurious efx_mcdi_ev_cpl() running concurrently by
  304. * acquiring the iface_lock. */
  305. spin_lock_bh(&mcdi->iface_lock);
  306. rc = -mcdi->resprc;
  307. resplen = mcdi->resplen;
  308. spin_unlock_bh(&mcdi->iface_lock);
  309. if (rc == 0) {
  310. efx_mcdi_copyout(efx, outbuf,
  311. min(outlen, mcdi->resplen + 3) & ~0x3);
  312. if (outlen_actual != NULL)
  313. *outlen_actual = resplen;
  314. } else if (cmd == MC_CMD_REBOOT && rc == -EIO)
  315. ; /* Don't reset if MC_CMD_REBOOT returns EIO */
  316. else if (rc == -EIO || rc == -EINTR) {
  317. netif_err(efx, hw, efx->net_dev, "MC fatal error %d\n",
  318. -rc);
  319. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  320. } else
  321. netif_dbg(efx, hw, efx->net_dev,
  322. "MC command 0x%x inlen %d failed rc=%d\n",
  323. cmd, (int)inlen, -rc);
  324. if (rc == -EIO || rc == -EINTR) {
  325. msleep(MCDI_STATUS_SLEEP_MS);
  326. efx_mcdi_poll_reboot(efx);
  327. }
  328. }
  329. efx_mcdi_release(mcdi);
  330. return rc;
  331. }
  332. void efx_mcdi_mode_poll(struct efx_nic *efx)
  333. {
  334. struct efx_mcdi_iface *mcdi;
  335. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  336. return;
  337. mcdi = efx_mcdi(efx);
  338. if (mcdi->mode == MCDI_MODE_POLL)
  339. return;
  340. /* We can switch from event completion to polled completion, because
  341. * mcdi requests are always completed in shared memory. We do this by
  342. * switching the mode to POLL'd then completing the request.
  343. * efx_mcdi_await_completion() will then call efx_mcdi_poll().
  344. *
  345. * We need an smp_wmb() to synchronise with efx_mcdi_await_completion(),
  346. * which efx_mcdi_complete() provides for us.
  347. */
  348. mcdi->mode = MCDI_MODE_POLL;
  349. efx_mcdi_complete(mcdi);
  350. }
  351. void efx_mcdi_mode_event(struct efx_nic *efx)
  352. {
  353. struct efx_mcdi_iface *mcdi;
  354. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  355. return;
  356. mcdi = efx_mcdi(efx);
  357. if (mcdi->mode == MCDI_MODE_EVENTS)
  358. return;
  359. /* We can't switch from polled to event completion in the middle of a
  360. * request, because the completion method is specified in the request.
  361. * So acquire the interface to serialise the requestors. We don't need
  362. * to acquire the iface_lock to change the mode here, but we do need a
  363. * write memory barrier ensure that efx_mcdi_rpc() sees it, which
  364. * efx_mcdi_acquire() provides.
  365. */
  366. efx_mcdi_acquire(mcdi);
  367. mcdi->mode = MCDI_MODE_EVENTS;
  368. efx_mcdi_release(mcdi);
  369. }
  370. static void efx_mcdi_ev_death(struct efx_nic *efx, int rc)
  371. {
  372. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  373. /* If there is an outstanding MCDI request, it has been terminated
  374. * either by a BADASSERT or REBOOT event. If the mcdi interface is
  375. * in polled mode, then do nothing because the MC reboot handler will
  376. * set the header correctly. However, if the mcdi interface is waiting
  377. * for a CMDDONE event it won't receive it [and since all MCDI events
  378. * are sent to the same queue, we can't be racing with
  379. * efx_mcdi_ev_cpl()]
  380. *
  381. * There's a race here with efx_mcdi_rpc(), because we might receive
  382. * a REBOOT event *before* the request has been copied out. In polled
  383. * mode (during startup) this is irrelevant, because efx_mcdi_complete()
  384. * is ignored. In event mode, this condition is just an edge-case of
  385. * receiving a REBOOT event after posting the MCDI request. Did the mc
  386. * reboot before or after the copyout? The best we can do always is
  387. * just return failure.
  388. */
  389. spin_lock(&mcdi->iface_lock);
  390. if (efx_mcdi_complete(mcdi)) {
  391. if (mcdi->mode == MCDI_MODE_EVENTS) {
  392. mcdi->resprc = rc;
  393. mcdi->resplen = 0;
  394. ++mcdi->credits;
  395. }
  396. } else {
  397. int count;
  398. /* Nobody was waiting for an MCDI request, so trigger a reset */
  399. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  400. /* Consume the status word since efx_mcdi_rpc_finish() won't */
  401. for (count = 0; count < MCDI_STATUS_DELAY_COUNT; ++count) {
  402. if (efx_mcdi_poll_reboot(efx))
  403. break;
  404. udelay(MCDI_STATUS_DELAY_US);
  405. }
  406. }
  407. spin_unlock(&mcdi->iface_lock);
  408. }
  409. static unsigned int efx_mcdi_event_link_speed[] = {
  410. [MCDI_EVENT_LINKCHANGE_SPEED_100M] = 100,
  411. [MCDI_EVENT_LINKCHANGE_SPEED_1G] = 1000,
  412. [MCDI_EVENT_LINKCHANGE_SPEED_10G] = 10000,
  413. };
  414. static void efx_mcdi_process_link_change(struct efx_nic *efx, efx_qword_t *ev)
  415. {
  416. u32 flags, fcntl, speed, lpa;
  417. speed = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_SPEED);
  418. EFX_BUG_ON_PARANOID(speed >= ARRAY_SIZE(efx_mcdi_event_link_speed));
  419. speed = efx_mcdi_event_link_speed[speed];
  420. flags = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LINK_FLAGS);
  421. fcntl = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_FCNTL);
  422. lpa = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LP_CAP);
  423. /* efx->link_state is only modified by efx_mcdi_phy_get_link(),
  424. * which is only run after flushing the event queues. Therefore, it
  425. * is safe to modify the link state outside of the mac_lock here.
  426. */
  427. efx_mcdi_phy_decode_link(efx, &efx->link_state, speed, flags, fcntl);
  428. efx_mcdi_phy_check_fcntl(efx, lpa);
  429. efx_link_status_changed(efx);
  430. }
  431. /* Called from falcon_process_eventq for MCDI events */
  432. void efx_mcdi_process_event(struct efx_channel *channel,
  433. efx_qword_t *event)
  434. {
  435. struct efx_nic *efx = channel->efx;
  436. int code = EFX_QWORD_FIELD(*event, MCDI_EVENT_CODE);
  437. u32 data = EFX_QWORD_FIELD(*event, MCDI_EVENT_DATA);
  438. switch (code) {
  439. case MCDI_EVENT_CODE_BADSSERT:
  440. netif_err(efx, hw, efx->net_dev,
  441. "MC watchdog or assertion failure at 0x%x\n", data);
  442. efx_mcdi_ev_death(efx, EINTR);
  443. break;
  444. case MCDI_EVENT_CODE_PMNOTICE:
  445. netif_info(efx, wol, efx->net_dev, "MCDI PM event.\n");
  446. break;
  447. case MCDI_EVENT_CODE_CMDDONE:
  448. efx_mcdi_ev_cpl(efx,
  449. MCDI_EVENT_FIELD(*event, CMDDONE_SEQ),
  450. MCDI_EVENT_FIELD(*event, CMDDONE_DATALEN),
  451. MCDI_EVENT_FIELD(*event, CMDDONE_ERRNO));
  452. break;
  453. case MCDI_EVENT_CODE_LINKCHANGE:
  454. efx_mcdi_process_link_change(efx, event);
  455. break;
  456. case MCDI_EVENT_CODE_SENSOREVT:
  457. efx_mcdi_sensor_event(efx, event);
  458. break;
  459. case MCDI_EVENT_CODE_SCHEDERR:
  460. netif_info(efx, hw, efx->net_dev,
  461. "MC Scheduler error address=0x%x\n", data);
  462. break;
  463. case MCDI_EVENT_CODE_REBOOT:
  464. netif_info(efx, hw, efx->net_dev, "MC Reboot\n");
  465. efx_mcdi_ev_death(efx, EIO);
  466. break;
  467. case MCDI_EVENT_CODE_MAC_STATS_DMA:
  468. /* MAC stats are gather lazily. We can ignore this. */
  469. break;
  470. case MCDI_EVENT_CODE_FLR:
  471. efx_sriov_flr(efx, MCDI_EVENT_FIELD(*event, FLR_VF));
  472. break;
  473. default:
  474. netif_err(efx, hw, efx->net_dev, "Unknown MCDI event 0x%x\n",
  475. code);
  476. }
  477. }
  478. /**************************************************************************
  479. *
  480. * Specific request functions
  481. *
  482. **************************************************************************
  483. */
  484. void efx_mcdi_print_fwver(struct efx_nic *efx, char *buf, size_t len)
  485. {
  486. u8 outbuf[ALIGN(MC_CMD_GET_VERSION_OUT_LEN, 4)];
  487. size_t outlength;
  488. const __le16 *ver_words;
  489. int rc;
  490. BUILD_BUG_ON(MC_CMD_GET_VERSION_IN_LEN != 0);
  491. rc = efx_mcdi_rpc(efx, MC_CMD_GET_VERSION, NULL, 0,
  492. outbuf, sizeof(outbuf), &outlength);
  493. if (rc)
  494. goto fail;
  495. if (outlength < MC_CMD_GET_VERSION_OUT_LEN) {
  496. rc = -EIO;
  497. goto fail;
  498. }
  499. ver_words = (__le16 *)MCDI_PTR(outbuf, GET_VERSION_OUT_VERSION);
  500. snprintf(buf, len, "%u.%u.%u.%u",
  501. le16_to_cpu(ver_words[0]), le16_to_cpu(ver_words[1]),
  502. le16_to_cpu(ver_words[2]), le16_to_cpu(ver_words[3]));
  503. return;
  504. fail:
  505. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  506. buf[0] = 0;
  507. }
  508. int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating,
  509. bool *was_attached)
  510. {
  511. u8 inbuf[MC_CMD_DRV_ATTACH_IN_LEN];
  512. u8 outbuf[MC_CMD_DRV_ATTACH_OUT_LEN];
  513. size_t outlen;
  514. int rc;
  515. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_NEW_STATE,
  516. driver_operating ? 1 : 0);
  517. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_UPDATE, 1);
  518. rc = efx_mcdi_rpc(efx, MC_CMD_DRV_ATTACH, inbuf, sizeof(inbuf),
  519. outbuf, sizeof(outbuf), &outlen);
  520. if (rc)
  521. goto fail;
  522. if (outlen < MC_CMD_DRV_ATTACH_OUT_LEN) {
  523. rc = -EIO;
  524. goto fail;
  525. }
  526. if (was_attached != NULL)
  527. *was_attached = MCDI_DWORD(outbuf, DRV_ATTACH_OUT_OLD_STATE);
  528. return 0;
  529. fail:
  530. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  531. return rc;
  532. }
  533. int efx_mcdi_get_board_cfg(struct efx_nic *efx, u8 *mac_address,
  534. u16 *fw_subtype_list, u32 *capabilities)
  535. {
  536. uint8_t outbuf[MC_CMD_GET_BOARD_CFG_OUT_LENMAX];
  537. size_t outlen, offset, i;
  538. int port_num = efx_port_num(efx);
  539. int rc;
  540. BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_IN_LEN != 0);
  541. rc = efx_mcdi_rpc(efx, MC_CMD_GET_BOARD_CFG, NULL, 0,
  542. outbuf, sizeof(outbuf), &outlen);
  543. if (rc)
  544. goto fail;
  545. if (outlen < MC_CMD_GET_BOARD_CFG_OUT_LENMIN) {
  546. rc = -EIO;
  547. goto fail;
  548. }
  549. offset = (port_num)
  550. ? MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST
  551. : MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST;
  552. if (mac_address)
  553. memcpy(mac_address, outbuf + offset, ETH_ALEN);
  554. if (fw_subtype_list) {
  555. offset = MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST;
  556. for (i = 0;
  557. i < MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM;
  558. i++) {
  559. fw_subtype_list[i] =
  560. le16_to_cpup((__le16 *)(outbuf + offset));
  561. offset += 2;
  562. }
  563. }
  564. if (capabilities) {
  565. if (port_num)
  566. *capabilities = MCDI_DWORD(outbuf,
  567. GET_BOARD_CFG_OUT_CAPABILITIES_PORT1);
  568. else
  569. *capabilities = MCDI_DWORD(outbuf,
  570. GET_BOARD_CFG_OUT_CAPABILITIES_PORT0);
  571. }
  572. return 0;
  573. fail:
  574. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d len=%d\n",
  575. __func__, rc, (int)outlen);
  576. return rc;
  577. }
  578. int efx_mcdi_log_ctrl(struct efx_nic *efx, bool evq, bool uart, u32 dest_evq)
  579. {
  580. u8 inbuf[MC_CMD_LOG_CTRL_IN_LEN];
  581. u32 dest = 0;
  582. int rc;
  583. if (uart)
  584. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_UART;
  585. if (evq)
  586. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ;
  587. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST, dest);
  588. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST_EVQ, dest_evq);
  589. BUILD_BUG_ON(MC_CMD_LOG_CTRL_OUT_LEN != 0);
  590. rc = efx_mcdi_rpc(efx, MC_CMD_LOG_CTRL, inbuf, sizeof(inbuf),
  591. NULL, 0, NULL);
  592. if (rc)
  593. goto fail;
  594. return 0;
  595. fail:
  596. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  597. return rc;
  598. }
  599. int efx_mcdi_nvram_types(struct efx_nic *efx, u32 *nvram_types_out)
  600. {
  601. u8 outbuf[MC_CMD_NVRAM_TYPES_OUT_LEN];
  602. size_t outlen;
  603. int rc;
  604. BUILD_BUG_ON(MC_CMD_NVRAM_TYPES_IN_LEN != 0);
  605. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TYPES, NULL, 0,
  606. outbuf, sizeof(outbuf), &outlen);
  607. if (rc)
  608. goto fail;
  609. if (outlen < MC_CMD_NVRAM_TYPES_OUT_LEN) {
  610. rc = -EIO;
  611. goto fail;
  612. }
  613. *nvram_types_out = MCDI_DWORD(outbuf, NVRAM_TYPES_OUT_TYPES);
  614. return 0;
  615. fail:
  616. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  617. __func__, rc);
  618. return rc;
  619. }
  620. int efx_mcdi_nvram_info(struct efx_nic *efx, unsigned int type,
  621. size_t *size_out, size_t *erase_size_out,
  622. bool *protected_out)
  623. {
  624. u8 inbuf[MC_CMD_NVRAM_INFO_IN_LEN];
  625. u8 outbuf[MC_CMD_NVRAM_INFO_OUT_LEN];
  626. size_t outlen;
  627. int rc;
  628. MCDI_SET_DWORD(inbuf, NVRAM_INFO_IN_TYPE, type);
  629. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_INFO, inbuf, sizeof(inbuf),
  630. outbuf, sizeof(outbuf), &outlen);
  631. if (rc)
  632. goto fail;
  633. if (outlen < MC_CMD_NVRAM_INFO_OUT_LEN) {
  634. rc = -EIO;
  635. goto fail;
  636. }
  637. *size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_SIZE);
  638. *erase_size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_ERASESIZE);
  639. *protected_out = !!(MCDI_DWORD(outbuf, NVRAM_INFO_OUT_FLAGS) &
  640. (1 << MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN));
  641. return 0;
  642. fail:
  643. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  644. return rc;
  645. }
  646. int efx_mcdi_nvram_update_start(struct efx_nic *efx, unsigned int type)
  647. {
  648. u8 inbuf[MC_CMD_NVRAM_UPDATE_START_IN_LEN];
  649. int rc;
  650. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_START_IN_TYPE, type);
  651. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_START_OUT_LEN != 0);
  652. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_START, inbuf, sizeof(inbuf),
  653. NULL, 0, NULL);
  654. if (rc)
  655. goto fail;
  656. return 0;
  657. fail:
  658. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  659. return rc;
  660. }
  661. int efx_mcdi_nvram_read(struct efx_nic *efx, unsigned int type,
  662. loff_t offset, u8 *buffer, size_t length)
  663. {
  664. u8 inbuf[MC_CMD_NVRAM_READ_IN_LEN];
  665. u8 outbuf[MC_CMD_NVRAM_READ_OUT_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
  666. size_t outlen;
  667. int rc;
  668. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_TYPE, type);
  669. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_OFFSET, offset);
  670. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_LENGTH, length);
  671. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_READ, inbuf, sizeof(inbuf),
  672. outbuf, sizeof(outbuf), &outlen);
  673. if (rc)
  674. goto fail;
  675. memcpy(buffer, MCDI_PTR(outbuf, NVRAM_READ_OUT_READ_BUFFER), length);
  676. return 0;
  677. fail:
  678. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  679. return rc;
  680. }
  681. int efx_mcdi_nvram_write(struct efx_nic *efx, unsigned int type,
  682. loff_t offset, const u8 *buffer, size_t length)
  683. {
  684. u8 inbuf[MC_CMD_NVRAM_WRITE_IN_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
  685. int rc;
  686. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_TYPE, type);
  687. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_OFFSET, offset);
  688. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_LENGTH, length);
  689. memcpy(MCDI_PTR(inbuf, NVRAM_WRITE_IN_WRITE_BUFFER), buffer, length);
  690. BUILD_BUG_ON(MC_CMD_NVRAM_WRITE_OUT_LEN != 0);
  691. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_WRITE, inbuf,
  692. ALIGN(MC_CMD_NVRAM_WRITE_IN_LEN(length), 4),
  693. NULL, 0, NULL);
  694. if (rc)
  695. goto fail;
  696. return 0;
  697. fail:
  698. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  699. return rc;
  700. }
  701. int efx_mcdi_nvram_erase(struct efx_nic *efx, unsigned int type,
  702. loff_t offset, size_t length)
  703. {
  704. u8 inbuf[MC_CMD_NVRAM_ERASE_IN_LEN];
  705. int rc;
  706. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_TYPE, type);
  707. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_OFFSET, offset);
  708. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_LENGTH, length);
  709. BUILD_BUG_ON(MC_CMD_NVRAM_ERASE_OUT_LEN != 0);
  710. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_ERASE, inbuf, sizeof(inbuf),
  711. NULL, 0, NULL);
  712. if (rc)
  713. goto fail;
  714. return 0;
  715. fail:
  716. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  717. return rc;
  718. }
  719. int efx_mcdi_nvram_update_finish(struct efx_nic *efx, unsigned int type)
  720. {
  721. u8 inbuf[MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN];
  722. int rc;
  723. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_FINISH_IN_TYPE, type);
  724. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN != 0);
  725. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_FINISH, inbuf, sizeof(inbuf),
  726. NULL, 0, NULL);
  727. if (rc)
  728. goto fail;
  729. return 0;
  730. fail:
  731. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  732. return rc;
  733. }
  734. static int efx_mcdi_nvram_test(struct efx_nic *efx, unsigned int type)
  735. {
  736. u8 inbuf[MC_CMD_NVRAM_TEST_IN_LEN];
  737. u8 outbuf[MC_CMD_NVRAM_TEST_OUT_LEN];
  738. int rc;
  739. MCDI_SET_DWORD(inbuf, NVRAM_TEST_IN_TYPE, type);
  740. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TEST, inbuf, sizeof(inbuf),
  741. outbuf, sizeof(outbuf), NULL);
  742. if (rc)
  743. return rc;
  744. switch (MCDI_DWORD(outbuf, NVRAM_TEST_OUT_RESULT)) {
  745. case MC_CMD_NVRAM_TEST_PASS:
  746. case MC_CMD_NVRAM_TEST_NOTSUPP:
  747. return 0;
  748. default:
  749. return -EIO;
  750. }
  751. }
  752. int efx_mcdi_nvram_test_all(struct efx_nic *efx)
  753. {
  754. u32 nvram_types;
  755. unsigned int type;
  756. int rc;
  757. rc = efx_mcdi_nvram_types(efx, &nvram_types);
  758. if (rc)
  759. goto fail1;
  760. type = 0;
  761. while (nvram_types != 0) {
  762. if (nvram_types & 1) {
  763. rc = efx_mcdi_nvram_test(efx, type);
  764. if (rc)
  765. goto fail2;
  766. }
  767. type++;
  768. nvram_types >>= 1;
  769. }
  770. return 0;
  771. fail2:
  772. netif_err(efx, hw, efx->net_dev, "%s: failed type=%u\n",
  773. __func__, type);
  774. fail1:
  775. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  776. return rc;
  777. }
  778. static int efx_mcdi_read_assertion(struct efx_nic *efx)
  779. {
  780. u8 inbuf[MC_CMD_GET_ASSERTS_IN_LEN];
  781. u8 outbuf[MC_CMD_GET_ASSERTS_OUT_LEN];
  782. unsigned int flags, index, ofst;
  783. const char *reason;
  784. size_t outlen;
  785. int retry;
  786. int rc;
  787. /* Attempt to read any stored assertion state before we reboot
  788. * the mcfw out of the assertion handler. Retry twice, once
  789. * because a boot-time assertion might cause this command to fail
  790. * with EINTR. And once again because GET_ASSERTS can race with
  791. * MC_CMD_REBOOT running on the other port. */
  792. retry = 2;
  793. do {
  794. MCDI_SET_DWORD(inbuf, GET_ASSERTS_IN_CLEAR, 1);
  795. rc = efx_mcdi_rpc(efx, MC_CMD_GET_ASSERTS,
  796. inbuf, MC_CMD_GET_ASSERTS_IN_LEN,
  797. outbuf, sizeof(outbuf), &outlen);
  798. } while ((rc == -EINTR || rc == -EIO) && retry-- > 0);
  799. if (rc)
  800. return rc;
  801. if (outlen < MC_CMD_GET_ASSERTS_OUT_LEN)
  802. return -EIO;
  803. /* Print out any recorded assertion state */
  804. flags = MCDI_DWORD(outbuf, GET_ASSERTS_OUT_GLOBAL_FLAGS);
  805. if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS)
  806. return 0;
  807. reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL)
  808. ? "system-level assertion"
  809. : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL)
  810. ? "thread-level assertion"
  811. : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED)
  812. ? "watchdog reset"
  813. : "unknown assertion";
  814. netif_err(efx, hw, efx->net_dev,
  815. "MCPU %s at PC = 0x%.8x in thread 0x%.8x\n", reason,
  816. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_SAVED_PC_OFFS),
  817. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_THREAD_OFFS));
  818. /* Print out the registers */
  819. ofst = MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST;
  820. for (index = 1; index < 32; index++) {
  821. netif_err(efx, hw, efx->net_dev, "R%.2d (?): 0x%.8x\n", index,
  822. MCDI_DWORD2(outbuf, ofst));
  823. ofst += sizeof(efx_dword_t);
  824. }
  825. return 0;
  826. }
  827. static void efx_mcdi_exit_assertion(struct efx_nic *efx)
  828. {
  829. u8 inbuf[MC_CMD_REBOOT_IN_LEN];
  830. /* Atomically reboot the mcfw out of the assertion handler */
  831. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  832. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS,
  833. MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION);
  834. efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, MC_CMD_REBOOT_IN_LEN,
  835. NULL, 0, NULL);
  836. }
  837. int efx_mcdi_handle_assertion(struct efx_nic *efx)
  838. {
  839. int rc;
  840. rc = efx_mcdi_read_assertion(efx);
  841. if (rc)
  842. return rc;
  843. efx_mcdi_exit_assertion(efx);
  844. return 0;
  845. }
  846. void efx_mcdi_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
  847. {
  848. u8 inbuf[MC_CMD_SET_ID_LED_IN_LEN];
  849. int rc;
  850. BUILD_BUG_ON(EFX_LED_OFF != MC_CMD_LED_OFF);
  851. BUILD_BUG_ON(EFX_LED_ON != MC_CMD_LED_ON);
  852. BUILD_BUG_ON(EFX_LED_DEFAULT != MC_CMD_LED_DEFAULT);
  853. BUILD_BUG_ON(MC_CMD_SET_ID_LED_OUT_LEN != 0);
  854. MCDI_SET_DWORD(inbuf, SET_ID_LED_IN_STATE, mode);
  855. rc = efx_mcdi_rpc(efx, MC_CMD_SET_ID_LED, inbuf, sizeof(inbuf),
  856. NULL, 0, NULL);
  857. if (rc)
  858. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  859. __func__, rc);
  860. }
  861. int efx_mcdi_reset_port(struct efx_nic *efx)
  862. {
  863. int rc = efx_mcdi_rpc(efx, MC_CMD_ENTITY_RESET, NULL, 0, NULL, 0, NULL);
  864. if (rc)
  865. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  866. __func__, rc);
  867. return rc;
  868. }
  869. int efx_mcdi_reset_mc(struct efx_nic *efx)
  870. {
  871. u8 inbuf[MC_CMD_REBOOT_IN_LEN];
  872. int rc;
  873. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  874. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, 0);
  875. rc = efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, sizeof(inbuf),
  876. NULL, 0, NULL);
  877. /* White is black, and up is down */
  878. if (rc == -EIO)
  879. return 0;
  880. if (rc == 0)
  881. rc = -EIO;
  882. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  883. return rc;
  884. }
  885. static int efx_mcdi_wol_filter_set(struct efx_nic *efx, u32 type,
  886. const u8 *mac, int *id_out)
  887. {
  888. u8 inbuf[MC_CMD_WOL_FILTER_SET_IN_LEN];
  889. u8 outbuf[MC_CMD_WOL_FILTER_SET_OUT_LEN];
  890. size_t outlen;
  891. int rc;
  892. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_WOL_TYPE, type);
  893. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_FILTER_MODE,
  894. MC_CMD_FILTER_MODE_SIMPLE);
  895. memcpy(MCDI_PTR(inbuf, WOL_FILTER_SET_IN_MAGIC_MAC), mac, ETH_ALEN);
  896. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_SET, inbuf, sizeof(inbuf),
  897. outbuf, sizeof(outbuf), &outlen);
  898. if (rc)
  899. goto fail;
  900. if (outlen < MC_CMD_WOL_FILTER_SET_OUT_LEN) {
  901. rc = -EIO;
  902. goto fail;
  903. }
  904. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_SET_OUT_FILTER_ID);
  905. return 0;
  906. fail:
  907. *id_out = -1;
  908. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  909. return rc;
  910. }
  911. int
  912. efx_mcdi_wol_filter_set_magic(struct efx_nic *efx, const u8 *mac, int *id_out)
  913. {
  914. return efx_mcdi_wol_filter_set(efx, MC_CMD_WOL_TYPE_MAGIC, mac, id_out);
  915. }
  916. int efx_mcdi_wol_filter_get_magic(struct efx_nic *efx, int *id_out)
  917. {
  918. u8 outbuf[MC_CMD_WOL_FILTER_GET_OUT_LEN];
  919. size_t outlen;
  920. int rc;
  921. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_GET, NULL, 0,
  922. outbuf, sizeof(outbuf), &outlen);
  923. if (rc)
  924. goto fail;
  925. if (outlen < MC_CMD_WOL_FILTER_GET_OUT_LEN) {
  926. rc = -EIO;
  927. goto fail;
  928. }
  929. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_GET_OUT_FILTER_ID);
  930. return 0;
  931. fail:
  932. *id_out = -1;
  933. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  934. return rc;
  935. }
  936. int efx_mcdi_wol_filter_remove(struct efx_nic *efx, int id)
  937. {
  938. u8 inbuf[MC_CMD_WOL_FILTER_REMOVE_IN_LEN];
  939. int rc;
  940. MCDI_SET_DWORD(inbuf, WOL_FILTER_REMOVE_IN_FILTER_ID, (u32)id);
  941. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_REMOVE, inbuf, sizeof(inbuf),
  942. NULL, 0, NULL);
  943. if (rc)
  944. goto fail;
  945. return 0;
  946. fail:
  947. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  948. return rc;
  949. }
  950. int efx_mcdi_flush_rxqs(struct efx_nic *efx)
  951. {
  952. struct efx_channel *channel;
  953. struct efx_rx_queue *rx_queue;
  954. __le32 *qid;
  955. int rc, count;
  956. BUILD_BUG_ON(EFX_MAX_CHANNELS >
  957. MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM);
  958. qid = kmalloc(EFX_MAX_CHANNELS * sizeof(*qid), GFP_KERNEL);
  959. if (qid == NULL)
  960. return -ENOMEM;
  961. count = 0;
  962. efx_for_each_channel(channel, efx) {
  963. efx_for_each_channel_rx_queue(rx_queue, channel) {
  964. if (rx_queue->flush_pending) {
  965. rx_queue->flush_pending = false;
  966. atomic_dec(&efx->rxq_flush_pending);
  967. qid[count++] = cpu_to_le32(
  968. efx_rx_queue_index(rx_queue));
  969. }
  970. }
  971. }
  972. rc = efx_mcdi_rpc(efx, MC_CMD_FLUSH_RX_QUEUES, (u8 *)qid,
  973. count * sizeof(*qid), NULL, 0, NULL);
  974. WARN_ON(rc > 0);
  975. kfree(qid);
  976. return rc;
  977. }
  978. int efx_mcdi_wol_filter_reset(struct efx_nic *efx)
  979. {
  980. int rc;
  981. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_RESET, NULL, 0, NULL, 0, NULL);
  982. if (rc)
  983. goto fail;
  984. return 0;
  985. fail:
  986. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  987. return rc;
  988. }