7990.c 21 KB

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  1. /*
  2. * 7990.c -- LANCE ethernet IC generic routines.
  3. * This is an attempt to separate out the bits of various ethernet
  4. * drivers that are common because they all use the AMD 7990 LANCE
  5. * (Local Area Network Controller for Ethernet) chip.
  6. *
  7. * Copyright (C) 05/1998 Peter Maydell <pmaydell@chiark.greenend.org.uk>
  8. *
  9. * Most of this stuff was obtained by looking at other LANCE drivers,
  10. * in particular a2065.[ch]. The AMD C-LANCE datasheet was also helpful.
  11. * NB: this was made easy by the fact that Jes Sorensen had cleaned up
  12. * most of a2025 and sunlance with the aim of merging them, so the
  13. * common code was pretty obvious.
  14. */
  15. #include <linux/crc32.h>
  16. #include <linux/delay.h>
  17. #include <linux/errno.h>
  18. #include <linux/netdevice.h>
  19. #include <linux/etherdevice.h>
  20. #include <linux/init.h>
  21. #include <linux/module.h>
  22. #include <linux/kernel.h>
  23. #include <linux/types.h>
  24. #include <linux/fcntl.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/ioport.h>
  27. #include <linux/in.h>
  28. #include <linux/route.h>
  29. #include <linux/string.h>
  30. #include <linux/skbuff.h>
  31. #include <asm/irq.h>
  32. /* Used for the temporal inet entries and routing */
  33. #include <linux/socket.h>
  34. #include <linux/bitops.h>
  35. #include <asm/io.h>
  36. #include <asm/dma.h>
  37. #include <asm/pgtable.h>
  38. #ifdef CONFIG_HP300
  39. #include <asm/blinken.h>
  40. #endif
  41. #include "7990.h"
  42. #define WRITERAP(lp,x) out_be16(lp->base + LANCE_RAP, (x))
  43. #define WRITERDP(lp,x) out_be16(lp->base + LANCE_RDP, (x))
  44. #define READRDP(lp) in_be16(lp->base + LANCE_RDP)
  45. #if defined(CONFIG_HPLANCE) || defined(CONFIG_HPLANCE_MODULE)
  46. #include "hplance.h"
  47. #undef WRITERAP
  48. #undef WRITERDP
  49. #undef READRDP
  50. #if defined(CONFIG_MVME147_NET) || defined(CONFIG_MVME147_NET_MODULE)
  51. /* Lossage Factor Nine, Mr Sulu. */
  52. #define WRITERAP(lp,x) (lp->writerap(lp,x))
  53. #define WRITERDP(lp,x) (lp->writerdp(lp,x))
  54. #define READRDP(lp) (lp->readrdp(lp))
  55. #else
  56. /* These inlines can be used if only CONFIG_HPLANCE is defined */
  57. static inline void WRITERAP(struct lance_private *lp, __u16 value)
  58. {
  59. do {
  60. out_be16(lp->base + HPLANCE_REGOFF + LANCE_RAP, value);
  61. } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
  62. }
  63. static inline void WRITERDP(struct lance_private *lp, __u16 value)
  64. {
  65. do {
  66. out_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP, value);
  67. } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
  68. }
  69. static inline __u16 READRDP(struct lance_private *lp)
  70. {
  71. __u16 value;
  72. do {
  73. value = in_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP);
  74. } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
  75. return value;
  76. }
  77. #endif
  78. #endif /* CONFIG_HPLANCE || CONFIG_HPLANCE_MODULE */
  79. /* debugging output macros, various flavours */
  80. /* #define TEST_HITS */
  81. #ifdef UNDEF
  82. #define PRINT_RINGS() \
  83. do { \
  84. int t; \
  85. for (t=0; t < RX_RING_SIZE; t++) { \
  86. printk("R%d: @(%02X %04X) len %04X, mblen %04X, bits %02X\n",\
  87. t, ib->brx_ring[t].rmd1_hadr, ib->brx_ring[t].rmd0,\
  88. ib->brx_ring[t].length,\
  89. ib->brx_ring[t].mblength, ib->brx_ring[t].rmd1_bits);\
  90. }\
  91. for (t=0; t < TX_RING_SIZE; t++) { \
  92. printk("T%d: @(%02X %04X) len %04X, misc %04X, bits %02X\n",\
  93. t, ib->btx_ring[t].tmd1_hadr, ib->btx_ring[t].tmd0,\
  94. ib->btx_ring[t].length,\
  95. ib->btx_ring[t].misc, ib->btx_ring[t].tmd1_bits);\
  96. }\
  97. } while (0)
  98. #else
  99. #define PRINT_RINGS()
  100. #endif
  101. /* Load the CSR registers. The LANCE has to be STOPped when we do this! */
  102. static void load_csrs (struct lance_private *lp)
  103. {
  104. volatile struct lance_init_block *aib = lp->lance_init_block;
  105. int leptr;
  106. leptr = LANCE_ADDR (aib);
  107. WRITERAP(lp, LE_CSR1); /* load address of init block */
  108. WRITERDP(lp, leptr & 0xFFFF);
  109. WRITERAP(lp, LE_CSR2);
  110. WRITERDP(lp, leptr >> 16);
  111. WRITERAP(lp, LE_CSR3);
  112. WRITERDP(lp, lp->busmaster_regval); /* set byteswap/ALEctrl/byte ctrl */
  113. /* Point back to csr0 */
  114. WRITERAP(lp, LE_CSR0);
  115. }
  116. /* #define to 0 or 1 appropriately */
  117. #define DEBUG_IRING 0
  118. /* Set up the Lance Rx and Tx rings and the init block */
  119. static void lance_init_ring (struct net_device *dev)
  120. {
  121. struct lance_private *lp = netdev_priv(dev);
  122. volatile struct lance_init_block *ib = lp->init_block;
  123. volatile struct lance_init_block *aib; /* for LANCE_ADDR computations */
  124. int leptr;
  125. int i;
  126. aib = lp->lance_init_block;
  127. lp->rx_new = lp->tx_new = 0;
  128. lp->rx_old = lp->tx_old = 0;
  129. ib->mode = LE_MO_PROM; /* normal, enable Tx & Rx */
  130. /* Copy the ethernet address to the lance init block
  131. * Notice that we do a byteswap if we're big endian.
  132. * [I think this is the right criterion; at least, sunlance,
  133. * a2065 and atarilance do the byteswap and lance.c (PC) doesn't.
  134. * However, the datasheet says that the BSWAP bit doesn't affect
  135. * the init block, so surely it should be low byte first for
  136. * everybody? Um.]
  137. * We could define the ib->physaddr as three 16bit values and
  138. * use (addr[1] << 8) | addr[0] & co, but this is more efficient.
  139. */
  140. #ifdef __BIG_ENDIAN
  141. ib->phys_addr [0] = dev->dev_addr [1];
  142. ib->phys_addr [1] = dev->dev_addr [0];
  143. ib->phys_addr [2] = dev->dev_addr [3];
  144. ib->phys_addr [3] = dev->dev_addr [2];
  145. ib->phys_addr [4] = dev->dev_addr [5];
  146. ib->phys_addr [5] = dev->dev_addr [4];
  147. #else
  148. for (i=0; i<6; i++)
  149. ib->phys_addr[i] = dev->dev_addr[i];
  150. #endif
  151. if (DEBUG_IRING)
  152. printk ("TX rings:\n");
  153. lp->tx_full = 0;
  154. /* Setup the Tx ring entries */
  155. for (i = 0; i < (1<<lp->lance_log_tx_bufs); i++) {
  156. leptr = LANCE_ADDR(&aib->tx_buf[i][0]);
  157. ib->btx_ring [i].tmd0 = leptr;
  158. ib->btx_ring [i].tmd1_hadr = leptr >> 16;
  159. ib->btx_ring [i].tmd1_bits = 0;
  160. ib->btx_ring [i].length = 0xf000; /* The ones required by tmd2 */
  161. ib->btx_ring [i].misc = 0;
  162. if (DEBUG_IRING)
  163. printk ("%d: 0x%8.8x\n", i, leptr);
  164. }
  165. /* Setup the Rx ring entries */
  166. if (DEBUG_IRING)
  167. printk ("RX rings:\n");
  168. for (i = 0; i < (1<<lp->lance_log_rx_bufs); i++) {
  169. leptr = LANCE_ADDR(&aib->rx_buf[i][0]);
  170. ib->brx_ring [i].rmd0 = leptr;
  171. ib->brx_ring [i].rmd1_hadr = leptr >> 16;
  172. ib->brx_ring [i].rmd1_bits = LE_R1_OWN;
  173. /* 0xf000 == bits that must be one (reserved, presumably) */
  174. ib->brx_ring [i].length = -RX_BUFF_SIZE | 0xf000;
  175. ib->brx_ring [i].mblength = 0;
  176. if (DEBUG_IRING)
  177. printk ("%d: 0x%8.8x\n", i, leptr);
  178. }
  179. /* Setup the initialization block */
  180. /* Setup rx descriptor pointer */
  181. leptr = LANCE_ADDR(&aib->brx_ring);
  182. ib->rx_len = (lp->lance_log_rx_bufs << 13) | (leptr >> 16);
  183. ib->rx_ptr = leptr;
  184. if (DEBUG_IRING)
  185. printk ("RX ptr: %8.8x\n", leptr);
  186. /* Setup tx descriptor pointer */
  187. leptr = LANCE_ADDR(&aib->btx_ring);
  188. ib->tx_len = (lp->lance_log_tx_bufs << 13) | (leptr >> 16);
  189. ib->tx_ptr = leptr;
  190. if (DEBUG_IRING)
  191. printk ("TX ptr: %8.8x\n", leptr);
  192. /* Clear the multicast filter */
  193. ib->filter [0] = 0;
  194. ib->filter [1] = 0;
  195. PRINT_RINGS();
  196. }
  197. /* LANCE must be STOPped before we do this, too... */
  198. static int init_restart_lance (struct lance_private *lp)
  199. {
  200. int i;
  201. WRITERAP(lp, LE_CSR0);
  202. WRITERDP(lp, LE_C0_INIT);
  203. /* Need a hook here for sunlance ledma stuff */
  204. /* Wait for the lance to complete initialization */
  205. for (i = 0; (i < 100) && !(READRDP(lp) & (LE_C0_ERR | LE_C0_IDON)); i++)
  206. barrier();
  207. if ((i == 100) || (READRDP(lp) & LE_C0_ERR)) {
  208. printk ("LANCE unopened after %d ticks, csr0=%4.4x.\n", i, READRDP(lp));
  209. return -1;
  210. }
  211. /* Clear IDON by writing a "1", enable interrupts and start lance */
  212. WRITERDP(lp, LE_C0_IDON);
  213. WRITERDP(lp, LE_C0_INEA | LE_C0_STRT);
  214. return 0;
  215. }
  216. static int lance_reset (struct net_device *dev)
  217. {
  218. struct lance_private *lp = netdev_priv(dev);
  219. int status;
  220. /* Stop the lance */
  221. WRITERAP(lp, LE_CSR0);
  222. WRITERDP(lp, LE_C0_STOP);
  223. load_csrs (lp);
  224. lance_init_ring (dev);
  225. dev->trans_start = jiffies; /* prevent tx timeout */
  226. status = init_restart_lance (lp);
  227. #ifdef DEBUG_DRIVER
  228. printk ("Lance restart=%d\n", status);
  229. #endif
  230. return status;
  231. }
  232. static int lance_rx (struct net_device *dev)
  233. {
  234. struct lance_private *lp = netdev_priv(dev);
  235. volatile struct lance_init_block *ib = lp->init_block;
  236. volatile struct lance_rx_desc *rd;
  237. unsigned char bits;
  238. #ifdef TEST_HITS
  239. int i;
  240. #endif
  241. #ifdef TEST_HITS
  242. printk ("[");
  243. for (i = 0; i < RX_RING_SIZE; i++) {
  244. if (i == lp->rx_new)
  245. printk ("%s",
  246. ib->brx_ring [i].rmd1_bits & LE_R1_OWN ? "_" : "X");
  247. else
  248. printk ("%s",
  249. ib->brx_ring [i].rmd1_bits & LE_R1_OWN ? "." : "1");
  250. }
  251. printk ("]");
  252. #endif
  253. #ifdef CONFIG_HP300
  254. blinken_leds(0x40, 0);
  255. #endif
  256. WRITERDP(lp, LE_C0_RINT | LE_C0_INEA); /* ack Rx int, reenable ints */
  257. for (rd = &ib->brx_ring [lp->rx_new]; /* For each Rx ring we own... */
  258. !((bits = rd->rmd1_bits) & LE_R1_OWN);
  259. rd = &ib->brx_ring [lp->rx_new]) {
  260. /* We got an incomplete frame? */
  261. if ((bits & LE_R1_POK) != LE_R1_POK) {
  262. dev->stats.rx_over_errors++;
  263. dev->stats.rx_errors++;
  264. continue;
  265. } else if (bits & LE_R1_ERR) {
  266. /* Count only the end frame as a rx error,
  267. * not the beginning
  268. */
  269. if (bits & LE_R1_BUF) dev->stats.rx_fifo_errors++;
  270. if (bits & LE_R1_CRC) dev->stats.rx_crc_errors++;
  271. if (bits & LE_R1_OFL) dev->stats.rx_over_errors++;
  272. if (bits & LE_R1_FRA) dev->stats.rx_frame_errors++;
  273. if (bits & LE_R1_EOP) dev->stats.rx_errors++;
  274. } else {
  275. int len = (rd->mblength & 0xfff) - 4;
  276. struct sk_buff *skb = netdev_alloc_skb(dev, len + 2);
  277. if (!skb) {
  278. printk ("%s: Memory squeeze, deferring packet.\n",
  279. dev->name);
  280. dev->stats.rx_dropped++;
  281. rd->mblength = 0;
  282. rd->rmd1_bits = LE_R1_OWN;
  283. lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask;
  284. return 0;
  285. }
  286. skb_reserve (skb, 2); /* 16 byte align */
  287. skb_put (skb, len); /* make room */
  288. skb_copy_to_linear_data(skb,
  289. (unsigned char *)&(ib->rx_buf [lp->rx_new][0]),
  290. len);
  291. skb->protocol = eth_type_trans (skb, dev);
  292. netif_rx (skb);
  293. dev->stats.rx_packets++;
  294. dev->stats.rx_bytes += len;
  295. }
  296. /* Return the packet to the pool */
  297. rd->mblength = 0;
  298. rd->rmd1_bits = LE_R1_OWN;
  299. lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask;
  300. }
  301. return 0;
  302. }
  303. static int lance_tx (struct net_device *dev)
  304. {
  305. struct lance_private *lp = netdev_priv(dev);
  306. volatile struct lance_init_block *ib = lp->init_block;
  307. volatile struct lance_tx_desc *td;
  308. int i, j;
  309. int status;
  310. #ifdef CONFIG_HP300
  311. blinken_leds(0x80, 0);
  312. #endif
  313. /* csr0 is 2f3 */
  314. WRITERDP(lp, LE_C0_TINT | LE_C0_INEA);
  315. /* csr0 is 73 */
  316. j = lp->tx_old;
  317. for (i = j; i != lp->tx_new; i = j) {
  318. td = &ib->btx_ring [i];
  319. /* If we hit a packet not owned by us, stop */
  320. if (td->tmd1_bits & LE_T1_OWN)
  321. break;
  322. if (td->tmd1_bits & LE_T1_ERR) {
  323. status = td->misc;
  324. dev->stats.tx_errors++;
  325. if (status & LE_T3_RTY) dev->stats.tx_aborted_errors++;
  326. if (status & LE_T3_LCOL) dev->stats.tx_window_errors++;
  327. if (status & LE_T3_CLOS) {
  328. dev->stats.tx_carrier_errors++;
  329. if (lp->auto_select) {
  330. lp->tpe = 1 - lp->tpe;
  331. printk("%s: Carrier Lost, trying %s\n",
  332. dev->name, lp->tpe?"TPE":"AUI");
  333. /* Stop the lance */
  334. WRITERAP(lp, LE_CSR0);
  335. WRITERDP(lp, LE_C0_STOP);
  336. lance_init_ring (dev);
  337. load_csrs (lp);
  338. init_restart_lance (lp);
  339. return 0;
  340. }
  341. }
  342. /* buffer errors and underflows turn off the transmitter */
  343. /* Restart the adapter */
  344. if (status & (LE_T3_BUF|LE_T3_UFL)) {
  345. dev->stats.tx_fifo_errors++;
  346. printk ("%s: Tx: ERR_BUF|ERR_UFL, restarting\n",
  347. dev->name);
  348. /* Stop the lance */
  349. WRITERAP(lp, LE_CSR0);
  350. WRITERDP(lp, LE_C0_STOP);
  351. lance_init_ring (dev);
  352. load_csrs (lp);
  353. init_restart_lance (lp);
  354. return 0;
  355. }
  356. } else if ((td->tmd1_bits & LE_T1_POK) == LE_T1_POK) {
  357. /*
  358. * So we don't count the packet more than once.
  359. */
  360. td->tmd1_bits &= ~(LE_T1_POK);
  361. /* One collision before packet was sent. */
  362. if (td->tmd1_bits & LE_T1_EONE)
  363. dev->stats.collisions++;
  364. /* More than one collision, be optimistic. */
  365. if (td->tmd1_bits & LE_T1_EMORE)
  366. dev->stats.collisions += 2;
  367. dev->stats.tx_packets++;
  368. }
  369. j = (j + 1) & lp->tx_ring_mod_mask;
  370. }
  371. lp->tx_old = j;
  372. WRITERDP(lp, LE_C0_TINT | LE_C0_INEA);
  373. return 0;
  374. }
  375. static irqreturn_t
  376. lance_interrupt (int irq, void *dev_id)
  377. {
  378. struct net_device *dev = (struct net_device *)dev_id;
  379. struct lance_private *lp = netdev_priv(dev);
  380. int csr0;
  381. spin_lock (&lp->devlock);
  382. WRITERAP(lp, LE_CSR0); /* LANCE Controller Status */
  383. csr0 = READRDP(lp);
  384. PRINT_RINGS();
  385. if (!(csr0 & LE_C0_INTR)) { /* Check if any interrupt has */
  386. spin_unlock (&lp->devlock);
  387. return IRQ_NONE; /* been generated by the Lance. */
  388. }
  389. /* Acknowledge all the interrupt sources ASAP */
  390. WRITERDP(lp, csr0 & ~(LE_C0_INEA|LE_C0_TDMD|LE_C0_STOP|LE_C0_STRT|LE_C0_INIT));
  391. if ((csr0 & LE_C0_ERR)) {
  392. /* Clear the error condition */
  393. WRITERDP(lp, LE_C0_BABL|LE_C0_ERR|LE_C0_MISS|LE_C0_INEA);
  394. }
  395. if (csr0 & LE_C0_RINT)
  396. lance_rx (dev);
  397. if (csr0 & LE_C0_TINT)
  398. lance_tx (dev);
  399. /* Log misc errors. */
  400. if (csr0 & LE_C0_BABL)
  401. dev->stats.tx_errors++; /* Tx babble. */
  402. if (csr0 & LE_C0_MISS)
  403. dev->stats.rx_errors++; /* Missed a Rx frame. */
  404. if (csr0 & LE_C0_MERR) {
  405. printk("%s: Bus master arbitration failure, status %4.4x.\n",
  406. dev->name, csr0);
  407. /* Restart the chip. */
  408. WRITERDP(lp, LE_C0_STRT);
  409. }
  410. if (lp->tx_full && netif_queue_stopped(dev) && (TX_BUFFS_AVAIL >= 0)) {
  411. lp->tx_full = 0;
  412. netif_wake_queue (dev);
  413. }
  414. WRITERAP(lp, LE_CSR0);
  415. WRITERDP(lp, LE_C0_BABL|LE_C0_CERR|LE_C0_MISS|LE_C0_MERR|LE_C0_IDON|LE_C0_INEA);
  416. spin_unlock (&lp->devlock);
  417. return IRQ_HANDLED;
  418. }
  419. int lance_open (struct net_device *dev)
  420. {
  421. struct lance_private *lp = netdev_priv(dev);
  422. int res;
  423. /* Install the Interrupt handler. Or we could shunt this out to specific drivers? */
  424. if (request_irq(lp->irq, lance_interrupt, IRQF_SHARED, lp->name, dev))
  425. return -EAGAIN;
  426. res = lance_reset(dev);
  427. spin_lock_init(&lp->devlock);
  428. netif_start_queue (dev);
  429. return res;
  430. }
  431. EXPORT_SYMBOL_GPL(lance_open);
  432. int lance_close (struct net_device *dev)
  433. {
  434. struct lance_private *lp = netdev_priv(dev);
  435. netif_stop_queue (dev);
  436. /* Stop the LANCE */
  437. WRITERAP(lp, LE_CSR0);
  438. WRITERDP(lp, LE_C0_STOP);
  439. free_irq(lp->irq, dev);
  440. return 0;
  441. }
  442. EXPORT_SYMBOL_GPL(lance_close);
  443. void lance_tx_timeout(struct net_device *dev)
  444. {
  445. printk("lance_tx_timeout\n");
  446. lance_reset(dev);
  447. dev->trans_start = jiffies; /* prevent tx timeout */
  448. netif_wake_queue (dev);
  449. }
  450. EXPORT_SYMBOL_GPL(lance_tx_timeout);
  451. int lance_start_xmit (struct sk_buff *skb, struct net_device *dev)
  452. {
  453. struct lance_private *lp = netdev_priv(dev);
  454. volatile struct lance_init_block *ib = lp->init_block;
  455. int entry, skblen, len;
  456. static int outs;
  457. unsigned long flags;
  458. if (!TX_BUFFS_AVAIL)
  459. return NETDEV_TX_LOCKED;
  460. netif_stop_queue (dev);
  461. skblen = skb->len;
  462. #ifdef DEBUG_DRIVER
  463. /* dump the packet */
  464. {
  465. int i;
  466. for (i = 0; i < 64; i++) {
  467. if ((i % 16) == 0)
  468. printk ("\n");
  469. printk ("%2.2x ", skb->data [i]);
  470. }
  471. }
  472. #endif
  473. len = (skblen <= ETH_ZLEN) ? ETH_ZLEN : skblen;
  474. entry = lp->tx_new & lp->tx_ring_mod_mask;
  475. ib->btx_ring [entry].length = (-len) | 0xf000;
  476. ib->btx_ring [entry].misc = 0;
  477. if (skb->len < ETH_ZLEN)
  478. memset((void *)&ib->tx_buf[entry][0], 0, ETH_ZLEN);
  479. skb_copy_from_linear_data(skb, (void *)&ib->tx_buf[entry][0], skblen);
  480. /* Now, give the packet to the lance */
  481. ib->btx_ring [entry].tmd1_bits = (LE_T1_POK|LE_T1_OWN);
  482. lp->tx_new = (lp->tx_new+1) & lp->tx_ring_mod_mask;
  483. outs++;
  484. /* Kick the lance: transmit now */
  485. WRITERDP(lp, LE_C0_INEA | LE_C0_TDMD);
  486. dev_kfree_skb (skb);
  487. spin_lock_irqsave (&lp->devlock, flags);
  488. if (TX_BUFFS_AVAIL)
  489. netif_start_queue (dev);
  490. else
  491. lp->tx_full = 1;
  492. spin_unlock_irqrestore (&lp->devlock, flags);
  493. return NETDEV_TX_OK;
  494. }
  495. EXPORT_SYMBOL_GPL(lance_start_xmit);
  496. /* taken from the depca driver via a2065.c */
  497. static void lance_load_multicast (struct net_device *dev)
  498. {
  499. struct lance_private *lp = netdev_priv(dev);
  500. volatile struct lance_init_block *ib = lp->init_block;
  501. volatile u16 *mcast_table = (u16 *)&ib->filter;
  502. struct netdev_hw_addr *ha;
  503. u32 crc;
  504. /* set all multicast bits */
  505. if (dev->flags & IFF_ALLMULTI){
  506. ib->filter [0] = 0xffffffff;
  507. ib->filter [1] = 0xffffffff;
  508. return;
  509. }
  510. /* clear the multicast filter */
  511. ib->filter [0] = 0;
  512. ib->filter [1] = 0;
  513. /* Add addresses */
  514. netdev_for_each_mc_addr(ha, dev) {
  515. crc = ether_crc_le(6, ha->addr);
  516. crc = crc >> 26;
  517. mcast_table [crc >> 4] |= 1 << (crc & 0xf);
  518. }
  519. }
  520. void lance_set_multicast (struct net_device *dev)
  521. {
  522. struct lance_private *lp = netdev_priv(dev);
  523. volatile struct lance_init_block *ib = lp->init_block;
  524. int stopped;
  525. stopped = netif_queue_stopped(dev);
  526. if (!stopped)
  527. netif_stop_queue (dev);
  528. while (lp->tx_old != lp->tx_new)
  529. schedule();
  530. WRITERAP(lp, LE_CSR0);
  531. WRITERDP(lp, LE_C0_STOP);
  532. lance_init_ring (dev);
  533. if (dev->flags & IFF_PROMISC) {
  534. ib->mode |= LE_MO_PROM;
  535. } else {
  536. ib->mode &= ~LE_MO_PROM;
  537. lance_load_multicast (dev);
  538. }
  539. load_csrs (lp);
  540. init_restart_lance (lp);
  541. if (!stopped)
  542. netif_start_queue (dev);
  543. }
  544. EXPORT_SYMBOL_GPL(lance_set_multicast);
  545. #ifdef CONFIG_NET_POLL_CONTROLLER
  546. void lance_poll(struct net_device *dev)
  547. {
  548. struct lance_private *lp = netdev_priv(dev);
  549. spin_lock (&lp->devlock);
  550. WRITERAP(lp, LE_CSR0);
  551. WRITERDP(lp, LE_C0_STRT);
  552. spin_unlock (&lp->devlock);
  553. lance_interrupt(dev->irq, dev);
  554. }
  555. #endif
  556. MODULE_LICENSE("GPL");