sdhci-tegra.c 10 KB

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  1. /*
  2. * Copyright (C) 2010 Google, Inc.
  3. *
  4. * This software is licensed under the terms of the GNU General Public
  5. * License version 2, as published by the Free Software Foundation, and
  6. * may be copied, distributed, and modified under those terms.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. */
  14. #include <linux/err.h>
  15. #include <linux/module.h>
  16. #include <linux/init.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/clk.h>
  19. #include <linux/io.h>
  20. #include <linux/of.h>
  21. #include <linux/of_device.h>
  22. #include <linux/of_gpio.h>
  23. #include <linux/gpio.h>
  24. #include <linux/mmc/card.h>
  25. #include <linux/mmc/host.h>
  26. #include <asm/gpio.h>
  27. #include <mach/gpio-tegra.h>
  28. #include <mach/sdhci.h>
  29. #include "sdhci-pltfm.h"
  30. #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
  31. #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
  32. struct sdhci_tegra_soc_data {
  33. struct sdhci_pltfm_data *pdata;
  34. u32 nvquirks;
  35. };
  36. struct sdhci_tegra {
  37. const struct tegra_sdhci_platform_data *plat;
  38. const struct sdhci_tegra_soc_data *soc_data;
  39. };
  40. static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg)
  41. {
  42. u32 val;
  43. if (unlikely(reg == SDHCI_PRESENT_STATE)) {
  44. /* Use wp_gpio here instead? */
  45. val = readl(host->ioaddr + reg);
  46. return val | SDHCI_WRITE_PROTECT;
  47. }
  48. return readl(host->ioaddr + reg);
  49. }
  50. static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
  51. {
  52. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  53. struct sdhci_tegra *tegra_host = pltfm_host->priv;
  54. const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  55. if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
  56. (reg == SDHCI_HOST_VERSION))) {
  57. /* Erratum: Version register is invalid in HW. */
  58. return SDHCI_SPEC_200;
  59. }
  60. return readw(host->ioaddr + reg);
  61. }
  62. static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
  63. {
  64. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  65. struct sdhci_tegra *tegra_host = pltfm_host->priv;
  66. const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  67. /* Seems like we're getting spurious timeout and crc errors, so
  68. * disable signalling of them. In case of real errors software
  69. * timers should take care of eventually detecting them.
  70. */
  71. if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
  72. val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
  73. writel(val, host->ioaddr + reg);
  74. if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
  75. (reg == SDHCI_INT_ENABLE))) {
  76. /* Erratum: Must enable block gap interrupt detection */
  77. u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
  78. if (val & SDHCI_INT_CARD_INT)
  79. gap_ctrl |= 0x8;
  80. else
  81. gap_ctrl &= ~0x8;
  82. writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
  83. }
  84. }
  85. static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
  86. {
  87. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  88. struct sdhci_tegra *tegra_host = pltfm_host->priv;
  89. const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
  90. if (!gpio_is_valid(plat->wp_gpio))
  91. return -1;
  92. return gpio_get_value(plat->wp_gpio);
  93. }
  94. static irqreturn_t carddetect_irq(int irq, void *data)
  95. {
  96. struct sdhci_host *sdhost = (struct sdhci_host *)data;
  97. tasklet_schedule(&sdhost->card_tasklet);
  98. return IRQ_HANDLED;
  99. };
  100. static int tegra_sdhci_8bit(struct sdhci_host *host, int bus_width)
  101. {
  102. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  103. struct sdhci_tegra *tegra_host = pltfm_host->priv;
  104. const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
  105. u32 ctrl;
  106. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  107. if (plat->is_8bit && bus_width == MMC_BUS_WIDTH_8) {
  108. ctrl &= ~SDHCI_CTRL_4BITBUS;
  109. ctrl |= SDHCI_CTRL_8BITBUS;
  110. } else {
  111. ctrl &= ~SDHCI_CTRL_8BITBUS;
  112. if (bus_width == MMC_BUS_WIDTH_4)
  113. ctrl |= SDHCI_CTRL_4BITBUS;
  114. else
  115. ctrl &= ~SDHCI_CTRL_4BITBUS;
  116. }
  117. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  118. return 0;
  119. }
  120. static struct sdhci_ops tegra_sdhci_ops = {
  121. .get_ro = tegra_sdhci_get_ro,
  122. .read_l = tegra_sdhci_readl,
  123. .read_w = tegra_sdhci_readw,
  124. .write_l = tegra_sdhci_writel,
  125. .platform_8bit_width = tegra_sdhci_8bit,
  126. };
  127. #ifdef CONFIG_ARCH_TEGRA_2x_SOC
  128. static struct sdhci_pltfm_data sdhci_tegra20_pdata = {
  129. .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
  130. SDHCI_QUIRK_SINGLE_POWER_WRITE |
  131. SDHCI_QUIRK_NO_HISPD_BIT |
  132. SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
  133. .ops = &tegra_sdhci_ops,
  134. };
  135. static struct sdhci_tegra_soc_data soc_data_tegra20 = {
  136. .pdata = &sdhci_tegra20_pdata,
  137. .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
  138. NVQUIRK_ENABLE_BLOCK_GAP_DET,
  139. };
  140. #endif
  141. #ifdef CONFIG_ARCH_TEGRA_3x_SOC
  142. static struct sdhci_pltfm_data sdhci_tegra30_pdata = {
  143. .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
  144. SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
  145. SDHCI_QUIRK_SINGLE_POWER_WRITE |
  146. SDHCI_QUIRK_NO_HISPD_BIT |
  147. SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
  148. .ops = &tegra_sdhci_ops,
  149. };
  150. static struct sdhci_tegra_soc_data soc_data_tegra30 = {
  151. .pdata = &sdhci_tegra30_pdata,
  152. };
  153. #endif
  154. static const struct of_device_id sdhci_tegra_dt_match[] __devinitdata = {
  155. #ifdef CONFIG_ARCH_TEGRA_3x_SOC
  156. { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
  157. #endif
  158. #ifdef CONFIG_ARCH_TEGRA_2x_SOC
  159. { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
  160. #endif
  161. {}
  162. };
  163. MODULE_DEVICE_TABLE(of, sdhci_dt_ids);
  164. static struct tegra_sdhci_platform_data * __devinit sdhci_tegra_dt_parse_pdata(
  165. struct platform_device *pdev)
  166. {
  167. struct tegra_sdhci_platform_data *plat;
  168. struct device_node *np = pdev->dev.of_node;
  169. if (!np)
  170. return NULL;
  171. plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
  172. if (!plat) {
  173. dev_err(&pdev->dev, "Can't allocate platform data\n");
  174. return NULL;
  175. }
  176. plat->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
  177. plat->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
  178. plat->power_gpio = of_get_named_gpio(np, "power-gpios", 0);
  179. if (of_find_property(np, "support-8bit", NULL))
  180. plat->is_8bit = 1;
  181. return plat;
  182. }
  183. static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
  184. {
  185. const struct of_device_id *match;
  186. const struct sdhci_tegra_soc_data *soc_data;
  187. struct sdhci_host *host;
  188. struct sdhci_pltfm_host *pltfm_host;
  189. struct tegra_sdhci_platform_data *plat;
  190. struct sdhci_tegra *tegra_host;
  191. struct clk *clk;
  192. int rc;
  193. match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
  194. if (match)
  195. soc_data = match->data;
  196. else
  197. soc_data = &soc_data_tegra20;
  198. host = sdhci_pltfm_init(pdev, soc_data->pdata);
  199. if (IS_ERR(host))
  200. return PTR_ERR(host);
  201. pltfm_host = sdhci_priv(host);
  202. plat = pdev->dev.platform_data;
  203. if (plat == NULL)
  204. plat = sdhci_tegra_dt_parse_pdata(pdev);
  205. if (plat == NULL) {
  206. dev_err(mmc_dev(host->mmc), "missing platform data\n");
  207. rc = -ENXIO;
  208. goto err_no_plat;
  209. }
  210. tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL);
  211. if (!tegra_host) {
  212. dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n");
  213. rc = -ENOMEM;
  214. goto err_no_plat;
  215. }
  216. tegra_host->plat = plat;
  217. tegra_host->soc_data = soc_data;
  218. pltfm_host->priv = tegra_host;
  219. if (gpio_is_valid(plat->power_gpio)) {
  220. rc = gpio_request(plat->power_gpio, "sdhci_power");
  221. if (rc) {
  222. dev_err(mmc_dev(host->mmc),
  223. "failed to allocate power gpio\n");
  224. goto err_power_req;
  225. }
  226. tegra_gpio_enable(plat->power_gpio);
  227. gpio_direction_output(plat->power_gpio, 1);
  228. }
  229. if (gpio_is_valid(plat->cd_gpio)) {
  230. rc = gpio_request(plat->cd_gpio, "sdhci_cd");
  231. if (rc) {
  232. dev_err(mmc_dev(host->mmc),
  233. "failed to allocate cd gpio\n");
  234. goto err_cd_req;
  235. }
  236. tegra_gpio_enable(plat->cd_gpio);
  237. gpio_direction_input(plat->cd_gpio);
  238. rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq,
  239. IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
  240. mmc_hostname(host->mmc), host);
  241. if (rc) {
  242. dev_err(mmc_dev(host->mmc), "request irq error\n");
  243. goto err_cd_irq_req;
  244. }
  245. }
  246. if (gpio_is_valid(plat->wp_gpio)) {
  247. rc = gpio_request(plat->wp_gpio, "sdhci_wp");
  248. if (rc) {
  249. dev_err(mmc_dev(host->mmc),
  250. "failed to allocate wp gpio\n");
  251. goto err_wp_req;
  252. }
  253. tegra_gpio_enable(plat->wp_gpio);
  254. gpio_direction_input(plat->wp_gpio);
  255. }
  256. clk = clk_get(mmc_dev(host->mmc), NULL);
  257. if (IS_ERR(clk)) {
  258. dev_err(mmc_dev(host->mmc), "clk err\n");
  259. rc = PTR_ERR(clk);
  260. goto err_clk_get;
  261. }
  262. clk_enable(clk);
  263. pltfm_host->clk = clk;
  264. host->mmc->pm_caps = plat->pm_flags;
  265. if (plat->is_8bit)
  266. host->mmc->caps |= MMC_CAP_8_BIT_DATA;
  267. rc = sdhci_add_host(host);
  268. if (rc)
  269. goto err_add_host;
  270. return 0;
  271. err_add_host:
  272. clk_disable(pltfm_host->clk);
  273. clk_put(pltfm_host->clk);
  274. err_clk_get:
  275. if (gpio_is_valid(plat->wp_gpio)) {
  276. tegra_gpio_disable(plat->wp_gpio);
  277. gpio_free(plat->wp_gpio);
  278. }
  279. err_wp_req:
  280. if (gpio_is_valid(plat->cd_gpio))
  281. free_irq(gpio_to_irq(plat->cd_gpio), host);
  282. err_cd_irq_req:
  283. if (gpio_is_valid(plat->cd_gpio)) {
  284. tegra_gpio_disable(plat->cd_gpio);
  285. gpio_free(plat->cd_gpio);
  286. }
  287. err_cd_req:
  288. if (gpio_is_valid(plat->power_gpio)) {
  289. tegra_gpio_disable(plat->power_gpio);
  290. gpio_free(plat->power_gpio);
  291. }
  292. err_power_req:
  293. err_no_plat:
  294. sdhci_pltfm_free(pdev);
  295. return rc;
  296. }
  297. static int __devexit sdhci_tegra_remove(struct platform_device *pdev)
  298. {
  299. struct sdhci_host *host = platform_get_drvdata(pdev);
  300. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  301. struct sdhci_tegra *tegra_host = pltfm_host->priv;
  302. const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
  303. int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
  304. sdhci_remove_host(host, dead);
  305. if (gpio_is_valid(plat->wp_gpio)) {
  306. tegra_gpio_disable(plat->wp_gpio);
  307. gpio_free(plat->wp_gpio);
  308. }
  309. if (gpio_is_valid(plat->cd_gpio)) {
  310. free_irq(gpio_to_irq(plat->cd_gpio), host);
  311. tegra_gpio_disable(plat->cd_gpio);
  312. gpio_free(plat->cd_gpio);
  313. }
  314. if (gpio_is_valid(plat->power_gpio)) {
  315. tegra_gpio_disable(plat->power_gpio);
  316. gpio_free(plat->power_gpio);
  317. }
  318. clk_disable(pltfm_host->clk);
  319. clk_put(pltfm_host->clk);
  320. sdhci_pltfm_free(pdev);
  321. return 0;
  322. }
  323. static struct platform_driver sdhci_tegra_driver = {
  324. .driver = {
  325. .name = "sdhci-tegra",
  326. .owner = THIS_MODULE,
  327. .of_match_table = sdhci_tegra_dt_match,
  328. .pm = SDHCI_PLTFM_PMOPS,
  329. },
  330. .probe = sdhci_tegra_probe,
  331. .remove = __devexit_p(sdhci_tegra_remove),
  332. };
  333. module_platform_driver(sdhci_tegra_driver);
  334. MODULE_DESCRIPTION("SDHCI driver for Tegra");
  335. MODULE_AUTHOR("Google, Inc.");
  336. MODULE_LICENSE("GPL v2");