device.c 15 KB

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  1. /*
  2. * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/module.h>
  33. #include <linux/moduleparam.h>
  34. #include <linux/debugfs.h>
  35. #include <rdma/ib_verbs.h>
  36. #include "iw_cxgb4.h"
  37. #define DRV_VERSION "0.1"
  38. MODULE_AUTHOR("Steve Wise");
  39. MODULE_DESCRIPTION("Chelsio T4 RDMA Driver");
  40. MODULE_LICENSE("Dual BSD/GPL");
  41. MODULE_VERSION(DRV_VERSION);
  42. static LIST_HEAD(uld_ctx_list);
  43. static DEFINE_MUTEX(dev_mutex);
  44. static struct dentry *c4iw_debugfs_root;
  45. struct c4iw_debugfs_data {
  46. struct c4iw_dev *devp;
  47. char *buf;
  48. int bufsize;
  49. int pos;
  50. };
  51. static int count_idrs(int id, void *p, void *data)
  52. {
  53. int *countp = data;
  54. *countp = *countp + 1;
  55. return 0;
  56. }
  57. static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count,
  58. loff_t *ppos)
  59. {
  60. struct c4iw_debugfs_data *d = file->private_data;
  61. return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos);
  62. }
  63. static int dump_qp(int id, void *p, void *data)
  64. {
  65. struct c4iw_qp *qp = p;
  66. struct c4iw_debugfs_data *qpd = data;
  67. int space;
  68. int cc;
  69. if (id != qp->wq.sq.qid)
  70. return 0;
  71. space = qpd->bufsize - qpd->pos - 1;
  72. if (space == 0)
  73. return 1;
  74. if (qp->ep)
  75. cc = snprintf(qpd->buf + qpd->pos, space,
  76. "qp sq id %u rq id %u state %u onchip %u "
  77. "ep tid %u state %u %pI4:%u->%pI4:%u\n",
  78. qp->wq.sq.qid, qp->wq.rq.qid, (int)qp->attr.state,
  79. qp->wq.sq.flags & T4_SQ_ONCHIP,
  80. qp->ep->hwtid, (int)qp->ep->com.state,
  81. &qp->ep->com.local_addr.sin_addr.s_addr,
  82. ntohs(qp->ep->com.local_addr.sin_port),
  83. &qp->ep->com.remote_addr.sin_addr.s_addr,
  84. ntohs(qp->ep->com.remote_addr.sin_port));
  85. else
  86. cc = snprintf(qpd->buf + qpd->pos, space,
  87. "qp sq id %u rq id %u state %u onchip %u\n",
  88. qp->wq.sq.qid, qp->wq.rq.qid,
  89. (int)qp->attr.state,
  90. qp->wq.sq.flags & T4_SQ_ONCHIP);
  91. if (cc < space)
  92. qpd->pos += cc;
  93. return 0;
  94. }
  95. static int qp_release(struct inode *inode, struct file *file)
  96. {
  97. struct c4iw_debugfs_data *qpd = file->private_data;
  98. if (!qpd) {
  99. printk(KERN_INFO "%s null qpd?\n", __func__);
  100. return 0;
  101. }
  102. kfree(qpd->buf);
  103. kfree(qpd);
  104. return 0;
  105. }
  106. static int qp_open(struct inode *inode, struct file *file)
  107. {
  108. struct c4iw_debugfs_data *qpd;
  109. int ret = 0;
  110. int count = 1;
  111. qpd = kmalloc(sizeof *qpd, GFP_KERNEL);
  112. if (!qpd) {
  113. ret = -ENOMEM;
  114. goto out;
  115. }
  116. qpd->devp = inode->i_private;
  117. qpd->pos = 0;
  118. spin_lock_irq(&qpd->devp->lock);
  119. idr_for_each(&qpd->devp->qpidr, count_idrs, &count);
  120. spin_unlock_irq(&qpd->devp->lock);
  121. qpd->bufsize = count * 128;
  122. qpd->buf = kmalloc(qpd->bufsize, GFP_KERNEL);
  123. if (!qpd->buf) {
  124. ret = -ENOMEM;
  125. goto err1;
  126. }
  127. spin_lock_irq(&qpd->devp->lock);
  128. idr_for_each(&qpd->devp->qpidr, dump_qp, qpd);
  129. spin_unlock_irq(&qpd->devp->lock);
  130. qpd->buf[qpd->pos++] = 0;
  131. file->private_data = qpd;
  132. goto out;
  133. err1:
  134. kfree(qpd);
  135. out:
  136. return ret;
  137. }
  138. static const struct file_operations qp_debugfs_fops = {
  139. .owner = THIS_MODULE,
  140. .open = qp_open,
  141. .release = qp_release,
  142. .read = debugfs_read,
  143. .llseek = default_llseek,
  144. };
  145. static int dump_stag(int id, void *p, void *data)
  146. {
  147. struct c4iw_debugfs_data *stagd = data;
  148. int space;
  149. int cc;
  150. space = stagd->bufsize - stagd->pos - 1;
  151. if (space == 0)
  152. return 1;
  153. cc = snprintf(stagd->buf + stagd->pos, space, "0x%x\n", id<<8);
  154. if (cc < space)
  155. stagd->pos += cc;
  156. return 0;
  157. }
  158. static int stag_release(struct inode *inode, struct file *file)
  159. {
  160. struct c4iw_debugfs_data *stagd = file->private_data;
  161. if (!stagd) {
  162. printk(KERN_INFO "%s null stagd?\n", __func__);
  163. return 0;
  164. }
  165. kfree(stagd->buf);
  166. kfree(stagd);
  167. return 0;
  168. }
  169. static int stag_open(struct inode *inode, struct file *file)
  170. {
  171. struct c4iw_debugfs_data *stagd;
  172. int ret = 0;
  173. int count = 1;
  174. stagd = kmalloc(sizeof *stagd, GFP_KERNEL);
  175. if (!stagd) {
  176. ret = -ENOMEM;
  177. goto out;
  178. }
  179. stagd->devp = inode->i_private;
  180. stagd->pos = 0;
  181. spin_lock_irq(&stagd->devp->lock);
  182. idr_for_each(&stagd->devp->mmidr, count_idrs, &count);
  183. spin_unlock_irq(&stagd->devp->lock);
  184. stagd->bufsize = count * sizeof("0x12345678\n");
  185. stagd->buf = kmalloc(stagd->bufsize, GFP_KERNEL);
  186. if (!stagd->buf) {
  187. ret = -ENOMEM;
  188. goto err1;
  189. }
  190. spin_lock_irq(&stagd->devp->lock);
  191. idr_for_each(&stagd->devp->mmidr, dump_stag, stagd);
  192. spin_unlock_irq(&stagd->devp->lock);
  193. stagd->buf[stagd->pos++] = 0;
  194. file->private_data = stagd;
  195. goto out;
  196. err1:
  197. kfree(stagd);
  198. out:
  199. return ret;
  200. }
  201. static const struct file_operations stag_debugfs_fops = {
  202. .owner = THIS_MODULE,
  203. .open = stag_open,
  204. .release = stag_release,
  205. .read = debugfs_read,
  206. .llseek = default_llseek,
  207. };
  208. static int setup_debugfs(struct c4iw_dev *devp)
  209. {
  210. struct dentry *de;
  211. if (!devp->debugfs_root)
  212. return -1;
  213. de = debugfs_create_file("qps", S_IWUSR, devp->debugfs_root,
  214. (void *)devp, &qp_debugfs_fops);
  215. if (de && de->d_inode)
  216. de->d_inode->i_size = 4096;
  217. de = debugfs_create_file("stags", S_IWUSR, devp->debugfs_root,
  218. (void *)devp, &stag_debugfs_fops);
  219. if (de && de->d_inode)
  220. de->d_inode->i_size = 4096;
  221. return 0;
  222. }
  223. void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
  224. struct c4iw_dev_ucontext *uctx)
  225. {
  226. struct list_head *pos, *nxt;
  227. struct c4iw_qid_list *entry;
  228. mutex_lock(&uctx->lock);
  229. list_for_each_safe(pos, nxt, &uctx->qpids) {
  230. entry = list_entry(pos, struct c4iw_qid_list, entry);
  231. list_del_init(&entry->entry);
  232. if (!(entry->qid & rdev->qpmask))
  233. c4iw_put_resource(&rdev->resource.qid_fifo, entry->qid,
  234. &rdev->resource.qid_fifo_lock);
  235. kfree(entry);
  236. }
  237. list_for_each_safe(pos, nxt, &uctx->qpids) {
  238. entry = list_entry(pos, struct c4iw_qid_list, entry);
  239. list_del_init(&entry->entry);
  240. kfree(entry);
  241. }
  242. mutex_unlock(&uctx->lock);
  243. }
  244. void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
  245. struct c4iw_dev_ucontext *uctx)
  246. {
  247. INIT_LIST_HEAD(&uctx->qpids);
  248. INIT_LIST_HEAD(&uctx->cqids);
  249. mutex_init(&uctx->lock);
  250. }
  251. /* Caller takes care of locking if needed */
  252. static int c4iw_rdev_open(struct c4iw_rdev *rdev)
  253. {
  254. int err;
  255. c4iw_init_dev_ucontext(rdev, &rdev->uctx);
  256. /*
  257. * qpshift is the number of bits to shift the qpid left in order
  258. * to get the correct address of the doorbell for that qp.
  259. */
  260. rdev->qpshift = PAGE_SHIFT - ilog2(rdev->lldi.udb_density);
  261. rdev->qpmask = rdev->lldi.udb_density - 1;
  262. rdev->cqshift = PAGE_SHIFT - ilog2(rdev->lldi.ucq_density);
  263. rdev->cqmask = rdev->lldi.ucq_density - 1;
  264. PDBG("%s dev %s stag start 0x%0x size 0x%0x num stags %d "
  265. "pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x "
  266. "qp qid start %u size %u cq qid start %u size %u\n",
  267. __func__, pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start,
  268. rdev->lldi.vr->stag.size, c4iw_num_stags(rdev),
  269. rdev->lldi.vr->pbl.start,
  270. rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start,
  271. rdev->lldi.vr->rq.size,
  272. rdev->lldi.vr->qp.start,
  273. rdev->lldi.vr->qp.size,
  274. rdev->lldi.vr->cq.start,
  275. rdev->lldi.vr->cq.size);
  276. PDBG("udb len 0x%x udb base %p db_reg %p gts_reg %p qpshift %lu "
  277. "qpmask 0x%x cqshift %lu cqmask 0x%x\n",
  278. (unsigned)pci_resource_len(rdev->lldi.pdev, 2),
  279. (void *)pci_resource_start(rdev->lldi.pdev, 2),
  280. rdev->lldi.db_reg,
  281. rdev->lldi.gts_reg,
  282. rdev->qpshift, rdev->qpmask,
  283. rdev->cqshift, rdev->cqmask);
  284. if (c4iw_num_stags(rdev) == 0) {
  285. err = -EINVAL;
  286. goto err1;
  287. }
  288. err = c4iw_init_resource(rdev, c4iw_num_stags(rdev), T4_MAX_NUM_PD);
  289. if (err) {
  290. printk(KERN_ERR MOD "error %d initializing resources\n", err);
  291. goto err1;
  292. }
  293. err = c4iw_pblpool_create(rdev);
  294. if (err) {
  295. printk(KERN_ERR MOD "error %d initializing pbl pool\n", err);
  296. goto err2;
  297. }
  298. err = c4iw_rqtpool_create(rdev);
  299. if (err) {
  300. printk(KERN_ERR MOD "error %d initializing rqt pool\n", err);
  301. goto err3;
  302. }
  303. err = c4iw_ocqp_pool_create(rdev);
  304. if (err) {
  305. printk(KERN_ERR MOD "error %d initializing ocqp pool\n", err);
  306. goto err4;
  307. }
  308. return 0;
  309. err4:
  310. c4iw_rqtpool_destroy(rdev);
  311. err3:
  312. c4iw_pblpool_destroy(rdev);
  313. err2:
  314. c4iw_destroy_resource(&rdev->resource);
  315. err1:
  316. return err;
  317. }
  318. static void c4iw_rdev_close(struct c4iw_rdev *rdev)
  319. {
  320. c4iw_pblpool_destroy(rdev);
  321. c4iw_rqtpool_destroy(rdev);
  322. c4iw_destroy_resource(&rdev->resource);
  323. }
  324. struct uld_ctx {
  325. struct list_head entry;
  326. struct cxgb4_lld_info lldi;
  327. struct c4iw_dev *dev;
  328. };
  329. static void c4iw_dealloc(struct uld_ctx *ctx)
  330. {
  331. c4iw_rdev_close(&ctx->dev->rdev);
  332. idr_destroy(&ctx->dev->cqidr);
  333. idr_destroy(&ctx->dev->qpidr);
  334. idr_destroy(&ctx->dev->mmidr);
  335. iounmap(ctx->dev->rdev.oc_mw_kva);
  336. ib_dealloc_device(&ctx->dev->ibdev);
  337. ctx->dev = NULL;
  338. }
  339. static void c4iw_remove(struct uld_ctx *ctx)
  340. {
  341. PDBG("%s c4iw_dev %p\n", __func__, ctx->dev);
  342. c4iw_unregister_device(ctx->dev);
  343. c4iw_dealloc(ctx);
  344. }
  345. static int rdma_supported(const struct cxgb4_lld_info *infop)
  346. {
  347. return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 &&
  348. infop->vr->rq.size > 0 && infop->vr->qp.size > 0 &&
  349. infop->vr->cq.size > 0 && infop->vr->ocq.size > 0;
  350. }
  351. static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop)
  352. {
  353. struct c4iw_dev *devp;
  354. int ret;
  355. if (!rdma_supported(infop)) {
  356. printk(KERN_INFO MOD "%s: RDMA not supported on this device.\n",
  357. pci_name(infop->pdev));
  358. return ERR_PTR(-ENOSYS);
  359. }
  360. devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp));
  361. if (!devp) {
  362. printk(KERN_ERR MOD "Cannot allocate ib device\n");
  363. return ERR_PTR(-ENOMEM);
  364. }
  365. devp->rdev.lldi = *infop;
  366. devp->rdev.oc_mw_pa = pci_resource_start(devp->rdev.lldi.pdev, 2) +
  367. (pci_resource_len(devp->rdev.lldi.pdev, 2) -
  368. roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size));
  369. devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa,
  370. devp->rdev.lldi.vr->ocq.size);
  371. PDBG(KERN_INFO MOD "ocq memory: "
  372. "hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n",
  373. devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size,
  374. devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva);
  375. ret = c4iw_rdev_open(&devp->rdev);
  376. if (ret) {
  377. printk(KERN_ERR MOD "Unable to open CXIO rdev err %d\n", ret);
  378. ib_dealloc_device(&devp->ibdev);
  379. return ERR_PTR(ret);
  380. }
  381. idr_init(&devp->cqidr);
  382. idr_init(&devp->qpidr);
  383. idr_init(&devp->mmidr);
  384. spin_lock_init(&devp->lock);
  385. if (c4iw_debugfs_root) {
  386. devp->debugfs_root = debugfs_create_dir(
  387. pci_name(devp->rdev.lldi.pdev),
  388. c4iw_debugfs_root);
  389. setup_debugfs(devp);
  390. }
  391. return devp;
  392. }
  393. static void *c4iw_uld_add(const struct cxgb4_lld_info *infop)
  394. {
  395. struct uld_ctx *ctx;
  396. static int vers_printed;
  397. int i;
  398. if (!vers_printed++)
  399. printk(KERN_INFO MOD "Chelsio T4 RDMA Driver - version %s\n",
  400. DRV_VERSION);
  401. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  402. if (!ctx) {
  403. ctx = ERR_PTR(-ENOMEM);
  404. goto out;
  405. }
  406. ctx->lldi = *infop;
  407. PDBG("%s found device %s nchan %u nrxq %u ntxq %u nports %u\n",
  408. __func__, pci_name(ctx->lldi.pdev),
  409. ctx->lldi.nchan, ctx->lldi.nrxq,
  410. ctx->lldi.ntxq, ctx->lldi.nports);
  411. mutex_lock(&dev_mutex);
  412. list_add_tail(&ctx->entry, &uld_ctx_list);
  413. mutex_unlock(&dev_mutex);
  414. for (i = 0; i < ctx->lldi.nrxq; i++)
  415. PDBG("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]);
  416. out:
  417. return ctx;
  418. }
  419. static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp,
  420. const struct pkt_gl *gl)
  421. {
  422. struct uld_ctx *ctx = handle;
  423. struct c4iw_dev *dev = ctx->dev;
  424. struct sk_buff *skb;
  425. const struct cpl_act_establish *rpl;
  426. unsigned int opcode;
  427. if (gl == NULL) {
  428. /* omit RSS and rsp_ctrl at end of descriptor */
  429. unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8;
  430. skb = alloc_skb(256, GFP_ATOMIC);
  431. if (!skb)
  432. goto nomem;
  433. __skb_put(skb, len);
  434. skb_copy_to_linear_data(skb, &rsp[1], len);
  435. } else if (gl == CXGB4_MSG_AN) {
  436. const struct rsp_ctrl *rc = (void *)rsp;
  437. u32 qid = be32_to_cpu(rc->pldbuflen_qid);
  438. c4iw_ev_handler(dev, qid);
  439. return 0;
  440. } else {
  441. skb = cxgb4_pktgl_to_skb(gl, 128, 128);
  442. if (unlikely(!skb))
  443. goto nomem;
  444. }
  445. rpl = cplhdr(skb);
  446. opcode = rpl->ot.opcode;
  447. if (c4iw_handlers[opcode])
  448. c4iw_handlers[opcode](dev, skb);
  449. else
  450. printk(KERN_INFO "%s no handler opcode 0x%x...\n", __func__,
  451. opcode);
  452. return 0;
  453. nomem:
  454. return -1;
  455. }
  456. static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state)
  457. {
  458. struct uld_ctx *ctx = handle;
  459. PDBG("%s new_state %u\n", __func__, new_state);
  460. switch (new_state) {
  461. case CXGB4_STATE_UP:
  462. printk(KERN_INFO MOD "%s: Up\n", pci_name(ctx->lldi.pdev));
  463. if (!ctx->dev) {
  464. int ret;
  465. ctx->dev = c4iw_alloc(&ctx->lldi);
  466. if (IS_ERR(ctx->dev)) {
  467. printk(KERN_ERR MOD
  468. "%s: initialization failed: %ld\n",
  469. pci_name(ctx->lldi.pdev),
  470. PTR_ERR(ctx->dev));
  471. ctx->dev = NULL;
  472. break;
  473. }
  474. ret = c4iw_register_device(ctx->dev);
  475. if (ret) {
  476. printk(KERN_ERR MOD
  477. "%s: RDMA registration failed: %d\n",
  478. pci_name(ctx->lldi.pdev), ret);
  479. c4iw_dealloc(ctx);
  480. }
  481. }
  482. break;
  483. case CXGB4_STATE_DOWN:
  484. printk(KERN_INFO MOD "%s: Down\n",
  485. pci_name(ctx->lldi.pdev));
  486. if (ctx->dev)
  487. c4iw_remove(ctx);
  488. break;
  489. case CXGB4_STATE_START_RECOVERY:
  490. printk(KERN_INFO MOD "%s: Fatal Error\n",
  491. pci_name(ctx->lldi.pdev));
  492. if (ctx->dev) {
  493. struct ib_event event;
  494. ctx->dev->rdev.flags |= T4_FATAL_ERROR;
  495. memset(&event, 0, sizeof event);
  496. event.event = IB_EVENT_DEVICE_FATAL;
  497. event.device = &ctx->dev->ibdev;
  498. ib_dispatch_event(&event);
  499. c4iw_remove(ctx);
  500. }
  501. break;
  502. case CXGB4_STATE_DETACH:
  503. printk(KERN_INFO MOD "%s: Detach\n",
  504. pci_name(ctx->lldi.pdev));
  505. if (ctx->dev)
  506. c4iw_remove(ctx);
  507. break;
  508. }
  509. return 0;
  510. }
  511. static struct cxgb4_uld_info c4iw_uld_info = {
  512. .name = DRV_NAME,
  513. .add = c4iw_uld_add,
  514. .rx_handler = c4iw_uld_rx_handler,
  515. .state_change = c4iw_uld_state_change,
  516. };
  517. static int __init c4iw_init_module(void)
  518. {
  519. int err;
  520. err = c4iw_cm_init();
  521. if (err)
  522. return err;
  523. c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL);
  524. if (!c4iw_debugfs_root)
  525. printk(KERN_WARNING MOD
  526. "could not create debugfs entry, continuing\n");
  527. cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info);
  528. return 0;
  529. }
  530. static void __exit c4iw_exit_module(void)
  531. {
  532. struct uld_ctx *ctx, *tmp;
  533. mutex_lock(&dev_mutex);
  534. list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) {
  535. if (ctx->dev)
  536. c4iw_remove(ctx);
  537. kfree(ctx);
  538. }
  539. mutex_unlock(&dev_mutex);
  540. cxgb4_unregister_uld(CXGB4_ULD_RDMA);
  541. c4iw_cm_term();
  542. debugfs_remove_recursive(c4iw_debugfs_root);
  543. }
  544. module_init(c4iw_init_module);
  545. module_exit(c4iw_exit_module);