lpd270.c 12 KB

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  1. /*
  2. * linux/arch/arm/mach-pxa/lpd270.c
  3. *
  4. * Support for the LogicPD PXA270 Card Engine.
  5. * Derived from the mainstone code, which carries these notices:
  6. *
  7. * Author: Nicolas Pitre
  8. * Created: Nov 05, 2002
  9. * Copyright: MontaVista Software Inc.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/gpio.h>
  16. #include <linux/init.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/syscore_ops.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/sched.h>
  21. #include <linux/bitops.h>
  22. #include <linux/fb.h>
  23. #include <linux/ioport.h>
  24. #include <linux/mtd/mtd.h>
  25. #include <linux/mtd/partitions.h>
  26. #include <linux/pwm_backlight.h>
  27. #include <asm/types.h>
  28. #include <asm/setup.h>
  29. #include <asm/memory.h>
  30. #include <asm/mach-types.h>
  31. #include <mach/hardware.h>
  32. #include <asm/irq.h>
  33. #include <asm/sizes.h>
  34. #include <asm/mach/arch.h>
  35. #include <asm/mach/map.h>
  36. #include <asm/mach/irq.h>
  37. #include <asm/mach/flash.h>
  38. #include <mach/pxa27x.h>
  39. #include <mach/lpd270.h>
  40. #include <mach/audio.h>
  41. #include <mach/pxafb.h>
  42. #include <mach/mmc.h>
  43. #include <mach/irda.h>
  44. #include <mach/ohci.h>
  45. #include <mach/smemc.h>
  46. #include "generic.h"
  47. #include "devices.h"
  48. static unsigned long lpd270_pin_config[] __initdata = {
  49. /* Chip Selects */
  50. GPIO15_nCS_1, /* Mainboard Flash */
  51. GPIO78_nCS_2, /* CPLD + Ethernet */
  52. /* LCD - 16bpp Active TFT */
  53. GPIO58_LCD_LDD_0,
  54. GPIO59_LCD_LDD_1,
  55. GPIO60_LCD_LDD_2,
  56. GPIO61_LCD_LDD_3,
  57. GPIO62_LCD_LDD_4,
  58. GPIO63_LCD_LDD_5,
  59. GPIO64_LCD_LDD_6,
  60. GPIO65_LCD_LDD_7,
  61. GPIO66_LCD_LDD_8,
  62. GPIO67_LCD_LDD_9,
  63. GPIO68_LCD_LDD_10,
  64. GPIO69_LCD_LDD_11,
  65. GPIO70_LCD_LDD_12,
  66. GPIO71_LCD_LDD_13,
  67. GPIO72_LCD_LDD_14,
  68. GPIO73_LCD_LDD_15,
  69. GPIO74_LCD_FCLK,
  70. GPIO75_LCD_LCLK,
  71. GPIO76_LCD_PCLK,
  72. GPIO77_LCD_BIAS,
  73. GPIO16_PWM0_OUT, /* Backlight */
  74. /* USB Host */
  75. GPIO88_USBH1_PWR,
  76. GPIO89_USBH1_PEN,
  77. /* AC97 */
  78. GPIO28_AC97_BITCLK,
  79. GPIO29_AC97_SDATA_IN_0,
  80. GPIO30_AC97_SDATA_OUT,
  81. GPIO31_AC97_SYNC,
  82. GPIO45_AC97_SYSCLK,
  83. GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
  84. };
  85. static unsigned int lpd270_irq_enabled;
  86. static void lpd270_mask_irq(struct irq_data *d)
  87. {
  88. int lpd270_irq = d->irq - LPD270_IRQ(0);
  89. __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
  90. lpd270_irq_enabled &= ~(1 << lpd270_irq);
  91. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  92. }
  93. static void lpd270_unmask_irq(struct irq_data *d)
  94. {
  95. int lpd270_irq = d->irq - LPD270_IRQ(0);
  96. lpd270_irq_enabled |= 1 << lpd270_irq;
  97. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  98. }
  99. static struct irq_chip lpd270_irq_chip = {
  100. .name = "CPLD",
  101. .irq_ack = lpd270_mask_irq,
  102. .irq_mask = lpd270_mask_irq,
  103. .irq_unmask = lpd270_unmask_irq,
  104. };
  105. static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
  106. {
  107. unsigned long pending;
  108. pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
  109. do {
  110. /* clear useless edge notification */
  111. desc->irq_data.chip->irq_ack(&desc->irq_data);
  112. if (likely(pending)) {
  113. irq = LPD270_IRQ(0) + __ffs(pending);
  114. generic_handle_irq(irq);
  115. pending = __raw_readw(LPD270_INT_STATUS) &
  116. lpd270_irq_enabled;
  117. }
  118. } while (pending);
  119. }
  120. static void __init lpd270_init_irq(void)
  121. {
  122. int irq;
  123. pxa27x_init_irq();
  124. __raw_writew(0, LPD270_INT_MASK);
  125. __raw_writew(0, LPD270_INT_STATUS);
  126. /* setup extra LogicPD PXA270 irqs */
  127. for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
  128. irq_set_chip_and_handler(irq, &lpd270_irq_chip,
  129. handle_level_irq);
  130. set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
  131. }
  132. irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler);
  133. irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
  134. }
  135. #ifdef CONFIG_PM
  136. static void lpd270_irq_resume(void)
  137. {
  138. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  139. }
  140. static struct syscore_ops lpd270_irq_syscore_ops = {
  141. .resume = lpd270_irq_resume,
  142. };
  143. static int __init lpd270_irq_device_init(void)
  144. {
  145. if (machine_is_logicpd_pxa270()) {
  146. register_syscore_ops(&lpd270_irq_syscore_ops);
  147. return 0;
  148. }
  149. return -ENODEV;
  150. }
  151. device_initcall(lpd270_irq_device_init);
  152. #endif
  153. static struct resource smc91x_resources[] = {
  154. [0] = {
  155. .start = LPD270_ETH_PHYS,
  156. .end = (LPD270_ETH_PHYS + 0xfffff),
  157. .flags = IORESOURCE_MEM,
  158. },
  159. [1] = {
  160. .start = LPD270_ETHERNET_IRQ,
  161. .end = LPD270_ETHERNET_IRQ,
  162. .flags = IORESOURCE_IRQ,
  163. },
  164. };
  165. static struct platform_device smc91x_device = {
  166. .name = "smc91x",
  167. .id = 0,
  168. .num_resources = ARRAY_SIZE(smc91x_resources),
  169. .resource = smc91x_resources,
  170. };
  171. static struct resource lpd270_flash_resources[] = {
  172. [0] = {
  173. .start = PXA_CS0_PHYS,
  174. .end = PXA_CS0_PHYS + SZ_64M - 1,
  175. .flags = IORESOURCE_MEM,
  176. },
  177. [1] = {
  178. .start = PXA_CS1_PHYS,
  179. .end = PXA_CS1_PHYS + SZ_64M - 1,
  180. .flags = IORESOURCE_MEM,
  181. },
  182. };
  183. static struct mtd_partition lpd270_flash0_partitions[] = {
  184. {
  185. .name = "Bootloader",
  186. .size = 0x00040000,
  187. .offset = 0,
  188. .mask_flags = MTD_WRITEABLE /* force read-only */
  189. }, {
  190. .name = "Kernel",
  191. .size = 0x00400000,
  192. .offset = 0x00040000,
  193. }, {
  194. .name = "Filesystem",
  195. .size = MTDPART_SIZ_FULL,
  196. .offset = 0x00440000
  197. },
  198. };
  199. static struct flash_platform_data lpd270_flash_data[2] = {
  200. {
  201. .name = "processor-flash",
  202. .map_name = "cfi_probe",
  203. .parts = lpd270_flash0_partitions,
  204. .nr_parts = ARRAY_SIZE(lpd270_flash0_partitions),
  205. }, {
  206. .name = "mainboard-flash",
  207. .map_name = "cfi_probe",
  208. .parts = NULL,
  209. .nr_parts = 0,
  210. }
  211. };
  212. static struct platform_device lpd270_flash_device[2] = {
  213. {
  214. .name = "pxa2xx-flash",
  215. .id = 0,
  216. .dev = {
  217. .platform_data = &lpd270_flash_data[0],
  218. },
  219. .resource = &lpd270_flash_resources[0],
  220. .num_resources = 1,
  221. }, {
  222. .name = "pxa2xx-flash",
  223. .id = 1,
  224. .dev = {
  225. .platform_data = &lpd270_flash_data[1],
  226. },
  227. .resource = &lpd270_flash_resources[1],
  228. .num_resources = 1,
  229. },
  230. };
  231. static struct platform_pwm_backlight_data lpd270_backlight_data = {
  232. .pwm_id = 0,
  233. .max_brightness = 1,
  234. .dft_brightness = 1,
  235. .pwm_period_ns = 78770,
  236. };
  237. static struct platform_device lpd270_backlight_device = {
  238. .name = "pwm-backlight",
  239. .dev = {
  240. .parent = &pxa27x_device_pwm0.dev,
  241. .platform_data = &lpd270_backlight_data,
  242. },
  243. };
  244. /* 5.7" TFT QVGA (LoLo display number 1) */
  245. static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
  246. .pixclock = 150000,
  247. .xres = 320,
  248. .yres = 240,
  249. .bpp = 16,
  250. .hsync_len = 0x14,
  251. .left_margin = 0x28,
  252. .right_margin = 0x0a,
  253. .vsync_len = 0x02,
  254. .upper_margin = 0x08,
  255. .lower_margin = 0x14,
  256. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  257. };
  258. static struct pxafb_mach_info sharp_lq057q3dc02 = {
  259. .modes = &sharp_lq057q3dc02_mode,
  260. .num_modes = 1,
  261. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  262. LCD_ALTERNATE_MAPPING,
  263. };
  264. /* 12.1" TFT SVGA (LoLo display number 2) */
  265. static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
  266. .pixclock = 50000,
  267. .xres = 800,
  268. .yres = 600,
  269. .bpp = 16,
  270. .hsync_len = 0x05,
  271. .left_margin = 0x52,
  272. .right_margin = 0x05,
  273. .vsync_len = 0x04,
  274. .upper_margin = 0x14,
  275. .lower_margin = 0x0a,
  276. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  277. };
  278. static struct pxafb_mach_info sharp_lq121s1dg31 = {
  279. .modes = &sharp_lq121s1dg31_mode,
  280. .num_modes = 1,
  281. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  282. LCD_ALTERNATE_MAPPING,
  283. };
  284. /* 3.6" TFT QVGA (LoLo display number 3) */
  285. static struct pxafb_mode_info sharp_lq036q1da01_mode = {
  286. .pixclock = 150000,
  287. .xres = 320,
  288. .yres = 240,
  289. .bpp = 16,
  290. .hsync_len = 0x0e,
  291. .left_margin = 0x04,
  292. .right_margin = 0x0a,
  293. .vsync_len = 0x03,
  294. .upper_margin = 0x03,
  295. .lower_margin = 0x03,
  296. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  297. };
  298. static struct pxafb_mach_info sharp_lq036q1da01 = {
  299. .modes = &sharp_lq036q1da01_mode,
  300. .num_modes = 1,
  301. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  302. LCD_ALTERNATE_MAPPING,
  303. };
  304. /* 6.4" TFT VGA (LoLo display number 5) */
  305. static struct pxafb_mode_info sharp_lq64d343_mode = {
  306. .pixclock = 25000,
  307. .xres = 640,
  308. .yres = 480,
  309. .bpp = 16,
  310. .hsync_len = 0x31,
  311. .left_margin = 0x89,
  312. .right_margin = 0x19,
  313. .vsync_len = 0x12,
  314. .upper_margin = 0x22,
  315. .lower_margin = 0x00,
  316. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  317. };
  318. static struct pxafb_mach_info sharp_lq64d343 = {
  319. .modes = &sharp_lq64d343_mode,
  320. .num_modes = 1,
  321. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  322. LCD_ALTERNATE_MAPPING,
  323. };
  324. /* 10.4" TFT VGA (LoLo display number 7) */
  325. static struct pxafb_mode_info sharp_lq10d368_mode = {
  326. .pixclock = 25000,
  327. .xres = 640,
  328. .yres = 480,
  329. .bpp = 16,
  330. .hsync_len = 0x31,
  331. .left_margin = 0x89,
  332. .right_margin = 0x19,
  333. .vsync_len = 0x12,
  334. .upper_margin = 0x22,
  335. .lower_margin = 0x00,
  336. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  337. };
  338. static struct pxafb_mach_info sharp_lq10d368 = {
  339. .modes = &sharp_lq10d368_mode,
  340. .num_modes = 1,
  341. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  342. LCD_ALTERNATE_MAPPING,
  343. };
  344. /* 3.5" TFT QVGA (LoLo display number 8) */
  345. static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
  346. .pixclock = 150000,
  347. .xres = 240,
  348. .yres = 320,
  349. .bpp = 16,
  350. .hsync_len = 0x0e,
  351. .left_margin = 0x0a,
  352. .right_margin = 0x0a,
  353. .vsync_len = 0x03,
  354. .upper_margin = 0x05,
  355. .lower_margin = 0x14,
  356. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  357. };
  358. static struct pxafb_mach_info sharp_lq035q7db02_20 = {
  359. .modes = &sharp_lq035q7db02_20_mode,
  360. .num_modes = 1,
  361. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  362. LCD_ALTERNATE_MAPPING,
  363. };
  364. static struct pxafb_mach_info *lpd270_lcd_to_use;
  365. static int __init lpd270_set_lcd(char *str)
  366. {
  367. if (!strnicmp(str, "lq057q3dc02", 11)) {
  368. lpd270_lcd_to_use = &sharp_lq057q3dc02;
  369. } else if (!strnicmp(str, "lq121s1dg31", 11)) {
  370. lpd270_lcd_to_use = &sharp_lq121s1dg31;
  371. } else if (!strnicmp(str, "lq036q1da01", 11)) {
  372. lpd270_lcd_to_use = &sharp_lq036q1da01;
  373. } else if (!strnicmp(str, "lq64d343", 8)) {
  374. lpd270_lcd_to_use = &sharp_lq64d343;
  375. } else if (!strnicmp(str, "lq10d368", 8)) {
  376. lpd270_lcd_to_use = &sharp_lq10d368;
  377. } else if (!strnicmp(str, "lq035q7db02-20", 14)) {
  378. lpd270_lcd_to_use = &sharp_lq035q7db02_20;
  379. } else {
  380. printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
  381. }
  382. return 1;
  383. }
  384. __setup("lcd=", lpd270_set_lcd);
  385. static struct platform_device *platform_devices[] __initdata = {
  386. &smc91x_device,
  387. &lpd270_backlight_device,
  388. &lpd270_flash_device[0],
  389. &lpd270_flash_device[1],
  390. };
  391. static struct pxaohci_platform_data lpd270_ohci_platform_data = {
  392. .port_mode = PMM_PERPORT_MODE,
  393. .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
  394. };
  395. static void __init lpd270_init(void)
  396. {
  397. pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));
  398. pxa_set_ffuart_info(NULL);
  399. pxa_set_btuart_info(NULL);
  400. pxa_set_stuart_info(NULL);
  401. lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
  402. lpd270_flash_data[1].width = 4;
  403. /*
  404. * System bus arbiter setting:
  405. * - Core_Park
  406. * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
  407. */
  408. ARB_CNTRL = ARB_CORE_PARK | 0x234;
  409. platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
  410. pxa_set_ac97_info(NULL);
  411. if (lpd270_lcd_to_use != NULL)
  412. pxa_set_fb_info(NULL, lpd270_lcd_to_use);
  413. pxa_set_ohci_info(&lpd270_ohci_platform_data);
  414. }
  415. static struct map_desc lpd270_io_desc[] __initdata = {
  416. {
  417. .virtual = (unsigned long)LPD270_CPLD_VIRT,
  418. .pfn = __phys_to_pfn(LPD270_CPLD_PHYS),
  419. .length = LPD270_CPLD_SIZE,
  420. .type = MT_DEVICE,
  421. },
  422. };
  423. static void __init lpd270_map_io(void)
  424. {
  425. pxa27x_map_io();
  426. iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
  427. /* for use I SRAM as framebuffer. */
  428. PSLR |= 0x00000F04;
  429. PCFR = 0x00000066;
  430. }
  431. MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
  432. /* Maintainer: Peter Barada */
  433. .atag_offset = 0x100,
  434. .map_io = lpd270_map_io,
  435. .nr_irqs = LPD270_NR_IRQS,
  436. .init_irq = lpd270_init_irq,
  437. .handle_irq = pxa27x_handle_irq,
  438. .timer = &pxa_timer,
  439. .init_machine = lpd270_init,
  440. .restart = pxa_restart,
  441. MACHINE_END