devices.c 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119
  1. #include <linux/module.h>
  2. #include <linux/kernel.h>
  3. #include <linux/init.h>
  4. #include <linux/platform_device.h>
  5. #include <linux/dma-mapping.h>
  6. #include <linux/spi/pxa2xx_spi.h>
  7. #include <linux/i2c/pxa-i2c.h>
  8. #include <asm/pmu.h>
  9. #include <mach/udc.h>
  10. #include <mach/pxa3xx-u2d.h>
  11. #include <mach/pxafb.h>
  12. #include <mach/mmc.h>
  13. #include <mach/irda.h>
  14. #include <mach/irqs.h>
  15. #include <mach/ohci.h>
  16. #include <plat/pxa27x_keypad.h>
  17. #include <mach/camera.h>
  18. #include <mach/audio.h>
  19. #include <mach/hardware.h>
  20. #include <plat/pxa3xx_nand.h>
  21. #include "devices.h"
  22. #include "generic.h"
  23. void __init pxa_register_device(struct platform_device *dev, void *data)
  24. {
  25. int ret;
  26. dev->dev.platform_data = data;
  27. ret = platform_device_register(dev);
  28. if (ret)
  29. dev_err(&dev->dev, "unable to register device: %d\n", ret);
  30. }
  31. static struct resource pxa_resource_pmu = {
  32. .start = IRQ_PMU,
  33. .end = IRQ_PMU,
  34. .flags = IORESOURCE_IRQ,
  35. };
  36. struct platform_device pxa_device_pmu = {
  37. .name = "arm-pmu",
  38. .id = ARM_PMU_DEVICE_CPU,
  39. .resource = &pxa_resource_pmu,
  40. .num_resources = 1,
  41. };
  42. static struct resource pxamci_resources[] = {
  43. [0] = {
  44. .start = 0x41100000,
  45. .end = 0x41100fff,
  46. .flags = IORESOURCE_MEM,
  47. },
  48. [1] = {
  49. .start = IRQ_MMC,
  50. .end = IRQ_MMC,
  51. .flags = IORESOURCE_IRQ,
  52. },
  53. [2] = {
  54. .start = 21,
  55. .end = 21,
  56. .flags = IORESOURCE_DMA,
  57. },
  58. [3] = {
  59. .start = 22,
  60. .end = 22,
  61. .flags = IORESOURCE_DMA,
  62. },
  63. };
  64. static u64 pxamci_dmamask = 0xffffffffUL;
  65. struct platform_device pxa_device_mci = {
  66. .name = "pxa2xx-mci",
  67. .id = 0,
  68. .dev = {
  69. .dma_mask = &pxamci_dmamask,
  70. .coherent_dma_mask = 0xffffffff,
  71. },
  72. .num_resources = ARRAY_SIZE(pxamci_resources),
  73. .resource = pxamci_resources,
  74. };
  75. void __init pxa_set_mci_info(struct pxamci_platform_data *info)
  76. {
  77. pxa_register_device(&pxa_device_mci, info);
  78. }
  79. static struct pxa2xx_udc_mach_info pxa_udc_info = {
  80. .gpio_pullup = -1,
  81. };
  82. void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
  83. {
  84. memcpy(&pxa_udc_info, info, sizeof *info);
  85. }
  86. static struct resource pxa2xx_udc_resources[] = {
  87. [0] = {
  88. .start = 0x40600000,
  89. .end = 0x4060ffff,
  90. .flags = IORESOURCE_MEM,
  91. },
  92. [1] = {
  93. .start = IRQ_USB,
  94. .end = IRQ_USB,
  95. .flags = IORESOURCE_IRQ,
  96. },
  97. };
  98. static u64 udc_dma_mask = ~(u32)0;
  99. struct platform_device pxa25x_device_udc = {
  100. .name = "pxa25x-udc",
  101. .id = -1,
  102. .resource = pxa2xx_udc_resources,
  103. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  104. .dev = {
  105. .platform_data = &pxa_udc_info,
  106. .dma_mask = &udc_dma_mask,
  107. }
  108. };
  109. struct platform_device pxa27x_device_udc = {
  110. .name = "pxa27x-udc",
  111. .id = -1,
  112. .resource = pxa2xx_udc_resources,
  113. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  114. .dev = {
  115. .platform_data = &pxa_udc_info,
  116. .dma_mask = &udc_dma_mask,
  117. }
  118. };
  119. #ifdef CONFIG_PXA3xx
  120. static struct resource pxa3xx_u2d_resources[] = {
  121. [0] = {
  122. .start = 0x54100000,
  123. .end = 0x54100fff,
  124. .flags = IORESOURCE_MEM,
  125. },
  126. [1] = {
  127. .start = IRQ_USB2,
  128. .end = IRQ_USB2,
  129. .flags = IORESOURCE_IRQ,
  130. },
  131. };
  132. struct platform_device pxa3xx_device_u2d = {
  133. .name = "pxa3xx-u2d",
  134. .id = -1,
  135. .resource = pxa3xx_u2d_resources,
  136. .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources),
  137. };
  138. void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
  139. {
  140. pxa_register_device(&pxa3xx_device_u2d, info);
  141. }
  142. #endif /* CONFIG_PXA3xx */
  143. static struct resource pxafb_resources[] = {
  144. [0] = {
  145. .start = 0x44000000,
  146. .end = 0x4400ffff,
  147. .flags = IORESOURCE_MEM,
  148. },
  149. [1] = {
  150. .start = IRQ_LCD,
  151. .end = IRQ_LCD,
  152. .flags = IORESOURCE_IRQ,
  153. },
  154. };
  155. static u64 fb_dma_mask = ~(u64)0;
  156. struct platform_device pxa_device_fb = {
  157. .name = "pxa2xx-fb",
  158. .id = -1,
  159. .dev = {
  160. .dma_mask = &fb_dma_mask,
  161. .coherent_dma_mask = 0xffffffff,
  162. },
  163. .num_resources = ARRAY_SIZE(pxafb_resources),
  164. .resource = pxafb_resources,
  165. };
  166. void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
  167. {
  168. pxa_device_fb.dev.parent = parent;
  169. pxa_register_device(&pxa_device_fb, info);
  170. }
  171. static struct resource pxa_resource_ffuart[] = {
  172. {
  173. .start = 0x40100000,
  174. .end = 0x40100023,
  175. .flags = IORESOURCE_MEM,
  176. }, {
  177. .start = IRQ_FFUART,
  178. .end = IRQ_FFUART,
  179. .flags = IORESOURCE_IRQ,
  180. }
  181. };
  182. struct platform_device pxa_device_ffuart = {
  183. .name = "pxa2xx-uart",
  184. .id = 0,
  185. .resource = pxa_resource_ffuart,
  186. .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
  187. };
  188. void __init pxa_set_ffuart_info(void *info)
  189. {
  190. pxa_register_device(&pxa_device_ffuart, info);
  191. }
  192. static struct resource pxa_resource_btuart[] = {
  193. {
  194. .start = 0x40200000,
  195. .end = 0x40200023,
  196. .flags = IORESOURCE_MEM,
  197. }, {
  198. .start = IRQ_BTUART,
  199. .end = IRQ_BTUART,
  200. .flags = IORESOURCE_IRQ,
  201. }
  202. };
  203. struct platform_device pxa_device_btuart = {
  204. .name = "pxa2xx-uart",
  205. .id = 1,
  206. .resource = pxa_resource_btuart,
  207. .num_resources = ARRAY_SIZE(pxa_resource_btuart),
  208. };
  209. void __init pxa_set_btuart_info(void *info)
  210. {
  211. pxa_register_device(&pxa_device_btuart, info);
  212. }
  213. static struct resource pxa_resource_stuart[] = {
  214. {
  215. .start = 0x40700000,
  216. .end = 0x40700023,
  217. .flags = IORESOURCE_MEM,
  218. }, {
  219. .start = IRQ_STUART,
  220. .end = IRQ_STUART,
  221. .flags = IORESOURCE_IRQ,
  222. }
  223. };
  224. struct platform_device pxa_device_stuart = {
  225. .name = "pxa2xx-uart",
  226. .id = 2,
  227. .resource = pxa_resource_stuart,
  228. .num_resources = ARRAY_SIZE(pxa_resource_stuart),
  229. };
  230. void __init pxa_set_stuart_info(void *info)
  231. {
  232. pxa_register_device(&pxa_device_stuart, info);
  233. }
  234. static struct resource pxa_resource_hwuart[] = {
  235. {
  236. .start = 0x41600000,
  237. .end = 0x4160002F,
  238. .flags = IORESOURCE_MEM,
  239. }, {
  240. .start = IRQ_HWUART,
  241. .end = IRQ_HWUART,
  242. .flags = IORESOURCE_IRQ,
  243. }
  244. };
  245. struct platform_device pxa_device_hwuart = {
  246. .name = "pxa2xx-uart",
  247. .id = 3,
  248. .resource = pxa_resource_hwuart,
  249. .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
  250. };
  251. void __init pxa_set_hwuart_info(void *info)
  252. {
  253. if (cpu_is_pxa255())
  254. pxa_register_device(&pxa_device_hwuart, info);
  255. else
  256. pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
  257. }
  258. static struct resource pxai2c_resources[] = {
  259. {
  260. .start = 0x40301680,
  261. .end = 0x403016a3,
  262. .flags = IORESOURCE_MEM,
  263. }, {
  264. .start = IRQ_I2C,
  265. .end = IRQ_I2C,
  266. .flags = IORESOURCE_IRQ,
  267. },
  268. };
  269. struct platform_device pxa_device_i2c = {
  270. .name = "pxa2xx-i2c",
  271. .id = 0,
  272. .resource = pxai2c_resources,
  273. .num_resources = ARRAY_SIZE(pxai2c_resources),
  274. };
  275. void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
  276. {
  277. pxa_register_device(&pxa_device_i2c, info);
  278. }
  279. #ifdef CONFIG_PXA27x
  280. static struct resource pxa27x_resources_i2c_power[] = {
  281. {
  282. .start = 0x40f00180,
  283. .end = 0x40f001a3,
  284. .flags = IORESOURCE_MEM,
  285. }, {
  286. .start = IRQ_PWRI2C,
  287. .end = IRQ_PWRI2C,
  288. .flags = IORESOURCE_IRQ,
  289. },
  290. };
  291. struct platform_device pxa27x_device_i2c_power = {
  292. .name = "pxa2xx-i2c",
  293. .id = 1,
  294. .resource = pxa27x_resources_i2c_power,
  295. .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
  296. };
  297. #endif
  298. static struct resource pxai2s_resources[] = {
  299. {
  300. .start = 0x40400000,
  301. .end = 0x40400083,
  302. .flags = IORESOURCE_MEM,
  303. }, {
  304. .start = IRQ_I2S,
  305. .end = IRQ_I2S,
  306. .flags = IORESOURCE_IRQ,
  307. },
  308. };
  309. struct platform_device pxa_device_i2s = {
  310. .name = "pxa2xx-i2s",
  311. .id = -1,
  312. .resource = pxai2s_resources,
  313. .num_resources = ARRAY_SIZE(pxai2s_resources),
  314. };
  315. struct platform_device pxa_device_asoc_ssp1 = {
  316. .name = "pxa-ssp-dai",
  317. .id = 0,
  318. };
  319. struct platform_device pxa_device_asoc_ssp2= {
  320. .name = "pxa-ssp-dai",
  321. .id = 1,
  322. };
  323. struct platform_device pxa_device_asoc_ssp3 = {
  324. .name = "pxa-ssp-dai",
  325. .id = 2,
  326. };
  327. struct platform_device pxa_device_asoc_ssp4 = {
  328. .name = "pxa-ssp-dai",
  329. .id = 3,
  330. };
  331. struct platform_device pxa_device_asoc_platform = {
  332. .name = "pxa-pcm-audio",
  333. .id = -1,
  334. };
  335. static u64 pxaficp_dmamask = ~(u32)0;
  336. struct platform_device pxa_device_ficp = {
  337. .name = "pxa2xx-ir",
  338. .id = -1,
  339. .dev = {
  340. .dma_mask = &pxaficp_dmamask,
  341. .coherent_dma_mask = 0xffffffff,
  342. },
  343. };
  344. void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
  345. {
  346. pxa_register_device(&pxa_device_ficp, info);
  347. }
  348. static struct resource pxa_rtc_resources[] = {
  349. [0] = {
  350. .start = 0x40900000,
  351. .end = 0x40900000 + 0x3b,
  352. .flags = IORESOURCE_MEM,
  353. },
  354. [1] = {
  355. .start = IRQ_RTC1Hz,
  356. .end = IRQ_RTC1Hz,
  357. .name = "rtc 1Hz",
  358. .flags = IORESOURCE_IRQ,
  359. },
  360. [2] = {
  361. .start = IRQ_RTCAlrm,
  362. .end = IRQ_RTCAlrm,
  363. .name = "rtc alarm",
  364. .flags = IORESOURCE_IRQ,
  365. },
  366. };
  367. struct platform_device pxa_device_rtc = {
  368. .name = "pxa-rtc",
  369. .id = -1,
  370. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  371. .resource = pxa_rtc_resources,
  372. };
  373. static struct resource sa1100_rtc_resources[] = {
  374. {
  375. .start = IRQ_RTC1Hz,
  376. .end = IRQ_RTC1Hz,
  377. .name = "rtc 1Hz",
  378. .flags = IORESOURCE_IRQ,
  379. }, {
  380. .start = IRQ_RTCAlrm,
  381. .end = IRQ_RTCAlrm,
  382. .name = "rtc alarm",
  383. .flags = IORESOURCE_IRQ,
  384. },
  385. };
  386. struct platform_device sa1100_device_rtc = {
  387. .name = "sa1100-rtc",
  388. .id = -1,
  389. .num_resources = ARRAY_SIZE(sa1100_rtc_resources),
  390. .resource = sa1100_rtc_resources,
  391. };
  392. static struct resource pxa_ac97_resources[] = {
  393. [0] = {
  394. .start = 0x40500000,
  395. .end = 0x40500000 + 0xfff,
  396. .flags = IORESOURCE_MEM,
  397. },
  398. [1] = {
  399. .start = IRQ_AC97,
  400. .end = IRQ_AC97,
  401. .flags = IORESOURCE_IRQ,
  402. },
  403. };
  404. static u64 pxa_ac97_dmamask = 0xffffffffUL;
  405. struct platform_device pxa_device_ac97 = {
  406. .name = "pxa2xx-ac97",
  407. .id = -1,
  408. .dev = {
  409. .dma_mask = &pxa_ac97_dmamask,
  410. .coherent_dma_mask = 0xffffffff,
  411. },
  412. .num_resources = ARRAY_SIZE(pxa_ac97_resources),
  413. .resource = pxa_ac97_resources,
  414. };
  415. void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
  416. {
  417. pxa_register_device(&pxa_device_ac97, ops);
  418. }
  419. #ifdef CONFIG_PXA25x
  420. static struct resource pxa25x_resource_pwm0[] = {
  421. [0] = {
  422. .start = 0x40b00000,
  423. .end = 0x40b0000f,
  424. .flags = IORESOURCE_MEM,
  425. },
  426. };
  427. struct platform_device pxa25x_device_pwm0 = {
  428. .name = "pxa25x-pwm",
  429. .id = 0,
  430. .resource = pxa25x_resource_pwm0,
  431. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
  432. };
  433. static struct resource pxa25x_resource_pwm1[] = {
  434. [0] = {
  435. .start = 0x40c00000,
  436. .end = 0x40c0000f,
  437. .flags = IORESOURCE_MEM,
  438. },
  439. };
  440. struct platform_device pxa25x_device_pwm1 = {
  441. .name = "pxa25x-pwm",
  442. .id = 1,
  443. .resource = pxa25x_resource_pwm1,
  444. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
  445. };
  446. static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  447. static struct resource pxa25x_resource_ssp[] = {
  448. [0] = {
  449. .start = 0x41000000,
  450. .end = 0x4100001f,
  451. .flags = IORESOURCE_MEM,
  452. },
  453. [1] = {
  454. .start = IRQ_SSP,
  455. .end = IRQ_SSP,
  456. .flags = IORESOURCE_IRQ,
  457. },
  458. [2] = {
  459. /* DRCMR for RX */
  460. .start = 13,
  461. .end = 13,
  462. .flags = IORESOURCE_DMA,
  463. },
  464. [3] = {
  465. /* DRCMR for TX */
  466. .start = 14,
  467. .end = 14,
  468. .flags = IORESOURCE_DMA,
  469. },
  470. };
  471. struct platform_device pxa25x_device_ssp = {
  472. .name = "pxa25x-ssp",
  473. .id = 0,
  474. .dev = {
  475. .dma_mask = &pxa25x_ssp_dma_mask,
  476. .coherent_dma_mask = DMA_BIT_MASK(32),
  477. },
  478. .resource = pxa25x_resource_ssp,
  479. .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
  480. };
  481. static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  482. static struct resource pxa25x_resource_nssp[] = {
  483. [0] = {
  484. .start = 0x41400000,
  485. .end = 0x4140002f,
  486. .flags = IORESOURCE_MEM,
  487. },
  488. [1] = {
  489. .start = IRQ_NSSP,
  490. .end = IRQ_NSSP,
  491. .flags = IORESOURCE_IRQ,
  492. },
  493. [2] = {
  494. /* DRCMR for RX */
  495. .start = 15,
  496. .end = 15,
  497. .flags = IORESOURCE_DMA,
  498. },
  499. [3] = {
  500. /* DRCMR for TX */
  501. .start = 16,
  502. .end = 16,
  503. .flags = IORESOURCE_DMA,
  504. },
  505. };
  506. struct platform_device pxa25x_device_nssp = {
  507. .name = "pxa25x-nssp",
  508. .id = 1,
  509. .dev = {
  510. .dma_mask = &pxa25x_nssp_dma_mask,
  511. .coherent_dma_mask = DMA_BIT_MASK(32),
  512. },
  513. .resource = pxa25x_resource_nssp,
  514. .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
  515. };
  516. static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
  517. static struct resource pxa25x_resource_assp[] = {
  518. [0] = {
  519. .start = 0x41500000,
  520. .end = 0x4150002f,
  521. .flags = IORESOURCE_MEM,
  522. },
  523. [1] = {
  524. .start = IRQ_ASSP,
  525. .end = IRQ_ASSP,
  526. .flags = IORESOURCE_IRQ,
  527. },
  528. [2] = {
  529. /* DRCMR for RX */
  530. .start = 23,
  531. .end = 23,
  532. .flags = IORESOURCE_DMA,
  533. },
  534. [3] = {
  535. /* DRCMR for TX */
  536. .start = 24,
  537. .end = 24,
  538. .flags = IORESOURCE_DMA,
  539. },
  540. };
  541. struct platform_device pxa25x_device_assp = {
  542. /* ASSP is basically equivalent to NSSP */
  543. .name = "pxa25x-nssp",
  544. .id = 2,
  545. .dev = {
  546. .dma_mask = &pxa25x_assp_dma_mask,
  547. .coherent_dma_mask = DMA_BIT_MASK(32),
  548. },
  549. .resource = pxa25x_resource_assp,
  550. .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
  551. };
  552. #endif /* CONFIG_PXA25x */
  553. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  554. static struct resource pxa27x_resource_camera[] = {
  555. [0] = {
  556. .start = 0x50000000,
  557. .end = 0x50000fff,
  558. .flags = IORESOURCE_MEM,
  559. },
  560. [1] = {
  561. .start = IRQ_CAMERA,
  562. .end = IRQ_CAMERA,
  563. .flags = IORESOURCE_IRQ,
  564. },
  565. };
  566. static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
  567. static struct platform_device pxa27x_device_camera = {
  568. .name = "pxa27x-camera",
  569. .id = 0, /* This is used to put cameras on this interface */
  570. .dev = {
  571. .dma_mask = &pxa27x_dma_mask_camera,
  572. .coherent_dma_mask = 0xffffffff,
  573. },
  574. .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
  575. .resource = pxa27x_resource_camera,
  576. };
  577. void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
  578. {
  579. pxa_register_device(&pxa27x_device_camera, info);
  580. }
  581. static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
  582. static struct resource pxa27x_resource_ohci[] = {
  583. [0] = {
  584. .start = 0x4C000000,
  585. .end = 0x4C00ff6f,
  586. .flags = IORESOURCE_MEM,
  587. },
  588. [1] = {
  589. .start = IRQ_USBH1,
  590. .end = IRQ_USBH1,
  591. .flags = IORESOURCE_IRQ,
  592. },
  593. };
  594. struct platform_device pxa27x_device_ohci = {
  595. .name = "pxa27x-ohci",
  596. .id = -1,
  597. .dev = {
  598. .dma_mask = &pxa27x_ohci_dma_mask,
  599. .coherent_dma_mask = DMA_BIT_MASK(32),
  600. },
  601. .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
  602. .resource = pxa27x_resource_ohci,
  603. };
  604. void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
  605. {
  606. pxa_register_device(&pxa27x_device_ohci, info);
  607. }
  608. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  609. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
  610. static struct resource pxa27x_resource_keypad[] = {
  611. [0] = {
  612. .start = 0x41500000,
  613. .end = 0x4150004c,
  614. .flags = IORESOURCE_MEM,
  615. },
  616. [1] = {
  617. .start = IRQ_KEYPAD,
  618. .end = IRQ_KEYPAD,
  619. .flags = IORESOURCE_IRQ,
  620. },
  621. };
  622. struct platform_device pxa27x_device_keypad = {
  623. .name = "pxa27x-keypad",
  624. .id = -1,
  625. .resource = pxa27x_resource_keypad,
  626. .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
  627. };
  628. void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
  629. {
  630. pxa_register_device(&pxa27x_device_keypad, info);
  631. }
  632. static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
  633. static struct resource pxa27x_resource_ssp1[] = {
  634. [0] = {
  635. .start = 0x41000000,
  636. .end = 0x4100003f,
  637. .flags = IORESOURCE_MEM,
  638. },
  639. [1] = {
  640. .start = IRQ_SSP,
  641. .end = IRQ_SSP,
  642. .flags = IORESOURCE_IRQ,
  643. },
  644. [2] = {
  645. /* DRCMR for RX */
  646. .start = 13,
  647. .end = 13,
  648. .flags = IORESOURCE_DMA,
  649. },
  650. [3] = {
  651. /* DRCMR for TX */
  652. .start = 14,
  653. .end = 14,
  654. .flags = IORESOURCE_DMA,
  655. },
  656. };
  657. struct platform_device pxa27x_device_ssp1 = {
  658. .name = "pxa27x-ssp",
  659. .id = 0,
  660. .dev = {
  661. .dma_mask = &pxa27x_ssp1_dma_mask,
  662. .coherent_dma_mask = DMA_BIT_MASK(32),
  663. },
  664. .resource = pxa27x_resource_ssp1,
  665. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  666. };
  667. static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
  668. static struct resource pxa27x_resource_ssp2[] = {
  669. [0] = {
  670. .start = 0x41700000,
  671. .end = 0x4170003f,
  672. .flags = IORESOURCE_MEM,
  673. },
  674. [1] = {
  675. .start = IRQ_SSP2,
  676. .end = IRQ_SSP2,
  677. .flags = IORESOURCE_IRQ,
  678. },
  679. [2] = {
  680. /* DRCMR for RX */
  681. .start = 15,
  682. .end = 15,
  683. .flags = IORESOURCE_DMA,
  684. },
  685. [3] = {
  686. /* DRCMR for TX */
  687. .start = 16,
  688. .end = 16,
  689. .flags = IORESOURCE_DMA,
  690. },
  691. };
  692. struct platform_device pxa27x_device_ssp2 = {
  693. .name = "pxa27x-ssp",
  694. .id = 1,
  695. .dev = {
  696. .dma_mask = &pxa27x_ssp2_dma_mask,
  697. .coherent_dma_mask = DMA_BIT_MASK(32),
  698. },
  699. .resource = pxa27x_resource_ssp2,
  700. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  701. };
  702. static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
  703. static struct resource pxa27x_resource_ssp3[] = {
  704. [0] = {
  705. .start = 0x41900000,
  706. .end = 0x4190003f,
  707. .flags = IORESOURCE_MEM,
  708. },
  709. [1] = {
  710. .start = IRQ_SSP3,
  711. .end = IRQ_SSP3,
  712. .flags = IORESOURCE_IRQ,
  713. },
  714. [2] = {
  715. /* DRCMR for RX */
  716. .start = 66,
  717. .end = 66,
  718. .flags = IORESOURCE_DMA,
  719. },
  720. [3] = {
  721. /* DRCMR for TX */
  722. .start = 67,
  723. .end = 67,
  724. .flags = IORESOURCE_DMA,
  725. },
  726. };
  727. struct platform_device pxa27x_device_ssp3 = {
  728. .name = "pxa27x-ssp",
  729. .id = 2,
  730. .dev = {
  731. .dma_mask = &pxa27x_ssp3_dma_mask,
  732. .coherent_dma_mask = DMA_BIT_MASK(32),
  733. },
  734. .resource = pxa27x_resource_ssp3,
  735. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  736. };
  737. static struct resource pxa27x_resource_pwm0[] = {
  738. [0] = {
  739. .start = 0x40b00000,
  740. .end = 0x40b0001f,
  741. .flags = IORESOURCE_MEM,
  742. },
  743. };
  744. struct platform_device pxa27x_device_pwm0 = {
  745. .name = "pxa27x-pwm",
  746. .id = 0,
  747. .resource = pxa27x_resource_pwm0,
  748. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
  749. };
  750. static struct resource pxa27x_resource_pwm1[] = {
  751. [0] = {
  752. .start = 0x40c00000,
  753. .end = 0x40c0001f,
  754. .flags = IORESOURCE_MEM,
  755. },
  756. };
  757. struct platform_device pxa27x_device_pwm1 = {
  758. .name = "pxa27x-pwm",
  759. .id = 1,
  760. .resource = pxa27x_resource_pwm1,
  761. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
  762. };
  763. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx || CONFIG_PXA95x*/
  764. #ifdef CONFIG_PXA3xx
  765. static struct resource pxa3xx_resources_mci2[] = {
  766. [0] = {
  767. .start = 0x42000000,
  768. .end = 0x42000fff,
  769. .flags = IORESOURCE_MEM,
  770. },
  771. [1] = {
  772. .start = IRQ_MMC2,
  773. .end = IRQ_MMC2,
  774. .flags = IORESOURCE_IRQ,
  775. },
  776. [2] = {
  777. .start = 93,
  778. .end = 93,
  779. .flags = IORESOURCE_DMA,
  780. },
  781. [3] = {
  782. .start = 94,
  783. .end = 94,
  784. .flags = IORESOURCE_DMA,
  785. },
  786. };
  787. struct platform_device pxa3xx_device_mci2 = {
  788. .name = "pxa2xx-mci",
  789. .id = 1,
  790. .dev = {
  791. .dma_mask = &pxamci_dmamask,
  792. .coherent_dma_mask = 0xffffffff,
  793. },
  794. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
  795. .resource = pxa3xx_resources_mci2,
  796. };
  797. void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
  798. {
  799. pxa_register_device(&pxa3xx_device_mci2, info);
  800. }
  801. static struct resource pxa3xx_resources_mci3[] = {
  802. [0] = {
  803. .start = 0x42500000,
  804. .end = 0x42500fff,
  805. .flags = IORESOURCE_MEM,
  806. },
  807. [1] = {
  808. .start = IRQ_MMC3,
  809. .end = IRQ_MMC3,
  810. .flags = IORESOURCE_IRQ,
  811. },
  812. [2] = {
  813. .start = 100,
  814. .end = 100,
  815. .flags = IORESOURCE_DMA,
  816. },
  817. [3] = {
  818. .start = 101,
  819. .end = 101,
  820. .flags = IORESOURCE_DMA,
  821. },
  822. };
  823. struct platform_device pxa3xx_device_mci3 = {
  824. .name = "pxa2xx-mci",
  825. .id = 2,
  826. .dev = {
  827. .dma_mask = &pxamci_dmamask,
  828. .coherent_dma_mask = 0xffffffff,
  829. },
  830. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
  831. .resource = pxa3xx_resources_mci3,
  832. };
  833. void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
  834. {
  835. pxa_register_device(&pxa3xx_device_mci3, info);
  836. }
  837. static struct resource pxa3xx_resources_gcu[] = {
  838. {
  839. .start = 0x54000000,
  840. .end = 0x54000fff,
  841. .flags = IORESOURCE_MEM,
  842. },
  843. {
  844. .start = IRQ_GCU,
  845. .end = IRQ_GCU,
  846. .flags = IORESOURCE_IRQ,
  847. },
  848. };
  849. static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
  850. struct platform_device pxa3xx_device_gcu = {
  851. .name = "pxa3xx-gcu",
  852. .id = -1,
  853. .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
  854. .resource = pxa3xx_resources_gcu,
  855. .dev = {
  856. .dma_mask = &pxa3xx_gcu_dmamask,
  857. .coherent_dma_mask = 0xffffffff,
  858. },
  859. };
  860. #endif /* CONFIG_PXA3xx */
  861. #if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
  862. static struct resource pxa3xx_resources_i2c_power[] = {
  863. {
  864. .start = 0x40f500c0,
  865. .end = 0x40f500d3,
  866. .flags = IORESOURCE_MEM,
  867. }, {
  868. .start = IRQ_PWRI2C,
  869. .end = IRQ_PWRI2C,
  870. .flags = IORESOURCE_IRQ,
  871. },
  872. };
  873. struct platform_device pxa3xx_device_i2c_power = {
  874. .name = "pxa3xx-pwri2c",
  875. .id = 1,
  876. .resource = pxa3xx_resources_i2c_power,
  877. .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
  878. };
  879. static struct resource pxa3xx_resources_nand[] = {
  880. [0] = {
  881. .start = 0x43100000,
  882. .end = 0x43100053,
  883. .flags = IORESOURCE_MEM,
  884. },
  885. [1] = {
  886. .start = IRQ_NAND,
  887. .end = IRQ_NAND,
  888. .flags = IORESOURCE_IRQ,
  889. },
  890. [2] = {
  891. /* DRCMR for Data DMA */
  892. .start = 97,
  893. .end = 97,
  894. .flags = IORESOURCE_DMA,
  895. },
  896. [3] = {
  897. /* DRCMR for Command DMA */
  898. .start = 99,
  899. .end = 99,
  900. .flags = IORESOURCE_DMA,
  901. },
  902. };
  903. static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
  904. struct platform_device pxa3xx_device_nand = {
  905. .name = "pxa3xx-nand",
  906. .id = -1,
  907. .dev = {
  908. .dma_mask = &pxa3xx_nand_dma_mask,
  909. .coherent_dma_mask = DMA_BIT_MASK(32),
  910. },
  911. .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
  912. .resource = pxa3xx_resources_nand,
  913. };
  914. void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
  915. {
  916. pxa_register_device(&pxa3xx_device_nand, info);
  917. }
  918. static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
  919. static struct resource pxa3xx_resource_ssp4[] = {
  920. [0] = {
  921. .start = 0x41a00000,
  922. .end = 0x41a0003f,
  923. .flags = IORESOURCE_MEM,
  924. },
  925. [1] = {
  926. .start = IRQ_SSP4,
  927. .end = IRQ_SSP4,
  928. .flags = IORESOURCE_IRQ,
  929. },
  930. [2] = {
  931. /* DRCMR for RX */
  932. .start = 2,
  933. .end = 2,
  934. .flags = IORESOURCE_DMA,
  935. },
  936. [3] = {
  937. /* DRCMR for TX */
  938. .start = 3,
  939. .end = 3,
  940. .flags = IORESOURCE_DMA,
  941. },
  942. };
  943. struct platform_device pxa3xx_device_ssp4 = {
  944. /* PXA3xx SSP is basically equivalent to PXA27x */
  945. .name = "pxa27x-ssp",
  946. .id = 3,
  947. .dev = {
  948. .dma_mask = &pxa3xx_ssp4_dma_mask,
  949. .coherent_dma_mask = DMA_BIT_MASK(32),
  950. },
  951. .resource = pxa3xx_resource_ssp4,
  952. .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
  953. };
  954. #endif /* CONFIG_PXA3xx || CONFIG_PXA95x */
  955. struct resource pxa_resource_gpio[] = {
  956. {
  957. .start = 0x40e00000,
  958. .end = 0x40e0ffff,
  959. .flags = IORESOURCE_MEM,
  960. }, {
  961. .start = IRQ_GPIO0,
  962. .end = IRQ_GPIO0,
  963. .name = "gpio0",
  964. .flags = IORESOURCE_IRQ,
  965. }, {
  966. .start = IRQ_GPIO1,
  967. .end = IRQ_GPIO1,
  968. .name = "gpio1",
  969. .flags = IORESOURCE_IRQ,
  970. }, {
  971. .start = IRQ_GPIO_2_x,
  972. .end = IRQ_GPIO_2_x,
  973. .name = "gpio_mux",
  974. .flags = IORESOURCE_IRQ,
  975. },
  976. };
  977. struct platform_device pxa_device_gpio = {
  978. .name = "pxa-gpio",
  979. .id = -1,
  980. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  981. .resource = pxa_resource_gpio,
  982. };
  983. /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  984. * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
  985. void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
  986. {
  987. struct platform_device *pd;
  988. pd = platform_device_alloc("pxa2xx-spi", id);
  989. if (pd == NULL) {
  990. printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
  991. id);
  992. return;
  993. }
  994. pd->dev.platform_data = info;
  995. platform_device_add(pd);
  996. }