cpufreq-pxa3xx.c 6.4 KB

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  1. /*
  2. * linux/arch/arm/mach-pxa/cpufreq-pxa3xx.c
  3. *
  4. * Copyright (C) 2008 Marvell International Ltd.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/sched.h>
  14. #include <linux/init.h>
  15. #include <linux/cpufreq.h>
  16. #include <linux/slab.h>
  17. #include <linux/io.h>
  18. #include <mach/pxa3xx-regs.h>
  19. #include "generic.h"
  20. #define HSS_104M (0)
  21. #define HSS_156M (1)
  22. #define HSS_208M (2)
  23. #define HSS_312M (3)
  24. #define SMCFS_78M (0)
  25. #define SMCFS_104M (2)
  26. #define SMCFS_208M (5)
  27. #define SFLFS_104M (0)
  28. #define SFLFS_156M (1)
  29. #define SFLFS_208M (2)
  30. #define SFLFS_312M (3)
  31. #define XSPCLK_156M (0)
  32. #define XSPCLK_NONE (3)
  33. #define DMCFS_26M (0)
  34. #define DMCFS_260M (3)
  35. struct pxa3xx_freq_info {
  36. unsigned int cpufreq_mhz;
  37. unsigned int core_xl : 5;
  38. unsigned int core_xn : 3;
  39. unsigned int hss : 2;
  40. unsigned int dmcfs : 2;
  41. unsigned int smcfs : 3;
  42. unsigned int sflfs : 2;
  43. unsigned int df_clkdiv : 3;
  44. int vcc_core; /* in mV */
  45. int vcc_sram; /* in mV */
  46. };
  47. #define OP(cpufreq, _xl, _xn, _hss, _dmc, _smc, _sfl, _dfi, vcore, vsram) \
  48. { \
  49. .cpufreq_mhz = cpufreq, \
  50. .core_xl = _xl, \
  51. .core_xn = _xn, \
  52. .hss = HSS_##_hss##M, \
  53. .dmcfs = DMCFS_##_dmc##M, \
  54. .smcfs = SMCFS_##_smc##M, \
  55. .sflfs = SFLFS_##_sfl##M, \
  56. .df_clkdiv = _dfi, \
  57. .vcc_core = vcore, \
  58. .vcc_sram = vsram, \
  59. }
  60. static struct pxa3xx_freq_info pxa300_freqs[] = {
  61. /* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
  62. OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
  63. OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
  64. OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
  65. OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
  66. };
  67. static struct pxa3xx_freq_info pxa320_freqs[] = {
  68. /* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
  69. OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
  70. OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
  71. OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
  72. OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
  73. OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
  74. };
  75. static unsigned int pxa3xx_freqs_num;
  76. static struct pxa3xx_freq_info *pxa3xx_freqs;
  77. static struct cpufreq_frequency_table *pxa3xx_freqs_table;
  78. static int setup_freqs_table(struct cpufreq_policy *policy,
  79. struct pxa3xx_freq_info *freqs, int num)
  80. {
  81. struct cpufreq_frequency_table *table;
  82. int i;
  83. table = kzalloc((num + 1) * sizeof(*table), GFP_KERNEL);
  84. if (table == NULL)
  85. return -ENOMEM;
  86. for (i = 0; i < num; i++) {
  87. table[i].index = i;
  88. table[i].frequency = freqs[i].cpufreq_mhz * 1000;
  89. }
  90. table[num].index = i;
  91. table[num].frequency = CPUFREQ_TABLE_END;
  92. pxa3xx_freqs = freqs;
  93. pxa3xx_freqs_num = num;
  94. pxa3xx_freqs_table = table;
  95. return cpufreq_frequency_table_cpuinfo(policy, table);
  96. }
  97. static void __update_core_freq(struct pxa3xx_freq_info *info)
  98. {
  99. uint32_t mask = ACCR_XN_MASK | ACCR_XL_MASK;
  100. uint32_t accr = ACCR;
  101. uint32_t xclkcfg;
  102. accr &= ~(ACCR_XN_MASK | ACCR_XL_MASK | ACCR_XSPCLK_MASK);
  103. accr |= ACCR_XN(info->core_xn) | ACCR_XL(info->core_xl);
  104. /* No clock until core PLL is re-locked */
  105. accr |= ACCR_XSPCLK(XSPCLK_NONE);
  106. xclkcfg = (info->core_xn == 2) ? 0x3 : 0x2; /* turbo bit */
  107. ACCR = accr;
  108. __asm__("mcr p14, 0, %0, c6, c0, 0\n" : : "r"(xclkcfg));
  109. while ((ACSR & mask) != (accr & mask))
  110. cpu_relax();
  111. }
  112. static void __update_bus_freq(struct pxa3xx_freq_info *info)
  113. {
  114. uint32_t mask;
  115. uint32_t accr = ACCR;
  116. mask = ACCR_SMCFS_MASK | ACCR_SFLFS_MASK | ACCR_HSS_MASK |
  117. ACCR_DMCFS_MASK;
  118. accr &= ~mask;
  119. accr |= ACCR_SMCFS(info->smcfs) | ACCR_SFLFS(info->sflfs) |
  120. ACCR_HSS(info->hss) | ACCR_DMCFS(info->dmcfs);
  121. ACCR = accr;
  122. while ((ACSR & mask) != (accr & mask))
  123. cpu_relax();
  124. }
  125. static int pxa3xx_cpufreq_verify(struct cpufreq_policy *policy)
  126. {
  127. return cpufreq_frequency_table_verify(policy, pxa3xx_freqs_table);
  128. }
  129. static unsigned int pxa3xx_cpufreq_get(unsigned int cpu)
  130. {
  131. return pxa3xx_get_clk_frequency_khz(0);
  132. }
  133. static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy,
  134. unsigned int target_freq,
  135. unsigned int relation)
  136. {
  137. struct pxa3xx_freq_info *next;
  138. struct cpufreq_freqs freqs;
  139. unsigned long flags;
  140. int idx;
  141. if (policy->cpu != 0)
  142. return -EINVAL;
  143. /* Lookup the next frequency */
  144. if (cpufreq_frequency_table_target(policy, pxa3xx_freqs_table,
  145. target_freq, relation, &idx))
  146. return -EINVAL;
  147. next = &pxa3xx_freqs[idx];
  148. freqs.old = policy->cur;
  149. freqs.new = next->cpufreq_mhz * 1000;
  150. freqs.cpu = policy->cpu;
  151. pr_debug("CPU frequency from %d MHz to %d MHz%s\n",
  152. freqs.old / 1000, freqs.new / 1000,
  153. (freqs.old == freqs.new) ? " (skipped)" : "");
  154. if (freqs.old == target_freq)
  155. return 0;
  156. cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
  157. local_irq_save(flags);
  158. __update_core_freq(next);
  159. __update_bus_freq(next);
  160. local_irq_restore(flags);
  161. cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
  162. return 0;
  163. }
  164. static int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
  165. {
  166. int ret = -EINVAL;
  167. /* set default policy and cpuinfo */
  168. policy->cpuinfo.min_freq = 104000;
  169. policy->cpuinfo.max_freq = (cpu_is_pxa320()) ? 806000 : 624000;
  170. policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
  171. policy->max = pxa3xx_get_clk_frequency_khz(0);
  172. policy->cur = policy->min = policy->max;
  173. if (cpu_is_pxa300() || cpu_is_pxa310())
  174. ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa300_freqs));
  175. if (cpu_is_pxa320())
  176. ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa320_freqs));
  177. if (ret) {
  178. pr_err("failed to setup frequency table\n");
  179. return ret;
  180. }
  181. pr_info("CPUFREQ support for PXA3xx initialized\n");
  182. return 0;
  183. }
  184. static struct cpufreq_driver pxa3xx_cpufreq_driver = {
  185. .verify = pxa3xx_cpufreq_verify,
  186. .target = pxa3xx_cpufreq_set,
  187. .init = pxa3xx_cpufreq_init,
  188. .get = pxa3xx_cpufreq_get,
  189. .name = "pxa3xx-cpufreq",
  190. };
  191. static int __init cpufreq_init(void)
  192. {
  193. if (cpu_is_pxa3xx())
  194. return cpufreq_register_driver(&pxa3xx_cpufreq_driver);
  195. return 0;
  196. }
  197. module_init(cpufreq_init);
  198. static void __exit cpufreq_exit(void)
  199. {
  200. cpufreq_unregister_driver(&pxa3xx_cpufreq_driver);
  201. }
  202. module_exit(cpufreq_exit);
  203. MODULE_DESCRIPTION("CPU frequency scaling driver for PXA3xx");
  204. MODULE_LICENSE("GPL");